US4527256A - Electrically erasable memory matrix (EEPROM) - Google Patents

Electrically erasable memory matrix (EEPROM) Download PDF

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Publication number
US4527256A
US4527256A US06/470,759 US47075983A US4527256A US 4527256 A US4527256 A US 4527256A US 47075983 A US47075983 A US 47075983A US 4527256 A US4527256 A US 4527256A
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potential
function
transistors
block
accordance
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Expired - Fee Related
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US06/470,759
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English (en)
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Burkhard Giebel
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ITT Inc
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ITT Industries Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/24—Bit-line control circuits

Definitions

  • EEPROM electrically erasable memory matrix
  • Each of the storage cells comprises a tunnel injector which is capable of tunnelling electrons through a sufficiently thin oxide layer, in both directions towards an electrically floating gate electrode.
  • the injector of each storage cell is connected, on one hand, via the source-drain line of a memory transistor, to a first bit line and on the other hand, via the source-drain line of a selection FET, to a second bit line, while the control gate of the memory transistor is connected to a programming line.
  • the gate of the selection FET is connected to a row select line via which, in a row-wise manner, the n storage cells of each row can be selected.
  • these are arranged in groups of b storage cells each.
  • the storage groups are organized in w blocks of b columns each and n rows each.
  • the control gates of the b memory transistors of each group are connected to a common programming line and, via the source-drain line of a group selection transistor, are connected in blocks to one common block line.
  • the gate of the group selection transistor is connected to the corresponding row selection line. In this way, a blockwise selection of the groups of each block becomes possible.
  • the storage cells are contacted in a columnwise manner with each time one throughgoing first and second bit line, and the block line is connected to a block signal source via the source-drain line of a block selection transistor whose gate is connected to one of w outputs of a block decoder, per block.
  • the outputs of the block decoder are connected to the gates of b column selection transistors whose source-drain lines, in turn, each time connect one of the second bit lines of each block to one of the data lines.
  • the invention relates to an electrically erasable memory matrix as set forth in the preamble of claim 1.
  • the invention is based on the idea of electrically separating the first bit lines from one another.
  • the above-mentioned object is achieved by taking the measures set forth in the characterizing part of claim 1.
  • a clamping gate consisting of the source-drain parallel arrangement of a transistor of the enhancement type with a transistor of the depletion type.
  • the first bit lines are high-resistively connected to ground, so that excessive currents at the end of the writing process, and any interferences caused thereby during the reprogramming, in non-selected groups are avoided in a simple way.
  • FIGS. 1 and 2 of the accompanying drawings in which:
  • FIG. 1 schematically shows the storage cell as used with the memory matrix according to the invention
  • FIG. 2 shows the basic circuit diagram of the electrically erasable memory matrix according to the invention.
  • This storage cell comprises a memory transistor Ts with a potentially floating gate electrode Fg on which, by means of a tunnel oxide area in a thickness of less than 200 ⁇ , and injector I is realized on the drain region of the memory transistor Ts.
  • a tunnel oxide area Through the tunnel oxide area, electrons can be injected in both directions either into or out of the potentially floating gate electrode Fg.
  • the direction of the charge carrier injection merely depends on the potentials of both the control gate Gs of the memory transistor Ts and the drain electrode.
  • a Fowler-Nordheim-tunnelling of electrons by oxides 200 ⁇ thick can already be accomplished with potentials of less than 20 V.
  • a selection FET Ta whose gate is connected to a row selection line Z.
  • the control gate Gs of the memory transistor is connected to a programming line P.
  • the source-drain line of the memory transistor Ts is arranged, on the one hand, between the injector I and a first bit line X, whereas, on the other hand, the injector is connected via the source-drain line of the selection FET Ta, to a second bit line Y.
  • FIG. 2 illustrates the matrix-like arrangement of the storage cells M11 to Mmn, as well as the wiring to the peripheral circuit shown in the form of blocks, which consists of a row decoder Dz, of a block signal source Bs, of a block decoder Db, of an X-clamping signal source Kx, of an Y-clamping signal source Ky, and of a data circuit E/A, (I/0).
  • the storage cells are assembled to groups of b storage cells each, on each time one common programming line P11 . . . Pwn, to which the control gates of the memory transistors are applied.
  • the groups are arranged in blocks having each time one common block line B1 . . .
  • the group selection transistors just like the block selection transistors Tb1 . . . Tbw, are designed as insulated-gate field-effect transistors of the depletion type.
  • the last mentioned transistors connect in a blockwise fashion, the block lines B1 . . . Bw to the block signal source Bs.
  • the selection of one of the rows is accomplished with the aid of the row decoder Dz via the respective one of the row selection lines Z1 . . . Zn which is connected to the gates of the group selection transistors T11 . . . Twn, as well as to the gate electrodes of the selection transistors Ta of the associated row.
  • the blocks are selected with the aid of the block decoder Db, with the outputs S1 . . . Sw thereof being connected to the gates of the associated block selection transistors Tb1 . . . Tbw, as well as in blocks to the gates of b column selection transistors T1 s . . . Tm s .
  • the second bit lines Y1 . . . Ym of a block to be optionally connected to the data lines.L1 . . . Lb of the data circuit E/A (I/0) via which the data are fed in and read out.
  • the data lines are connected to a read (sense) amplifier which supplies a constant voltage of approximately 2 V, as is shown in FIG. 2.
  • the data circuit E/A (I/0) comprises the data input Ed and the data output Ad.
  • each of the m first bit lines X1 . . . Xm and ground there is arranged between each of the m first bit lines X1 . . . Xm and ground, the switching section of one of m clamping gates G1 . . . Gm.
  • Each clamping gate contains the source-drain parallel arrangement of a field-effect transistor of the enhancement type with a field-effect transistor of the depletion type.
  • One such clamping gate provides the possibility to apply the individual first bit lines X1 . . . Xm optionally either in a high-or low-ohmic manner to ground.
  • the potentials required to this end, for V1 identical or almost identical to the ground potential Vo, or else for V2 identical or almost identical to the operating potential Vcc, are supplied by the X-clamping signal source Kx.
  • the second bit lines Y1 . . . Ym have to be applied to ground, one of the clamping transistors Tk1 . . . Tkm is connected to each of the second bit lines Y1 . . . Ym, with the gates of the clamping transistors being controlled by a Y-clamping signal source Ky in accordance with V3 ⁇ Vo or V4 ⁇ Vcc.
  • the X-clamping signal source Kx as well as the Y-clamping signal source Ky supply a potential near that of the ground potential, so that the associated clamping transistor is blocked, and the respective clamping gate comprises a source-drain resistance corresponding to the high-ohmic resistance of the field-effect transistor of the depletion type.
  • the block decoder Db contains w NOR decoder circuit parts whose outputs are connected to the individual block selection lines S1 . . . Sw.
  • the block signal source Bs optionally makes available one of three potentials, i.e. V8 identical or almost identical to the ground potential Vo, V9 identical to the read voltage V L , or V10 identical to the potential Vp of the programming voltage source.
  • a read voltage V L can be chosen to be identical to the ground potential Vo, in cases where the memory transistors Ts on the substrate surface below the control gate, have such a concentration of dopings of the conductivity type of the source or drain regions, that prior to the first programming of the cells, in one such cell with the programming lines applied to ground potential, and first bit lines when applying a potential against ground to the second bit lines, a current will respectively flow through the source-drain line of the individual cells.
  • the extensive interference immunity of a memory matrix according to the invention and as shown in FIG. 2 results from the fact that during the re-programming processes the potential on the programming lines P of non-selected groups is a potential corresponding in the utmost to the amount of the application voltage of a group selection transistor T11 . . . Twn of about 3 V, and that on the first bit line X there may appear a potential corresponding in the utmost to the application voltage of a "written", hence of a memory transistor set to the logic zero, of about 7 V. It is moreover safeguarded that on the row selection lines Z1 . . . Zn there appears a re-programming potential amounting to the supply voltage Vp and, on the second bit lines Y1 . . . Ym, a reprogramming potential amounting to the supply voltage Vp reduced by an application voltage of about 3 V of the involved field-effect transistor of the depletion type, i.e., at the smallest current intake from the supply source.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
US06/470,759 1982-03-17 1983-02-28 Electrically erasable memory matrix (EEPROM) Expired - Fee Related US4527256A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP82102142.5 1982-03-17
EP82102142A EP0088815B1 (de) 1982-03-17 1982-03-17 Elektrisch löschbare Speichermatrix (EEPROM)

Publications (1)

Publication Number Publication Date
US4527256A true US4527256A (en) 1985-07-02

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Application Number Title Priority Date Filing Date
US06/470,759 Expired - Fee Related US4527256A (en) 1982-03-17 1983-02-28 Electrically erasable memory matrix (EEPROM)

Country Status (4)

Country Link
US (1) US4527256A (enrdf_load_stackoverflow)
EP (1) EP0088815B1 (enrdf_load_stackoverflow)
JP (1) JPS58171799A (enrdf_load_stackoverflow)
DE (1) DE3267974D1 (enrdf_load_stackoverflow)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4677590A (en) * 1981-12-29 1987-06-30 Fujitsu Limited Nonvolatile semiconductor memory circuit including dummy sense amplifiers
US4694433A (en) * 1984-05-14 1987-09-15 International Business Machines Corporation Semiconductor memory having subarrays and partial word lines
US4901281A (en) * 1985-08-16 1990-02-13 Fujitsu Limited Semiconductor memory device having two column transfer gate transistor groups independently provided for a sense amplifier and a programmed circuit
US5109361A (en) * 1989-11-30 1992-04-28 Samsung Electronics Co., Ltd. Electrically page erasable and programmable read only memory
US5229963A (en) * 1988-09-21 1993-07-20 Kabushiki Kaisha Toshiba Semiconductor nonvolatile memory device for controlling the potentials on bit lines
US5291439A (en) * 1991-09-12 1994-03-01 International Business Machines Corporation Semiconductor memory cell and memory array with inversion layer
US5377151A (en) * 1990-09-29 1994-12-27 Nec Corporation Semiconductor memory device having low-noise sense structure
US5463583A (en) * 1989-06-30 1995-10-31 Fujitsu Limited Non-volatile semiconductor memory device
US5515320A (en) * 1994-07-28 1996-05-07 Nec Corporation Non-volatile memory
US5719806A (en) * 1991-02-18 1998-02-17 Yamane; Masatoshi Memory cell array
US20060023509A1 (en) * 2004-07-30 2006-02-02 Seiko Epson Corporation Nonvolatile memory device and data write method for nonvolatile memory device
US20090307140A1 (en) * 2008-06-06 2009-12-10 Upendra Mardikar Mobile device over-the-air (ota) registration and point-of-sale (pos) payment
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US11595820B2 (en) 2011-09-02 2023-02-28 Paypal, Inc. Secure elements broker (SEB) for application communication channel selector optimization

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3277715D1 (en) * 1982-08-06 1987-12-23 Itt Ind Gmbh Deutsche Electrically programmable memory array
JPH0743948B2 (ja) * 1985-08-16 1995-05-15 三菱電機株式会社 半導体記憶装置
JPS62298997A (ja) * 1986-06-18 1987-12-26 Seiko Instr & Electronics Ltd 不揮発性ｒａｍ
IT1214246B (it) * 1987-05-27 1990-01-10 Sgs Microelettronica Spa Dispositivo di memoria non volatile ad elevato numero di cicli di modifica.

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4441168A (en) * 1982-01-13 1984-04-03 Sperry Corporation Storage logic/array (SLA) circuit
US4441169A (en) * 1981-02-25 1984-04-03 Tokyo Shibaura Denki Kabushiki Kaisha Static random access memory having a read out control circuit connected to a memory cell

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4266283A (en) * 1979-02-16 1981-05-05 Intel Corporation Electrically alterable read-mostly memory
DE3103807A1 (de) * 1980-02-04 1981-12-24 Texas Instruments Inc., 75222 Dallas, Tex. "1-aus-n-decoder fuer einen halbleiterspeicher o.dgl., verfahren zum auswaehlen von einer aus n leitungen in einer matrix und adressdecodierschaltungsanordnung"
US4317110A (en) * 1980-06-30 1982-02-23 Rca Corporation Multi-mode circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4441169A (en) * 1981-02-25 1984-04-03 Tokyo Shibaura Denki Kabushiki Kaisha Static random access memory having a read out control circuit connected to a memory cell
US4441168A (en) * 1982-01-13 1984-04-03 Sperry Corporation Storage logic/array (SLA) circuit

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4677590A (en) * 1981-12-29 1987-06-30 Fujitsu Limited Nonvolatile semiconductor memory circuit including dummy sense amplifiers
US4694433A (en) * 1984-05-14 1987-09-15 International Business Machines Corporation Semiconductor memory having subarrays and partial word lines
US4901281A (en) * 1985-08-16 1990-02-13 Fujitsu Limited Semiconductor memory device having two column transfer gate transistor groups independently provided for a sense amplifier and a programmed circuit
US5229963A (en) * 1988-09-21 1993-07-20 Kabushiki Kaisha Toshiba Semiconductor nonvolatile memory device for controlling the potentials on bit lines
US5463583A (en) * 1989-06-30 1995-10-31 Fujitsu Limited Non-volatile semiconductor memory device
US5109361A (en) * 1989-11-30 1992-04-28 Samsung Electronics Co., Ltd. Electrically page erasable and programmable read only memory
US5377151A (en) * 1990-09-29 1994-12-27 Nec Corporation Semiconductor memory device having low-noise sense structure
US5719806A (en) * 1991-02-18 1998-02-17 Yamane; Masatoshi Memory cell array
US5291439A (en) * 1991-09-12 1994-03-01 International Business Machines Corporation Semiconductor memory cell and memory array with inversion layer
US5515320A (en) * 1994-07-28 1996-05-07 Nec Corporation Non-volatile memory
US20060023509A1 (en) * 2004-07-30 2006-02-02 Seiko Epson Corporation Nonvolatile memory device and data write method for nonvolatile memory device
US7292475B2 (en) * 2004-07-30 2007-11-06 Seiko Epson Corporation Nonvolatile memory device and data write method for nonvolatile memory device
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US20090307140A1 (en) * 2008-06-06 2009-12-10 Upendra Mardikar Mobile device over-the-air (ota) registration and point-of-sale (pos) payment
US11521194B2 (en) 2008-06-06 2022-12-06 Paypal, Inc. Trusted service manager (TSM) architectures and methods
US11595820B2 (en) 2011-09-02 2023-02-28 Paypal, Inc. Secure elements broker (SEB) for application communication channel selector optimization
US12022290B2 (en) 2011-09-02 2024-06-25 Paypal, Inc. Secure elements broker (SEB) for application communication channel selector optimization

Also Published As

Publication number Publication date
DE3267974D1 (en) 1986-01-30
JPS58171799A (ja) 1983-10-08
JPH0234120B2 (enrdf_load_stackoverflow) 1990-08-01
EP0088815B1 (de) 1985-12-18
EP0088815A1 (de) 1983-09-21

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