US4513431A - Charge coupled device output circuit structure - Google Patents

Charge coupled device output circuit structure Download PDF

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Publication number
US4513431A
US4513431A US06/385,587 US38558782A US4513431A US 4513431 A US4513431 A US 4513431A US 38558782 A US38558782 A US 38558782A US 4513431 A US4513431 A US 4513431A
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Prior art keywords
electrodes
floating diffusion
electrode
diffusion
output
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Expired - Fee Related
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US06/385,587
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English (en)
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Savvas G. Chamberlain
Eugene S. Schlig
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International Business Machines Corp
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International Business Machines Corp
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Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: CHAMBERLAIN, SAVVAS G., SCHLIG, EUGENE S.
Priority to EP83102356A priority patent/EP0096166B1/de
Priority to DE8383102356T priority patent/DE3377316D1/de
Priority to JP58067175A priority patent/JPS58216464A/ja
Application granted granted Critical
Publication of US4513431A publication Critical patent/US4513431A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/762—Charge transfer devices
    • H01L29/765—Charge-coupled devices
    • H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
    • H01L29/76816—Output structures

Definitions

  • the invention relates to Charge Coupled Device (CCD) structure and it particularly pertains to such structures for use in the output circuit portion thereof.
  • CCD Charge Coupled Device
  • the structure comprises a CCD structure having a floating diffusion region from which an output signal proportional to signal charge is taken and a drain diffusion spaced apart from the output diffusion and to which the signal charge is returned as drain operating potential is applied.
  • a plurality of electrodes are interposed in typical CCD device fashion between these two final diffusions of the overall CCD structure.
  • a single direct potential biased barrier electrode is placed immediately preceding the first diffusion, and a single pulsed electrode is interposed between the two diffusions for operating as a reset gate electrode of a field effect transistor comprising the floating (source) diffusion, the gate electrode and the drain diffusion.
  • This latter arrangement resets the floating diffusion for the next charge to be processed. In doing so, however, the potential change of the floating diffusion due to signal charge is severely limited, which limitation is obviated by the arrangement according to the invention.
  • a pulsed electrode is placed immediately preceding the floating diffusion and a plurality of electrodes is interposed between the two diffusions.
  • a minimum of three interposed electrodes is recommended but four are suggested by practical design considerations and more are indicated for some designs.
  • the first such electrode beyond the output floating diffusion is operated as a reset pulse gate electrode and the last such electrode before the drain diffusion is operated as a drain pulse gate electrode, while the intermediate electrode, or electrodes, have phased clock pulses applied thereto in synchronism with such phased clock pulses applied to other electrodes of the overall CCD circuit arrangement.
  • the preceding pulsed electrode serves to extend the lower limit of the potential change of the floating diffusion.
  • the interposed electrodes permit signal charge to be transferred out of the floating diffusion into a gate-induced potential well instead of directly into the drain diffusion, extending the upper limit of potential change of the floating diffusion.
  • the drain gate isolates the drain diffusion from the preceding final CCD stages thereby obviating "charge sloshing".
  • Frye, et al disclose a pair of cross-couple CCD arrangements of the prior art that overcome some prior art problems.
  • the patent to Graham is directed to the output stage of a CCD arrangement which has an electrode doped at its outer edges in dissimilar polarity.
  • Hoffman and Mauthe show a CCD structure and a circuit arrangement which provide improved output potentials by a regenerative or positive feedback arrangement.
  • FIG. 1 is a schematic diagram of a portion of a prior art CCD structure
  • FIG. 2 is a graphical representation of the electrostatic channel potential spatially correlated to the structure to be useful in an understanding of the prior art arrangement shown in FIG. 1;
  • FIG. 3 is a schematic diagram of an output stage portion of a CCD according to the invention.
  • FIG. 4 (sections A through F being taken together) is a graphical representation of the electrostatic channel potentials also spatially correlated to the structure to be useful in an understanding of the CCD according to the invention.
  • FIG. 5 is a graphical representation of waveforms appearing in the operation of output circuitry incorporating the CCD according to the invention.
  • FIG. 1 depicts a schematic cross-section of the output stage portion of prior art "floating diffusion” CCD structure.
  • An N-channel, buried channel device is shown having a P-type silicon substrate 10 on which an N-type ion implant layer 12 is formed.
  • Layer 12 may alternatively be formed as a profiled N-type layer fabricated by means of two or more ion implantation steps.
  • An N+-type floating diffusion 14 and an N+-type drain diffusion 16 are diffused into the layer 12 over which a layer 18 of silicon dioxide insulation is formed as a base for a number of electrodes 22,25,26,27 and 28 of polysilicon material which are arranged in conventional manner as shown.
  • Output source follower and/or amplifying circuitry 30 is connected between terminals 31 and 32.
  • CCD clock pulse train phases 02,03 and 04 are applied to terminals 34,35 and 36.
  • Direct barrier potential on the order of 1 volt is applied to terminal 37 leading to the barrier electrode 24.
  • Reset pulses are applied to terminal 38 leading to the reset gate electrode 26.
  • a drain potential of the order of 8.5 v. is applied to terminal 39 leading to the diffused drain electrode 16 and substrate potential of the order of -2.2 v. is applied to the respective terminal 40.
  • FIG. 1 The structure of FIG. 1, of course, in actuality extends perpendicular to the drawing.
  • the CCD channel is delimited on its periphery by a channel-stop structure 19 as known in the art.
  • FIG. 2 shows a plot of electrostatic channel potential relative to the substrate against the spacing along the structure.
  • the potentials given are those obtained in actual practice, but these are exemplary values.
  • the change in potential of the floating diffusion, caused by the signal charge, is applied to the input terminal of the output amplifier 30, usually a source follower circuit followed by at least one amplifier circuit, and this amplified signal at the terminal 32 is the output signal of the CCD chip.
  • the source follower circuit is not a voltage amplifier, and voltage amplification at the stage following the source follower has the disadvantage of adding significant random noise to the signal.
  • FIG. 2 is a graphical representation of the channel potential levels as distributed along the CCD (in FIG. 1) for a given charge coupled transfer operation.
  • the level 200 represents the "OFF" level of a CCD stage, while the level 202 represents the “ON” level.
  • the barrier level under the electrode 24 is represented at level 204.
  • the levels 206 and 208 indicate the limits of the maximum signal potential range or swing 210 at the floating diffusion 14.
  • the reset "OFF" level is that of 212 while the "ON” level is indicated by the level 214.
  • the drain potential is indicated by the final level 216.
  • the upper limit of the potential swing at the floating diffusion electrode 14 is less than 10.7 v., while the limit imposed by the allowable maximum input voltage of the output amplifier 30 would be about 12.3 v.
  • FIG. 3 depicts a schematic cross-section of a portion of a CCD structure according to the invention shown as applied to a structure as shown in FIG. 1 for clarity in discussion, but it is the be understood that the structure in accordance with the invention is applicable to many differing CCD as well.
  • phase 2 pulses are applied to terminals 34,35 and 36 as before and phase 3 and 4 pulses are now applied at terminals 54 and 56, respectively, leading to the electrodes 44 and 46.
  • a set pulse rather than direct potential is applied to the terminal 37 leading to the barrier gate electrode 24 and now also to terminal 58 leading to a new drain gate electrode 48. Since the barrier gate 24 is a pulsed electrode, as shown in FIG. 3, it is termed a "set gate” hereinafter. Reset pulse is applied to the terminal 52 leading to the electrode 42 as was the case before with gate electrode 26 served by terminal 38. Drain and substrate potentials remain the same.
  • a structure as shown in FIG. 3 permits the floating diffusion potential swing to be increased to the difference between the latter limit of the 12.3 v. and the channel potential under the CCD gates that are "OFF", that is a potential of 8.9 v. That increased potential swing is 3.4 v. or more than four times greater than before.
  • FIGS. 4A-4F show the cross-section and potential diagrams according to the invention.
  • the set gate electrode 24 receives a low amplitude pulse instead of dc, two additional CCD electrodes 44,46 are added after the reset gate electrode 42 and connected to the same clock phases as the two gates 22,28 preceding the barrier gate 24 and a drain gate 48 is added preceding the drain diffusion 16.
  • the drain gate 48 may receive a small dc bias or, for convenience, be connected as shown to the same pulse as the set gate electrode 24.
  • CCD electrodes 44,46 between the reset and drain gates 42,48 are suggested by practical design considerations but for purposes of the invention the second electrode 46 may be eliminated. Similarly, more than two such electrodes, connected to properly sequenced phase pulses as known in the art, may be used.
  • the first signal charge packet Q1 resides under the last gate electrode 28 of the CCD device at .0.4 time.
  • the floating diffusion 14 stores only background charge and is at 12.3 v., the zero-signal level.
  • FIG. 4B .0.4 clock has turned off after the set gate electrode 24 received a positive pulse to raise its channel potential.
  • the signal Q1 transfers over the potential barrier beneath set gate electrode 24 and resides in the floating diffusion 14 and under the set gate electrode 24 which then turns off transferring the charge Q1 into the floating diffusion 14.
  • the floating diffusion potential is reduced by Q1 to 8.9 v., giving a floating diffusion potential swing of 3.4 v. as shown in FIG. 4C.
  • a pulse is applied to the reset gate electrode 42 at a time in the clock cycle when both clocks .0.3 and .0.4 are high.
  • the reset gate channel potential increases to 12.3 v., allowing the signal charge Q1 to transfer into the potential well under the electrodes 44, 46 as shown in FIG. 4D.
  • the "ON" potential under the CCD gates in an example of this design is typically 16.6 v. when no charge is present.
  • the floating diffusion 14 returns to 12.3 v.
  • the reset gate 42 turns off and then the .0.3 electrode 44 turns off; leaving the charge Q1 under the .0.4 electrode 46 as in FIG. 4E. This is the same phase of the cycle as shown in FIG. 4A, and the next signal charge packet, Q2, now resides under the last CCD .0.4 electrode 28.
  • FIG. 5 is a timing diagram showing only the essential waves helpful in an understanding of the operation of the arrangement according to the invention.
  • the relative amplitudes of the waves are not indicated in FIG. 5.
  • a curve 500 represents phase .0.4 of a four-phase clock wave applied to the electrodes 28 and 46.
  • the pulse wave applied to the set gate electrode 24 and the drain gate electrode 48 is represented by a curve 510.
  • the next curve 520 represents the pulse wave applied to the reset gate electrode 42, while curve 530 represents the phase .0.3 of the four-phase clock wave applied to electrodes 22 and 44.
  • the final curve 540 represents the output potential wave at the floating diffusion 14; the same wave appears at the output terminal 32.
  • the letters A,B . . . F refer to the FIGS. 4A, 4B, . . . 4F, respectively, and indicated the time at which the respective figures are applicable.
  • any dc biased barrier electrode is replaced with a pulsed "set gate” electrode in order to decrease the minimum allowable floating diffusion potential to the potential under gates at the clock down level, 8.9 v. in an example of an arrangement according to the invention.
  • electrodes are provided for arranging transfer of the signal charge out of the floating diffusion into a gate-induced potential well instead of directly into a drain diffusion. Since the potential well is at higher potential than the drain (16.6 v. compared to 10.7 v. in the example mentioned), the floating diffusion can be reset to a higher potential than the drain potential. That higher potential (12.3 v. in the example mentioned) is typically limited by the output amplifier design considerations.
  • drain gate which isolates the drain diffusion from the final CCD stages, avoiding "charge sloshing".

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Solid State Image Pick-Up Elements (AREA)
US06/385,587 1982-06-07 1982-06-07 Charge coupled device output circuit structure Expired - Fee Related US4513431A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
US06/385,587 US4513431A (en) 1982-06-07 1982-06-07 Charge coupled device output circuit structure
EP83102356A EP0096166B1 (de) 1982-06-07 1983-03-10 Ladungsverschiebeanordnung und Schaltung zu ihrem Betrieb
DE8383102356T DE3377316D1 (en) 1982-06-07 1983-03-10 Charge coupled device and circuit arrangement for its operation
JP58067175A JPS58216464A (ja) 1982-06-07 1983-04-18 Ｃｃｄ用出力回路構造体

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US06/385,587 US4513431A (en) 1982-06-07 1982-06-07 Charge coupled device output circuit structure

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EP (1) EP0096166B1 (de)
JP (1) JPS58216464A (de)
DE (1) DE3377316D1 (de)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4603426A (en) * 1985-04-04 1986-07-29 Rca Corporation Floating-diffusion charge sensing for buried-channel CCD using a doubled clocking voltage
EP0280097A2 (de) * 1987-02-13 1988-08-31 Kabushiki Kaisha Toshiba Ladungstransfervorrichtung mit Verstärker
US4811371A (en) * 1986-05-16 1989-03-07 Rca Corporation Floating-diffusion electrometer with adjustable sensitivity
US5227650A (en) * 1991-01-23 1993-07-13 Sony Corporation Charge coupled device delay line employing a floating gate or floating diffusion gate at its intermediate output portion
US5483282A (en) * 1992-06-18 1996-01-09 Mitsubishi Denki Kabushiki Kaisha Method for driving a linear image sensor
US5600696A (en) * 1995-10-11 1997-02-04 David Sarnoff Research Center, Inc. Dual-gain floating diffusion output amplifier
US5614740A (en) * 1991-05-10 1997-03-25 Q-Dot, Inc. High-speed peristaltic CCD imager with GaAs fet output
US5861582A (en) * 1996-01-23 1999-01-19 Synapse Technology, Inc. Patient weighing system
US6160292A (en) * 1997-04-23 2000-12-12 International Business Machines Corporation Circuit and methods to improve the operation of SOI devices

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2567831B2 (ja) * 1984-07-04 1996-12-25 株式会社東芝 電荷検出回路
JPH084136B2 (ja) * 1987-12-22 1996-01-17 日本電気株式会社 電荷転送装置
JPH07123163B2 (ja) * 1989-07-21 1995-12-25 日本電気株式会社 電荷転送装置
JP3024051U (ja) * 1995-10-24 1996-05-17 迪來企業有限公司 通用型掃除機用集塵袋

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4118795A (en) * 1976-08-27 1978-10-03 Texas Instruments Incorporated Two-phase CCD regenerator - I/O circuits
US4132903A (en) * 1977-05-12 1979-01-02 Rca Corporation CCD output circuit using thin film transistor
US4139784A (en) * 1977-08-02 1979-02-13 Rca Corporation CCD Input circuits
US4242600A (en) * 1977-05-10 1980-12-30 Siemens Aktiengesellschaft Digital CCD arrangement

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2703359A1 (de) * 1977-01-27 1978-08-03 Siemens Ag Ausgangsstufe fuer eine ladungsverschiebevorrichtung
JPS5528525A (en) * 1978-08-17 1980-02-29 Toshiba Corp Input bias control system for charge transfer element
JPS55145367A (en) * 1979-04-27 1980-11-12 Toshiba Corp Standard charge level generator for charge transfer device
JPS5946424B2 (ja) * 1979-08-31 1984-11-12 松下電器産業株式会社 電荷転送素子

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4118795A (en) * 1976-08-27 1978-10-03 Texas Instruments Incorporated Two-phase CCD regenerator - I/O circuits
US4242600A (en) * 1977-05-10 1980-12-30 Siemens Aktiengesellschaft Digital CCD arrangement
US4132903A (en) * 1977-05-12 1979-01-02 Rca Corporation CCD output circuit using thin film transistor
US4139784A (en) * 1977-08-02 1979-02-13 Rca Corporation CCD Input circuits

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4603426A (en) * 1985-04-04 1986-07-29 Rca Corporation Floating-diffusion charge sensing for buried-channel CCD using a doubled clocking voltage
US4811371A (en) * 1986-05-16 1989-03-07 Rca Corporation Floating-diffusion electrometer with adjustable sensitivity
EP0280097A2 (de) * 1987-02-13 1988-08-31 Kabushiki Kaisha Toshiba Ladungstransfervorrichtung mit Verstärker
EP0280097A3 (en) * 1987-02-13 1990-02-28 Kabushiki Kaisha Toshiba Charge transfer device with booster circuit
US5227650A (en) * 1991-01-23 1993-07-13 Sony Corporation Charge coupled device delay line employing a floating gate or floating diffusion gate at its intermediate output portion
US5614740A (en) * 1991-05-10 1997-03-25 Q-Dot, Inc. High-speed peristaltic CCD imager with GaAs fet output
US5483282A (en) * 1992-06-18 1996-01-09 Mitsubishi Denki Kabushiki Kaisha Method for driving a linear image sensor
US5600696A (en) * 1995-10-11 1997-02-04 David Sarnoff Research Center, Inc. Dual-gain floating diffusion output amplifier
WO1997014153A1 (en) * 1995-10-11 1997-04-17 Sarnoff Corporation Dual-gain floating diffusion output amplifier
US5861582A (en) * 1996-01-23 1999-01-19 Synapse Technology, Inc. Patient weighing system
US6160292A (en) * 1997-04-23 2000-12-12 International Business Machines Corporation Circuit and methods to improve the operation of SOI devices
US7405982B1 (en) 1997-04-23 2008-07-29 International Business Machines Corporation Methods to improve the operation of SOI devices

Also Published As

Publication number Publication date
JPS6233751B2 (de) 1987-07-22
DE3377316D1 (en) 1988-08-11
EP0096166A3 (en) 1986-03-19
EP0096166A2 (de) 1983-12-21
EP0096166B1 (de) 1988-07-06
JPS58216464A (ja) 1983-12-16

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