US4492989A - Time base correcting apparatus - Google Patents

Time base correcting apparatus Download PDF

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Publication number
US4492989A
US4492989A US06/465,462 US46546283A US4492989A US 4492989 A US4492989 A US 4492989A US 46546283 A US46546283 A US 46546283A US 4492989 A US4492989 A US 4492989A
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signal
address
write
data
read
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US06/465,462
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English (en)
Inventor
Nobuhiko Watanabe
Masato Tanaka
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Sony Corp
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Sony Corp
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Assigned to SONY CORPORATION,A CORP. OF JAPAN reassignment SONY CORPORATION,A CORP. OF JAPAN ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: TANAKA, MASATO, WATANABE, NOBUHIKO
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/12—Formatting, e.g. arrangement of data block or words on the record carriers
    • G11B20/1201—Formatting, e.g. arrangement of data block or words on the record carriers on tapes
    • G11B20/1202—Formatting, e.g. arrangement of data block or words on the record carriers on tapes with longitudinal tracks only
    • G11B20/1204—Formatting, e.g. arrangement of data block or words on the record carriers on tapes with longitudinal tracks only for continuous data, e.g. digitised analog information signals, pulse code modulated [PCM] data
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1806—Pulse code modulation systems for audio signals
    • G11B20/1813—Pulse code modulation systems for audio signals by adding special bits or symbols to the coded information
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/22—Signal processing not specific to the method of recording or reproducing; Circuits therefor for reducing distortions
    • G11B20/225—Signal processing not specific to the method of recording or reproducing; Circuits therefor for reducing distortions for reducing wow or flutter
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
    • G11B27/10—Indexing; Addressing; Timing or synchronising; Measuring tape travel
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/12—Formatting, e.g. arrangement of data block or words on the record carriers
    • G11B20/1201—Formatting, e.g. arrangement of data block or words on the record carriers on tapes
    • G11B20/1202—Formatting, e.g. arrangement of data block or words on the record carriers on tapes with longitudinal tracks only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B2220/00—Record carriers by type
    • G11B2220/90—Tape-like record carriers

Definitions

  • This invention generally relates to a time base correcting apparatus and more particularly relates to a time base correcting apparatus capable of correction of time base errors or variations contained in a digital signal which is formed of successive data blocks.
  • TBC time base correcting apparatus or corrector
  • the conventional TBC is provided, forming the write-in address on the basis of the synchronizing signal separated from the reproduced data. Since the synchronizing signal contained in the reproduced data is affected by a dropout, a noise and so on, the control of the write-in address based on such synchronizing signal is not made stable and hence the data of one block is written at the wrong block address with a result that the time series of data read out from the memory becomes different from that of the reproduced data. Particularly when an interleave technique is used to cope with burst errors due to dropout, the time series of the reproduced data must strictly be coincident with that upon recording. When the synchronizing signal is separated from the reproduced data, in the conventional TBC, it is proposed to eliminate the influences of dropout and noise and then to derive only the correct synchronizing signal, too. But, this is not satisfactory.
  • a phase-locked loop (PLL) servo by which upon playback the running of the magnetic tape is phase-locked to the reference signal, is made unstable by this discontinuity giving rise to a problem that it takes a long settling time for the magnetic tape to be phase-locked to the reference signal.
  • PLL phase-locked loop
  • a servo circuit in which a polyphase, for example, four-phase signal is used or a reference signal so as to enable the transportation of the magnetic tape to be phase-locked to any one phase of the four-phase reference signal.
  • a time base correcting apparatus capable of correcting time base errors contained in a digital signal supplied thereto in the form of successive data blocks with each data block including plural data words.
  • Each data block includes therein at least plural data words and a block address circulating with a predetermined phase relation relative to a certain reference signal.
  • a memory is provided, having plural addressable storage locations, each adapted to store a respective data block. Write-in addresses to identify the particular storage locations are generated according to data block addresses and read-out addresses.
  • the write-in address is varied by a lock phase mode signal indicative of a phase relation at which an incoming digital signal is locked to a reference signal so that notwithstanding the phase mode in which the digital signal is locked to the reference signal, the correction ability of the time base correcting apparatus can be prevented from being lowered.
  • FIG. 1 is a schematic diagram representing one example of track patterns from which data is reproduced and supplied to a time base correcting apparatus of the present invention
  • FIGS. 2A and 2B are timing diagrams representing various signals that are recorded as data and control tracks of a record medium with which the present invention is used;
  • FIG. 3 is a schematic diagram representing the arrangement of recording and playback transducers
  • FIG. 4 is a schematic block diagram showing an example of the time base correcting apparatus according to this invention.
  • FIGS. 5A-5D are respectively timing diagrams each used to explain a polyphase servo circuit used in one embodiment of the time base correcting apparatus according to this invention.
  • FIGS. 6A-6D are respectively schematic diagrams showing tables for a read-only memory (ROM) for generating write-in block addresses used in one embodiment of this invention.
  • ROM read-only memory
  • FIGS. 7A-7I and FIGS. 8A-8G are respectively timing diagrams each used to explain one embodiment of this invention.
  • FIG. 1 In this case, on a magnetic tape 1 of 1/4-inch width are formed 8 data tracks TD 0 to TD 7 , 2 analog tracks TA 1 and TA 2 , a control track TC and a time code track TT, respectively. On 8 data tracks TD 0 to TD 7 are recorded respective audio PCM signals of totally 8 channels, each being encoded as is determined before. As illustrated in FIG. 2A, the data tracks TD(TD 0 to TD 7 ) and the control track TC are coincident with each other at their recording positions for each sector in the width direction.
  • One sector of each of the data tracks TD includes data of 4 blocks.
  • one transmission block (simply, referred to as one block) is formed of data of 16 words, each word being formed of 16 bits, a data synchronizing signal (shown by the hatched area in FIG. 2B) added to the beginning of the data and a cyclic redundancy check (CRC) code added to its end.
  • a block address signal of 3 bits is inserted into the interval of the data synchronizing signal, and the block address signal and the data will both be detected for error by the CRC code.
  • One sector of the control track TC is comprised of a synchronizing signal of 4 bits (shown by the hatched interval in FIG.
  • a control word of 16 bits is used to identify the sampling frequency of the PCM audio signal to be recorded and the recording format and the sector address is the absolute address incrementing from 0 address, both of which will be detected for error by the CRC code.
  • a modulation method for recording the audio PCM signal on the data tracks TD there is employed a modulation system of high density recording, while an FM-modulation system or the like is employed to record a control signal on the control track TC.
  • a least significant bit S 0 of the sector address signal is adapted to be coincident with a most significant bit of each block address signal of 4 blocks. That is, the block address [B 2 B 1 B 0 ] sequentially changes so as to appear as [S 0 0 0], [S 0 0 1], [S 0 1 0] and [S 0 1 1] in that sector.
  • each transducer has 10 recording or reproducing magnetic gaps each arranged in line along the width direction of the magnetic tape 1 of which 8 magnetic gaps correspond to the data tracks TD 0 to TD 7 and the rest two magnetic gaps correspond to the control track TC and the time code track TT, respectively.
  • the first recording on the magnetic tape 1 is carried out by the recording transducer HR, and in the case of sync-recording and cut-in/-out, the recording transducer HR' is employed.
  • the control track TC once formed by the recording transducer HR is not rewritten but only the data tracks TD are rewritten.
  • FIG. 4 schematically illustrates an arrangement of an example of the time base correcting apparatus according to the present invention in which a PCM signal is reproduced by the playback transducer HP from the data tracks TD and the control track TC is reproduced by a control transducer HC.
  • the output from the control transducer HC is supplied through a playback amplifier 2 to a CTL detection circuit 3 in which a CTL (control) signal is detected by detecting a synchronizing signal of each sector.
  • This CTL signal is supplied to a waveform shape circuit 4 which then produces at its output a servo pulse.
  • This servo pulse is supplied to a D-type flip-flop circuit 5 for phase comparison as its clock input.
  • Reference numeral 6 denotes a counter for counting a clock pulse CK of which plural bits except upper 2 bits are parallel-supplied to the D-type flip-flop circuit 5 as a reference signal.
  • the upper 2 bits of the counter 6 repeatedly changes with the cycle corresponding to one sector so as to appear as 0, 1, 2 and 3, while as shown by a sawtooth wave in FIG. 5B, the lower bits thereof change their values stepwise at every clock pulses CK.
  • the reference signal of which the value changes stepwise is formed on the basis of 2's complementary code and the value thereof is changed symmetrically around the center axis 0, which is repeated four times per one sector.
  • the D-type flip-flop circuit 5 is adapted to sample any one phase of the four-phase reference signal by the servo pulse, which then produces at its output a phase comparison output and a lock mode signal.
  • the phase comparison output is supplied to an addition circuit or adder 7 and therein added with an output from a speed detection circuit 8.
  • the detection of speed is carried out such that a signal with a frequency proportional to a revolution rate of a capstan motor 9 is generated by a tachogenerator 10 and the frequency of this signal is converted in the speed detection circuit 8 into the level thereof.
  • the output from the adder 7 is converted by a digital-to-analog (D/A) converter 11 into an analog signal which is then supplied through a servo amplifier 12 to the capstan motor 9 made of a DC motor.
  • D/A digital-to-analog
  • the magnetic tape 1 is transported at the predetermined speed with its phase locked to the reference signal.
  • This phase-lock is performed for any one of 4-phase reference signal.
  • P 10 , P 11 , P 12 and P 13 respectively denote servo pulses in the state of being phase-locked to 0-th mode, first mode, second mode and third mode. Since in the D-type flip-flop circuit 5, the upper 2 bits of the counter 6 are sampled, the D-type flip-flop circuit 5 generates lock mode signals as shown in FIG. 5D in response to the servo pulse with its phase locked to the 0-th mode to the third mode.
  • the reproduced data (which is considered as data of one channel for simplicity) from the playback transducer HP is supplied through a playback amplifier 13 to a sync detection and demodulation circuit 14 from which a reproduced data and a block synchronizing signal are supplied to a delay circuit 15.
  • This delay circuit 15 is provided to match the time bases between the reproduced signal through the circuit 14 and the lock mode signals generated from the aforementioned D-type flip-flop circuit 5.
  • the reproduced data WDT and the reproduced synchronizing pulse PSY from this delay circuit 15 and the lock mode signals are supplied to the TBC.
  • numeral 16 denotes a memory or random-access memory (RAM) for the TBC.
  • the reproduced data WDT is supplied to a delay circuit 17 and a CRC (cyclic redundancy check) checker 18.
  • the CRC checker 18 checks whether the block address signal and the data at every block have errors or not and generates an error detection output EDT which takes a value "1" in the presence of the error and "0" in the absence of the error.
  • the RAM 16 stores therein the data contained in one block except the synchronizing signal and the block address signal (both are presented as SYNC in FIGS. 2A and 2B and so on) and is of a storage capacity of, for example, 8 blocks in consideration of jitter amount. This storage capacity of 8 blocks enables the correction of jitters up to ⁇ 2 blocks.
  • the RAM 16 is supplied with an input data WDT', that is derived through the delay circuit 17, a write-in control pulse WE and an address through an address selector 19, and then produces an output data RDT.
  • the address selector 19 is provided to select the write-in address or the read-out address and is switched at every predetermined interval.
  • the write-in address and the read-out address are respectively formed of a bit address and a block address.
  • the write-in address is provided by a bit address counter 20 and a block address counter 21.
  • a playback bit clock obtained from a clock extracting circuit (not shown) is supplied through a terminal 22 to the bit address counter 20.
  • a playback sync pulse PSY' appearing at the output from a delay circuit 27 is supplied to a clear terminal CL of the address counter 20 and a load terminal LD of the address counter 21.
  • a flip-flop circuit 28 to which the error detection output EDT from the CRC checker 18 is supplied at its input D is supplied at its enable terminal EN with the sync pulse PSY' and this flip-flop circuit 28 produces at its output Q the write-in control pulse WE.
  • An address generation ROM (read-only memory) 29 is further provided to generate a write-in block address WA which is then supplied to the block address counter 21 at its parallel input IN and loaded therein by the playback sync pulse PSY' applied thereto at its load terminal LD.
  • the ROM 29 generates the predetermined block address WA on the basis of the playback block address BA contained in the reproduced and the lock mode signal from the flip-flop circuit 5.
  • the read-out bit address is provided by such a manner that a bit address counter 23 is supplied with a reference bit clock through a terminal 25, while the read-out block address RA is produced in such a manner that a block address counter 24 is supplied with a reference block clock through a terminal 26.
  • the read-out block address RA is supplied to the ROM 29 as mentioned before which then generates the write-in block address WA.
  • Each of the address counters 23 and 24 is supplied at its clear terminal CL with a predetermined clear pulse.
  • An 8-bit error flag memory 30 is provided to which an incoming data is supplied from a multiplexer 31.
  • the error detection signal EDT takes a value "1" by which the data of that block is inhibited from being written.
  • the multiplexer 31 is controlled by the write-in control pulse WE such that "0" is supplied to the error flag memory 30 upon write-in operation, while in other operation, "1" is supplied thereto.
  • the output from the error flag memory 30 is supplied to a latch 32 and the output from this latch 32 is delivered as an error flag EFLG.
  • a controller 33 is provided which is supplied with the same address and write-in control pulse WE as those supplied to the RAM 16 whereby the error flag memory 30 is controlled in association with the operation of the RAM 16.
  • the 4-phase phase-locked loop (PLL) servo and the mode to which the reproduced data is locked at present is indicated by the lock mode signal, so that the ROM 29 is adapted to selectively change the tables shown in FIGS. 6A, 6B, 6C and 6D in response to each mode.
  • PLL phase-locked loop
  • the read-out block address RA sequentially changes from 0-address to 7-address as shown in FIG. 7A. If, now, the reproduced data is locked to the 0-th mode and contains no time base error, the reproduced control signal CTL becomes to have such a phase as shown in FIG. 7B. Then, the reproduced block address BA contained in the reproduced data WDT' varys sequentially so as to appear as [0] [1] [2] [3] as illustrated in FIG. 7C.
  • the ROM 29 employs the conversion table shown in FIG. 6A and produces the write-in block address WA shown in FIG.
  • the TBC is capable of correcting the errors up to ⁇ 2 blocks and the data is delayed by 4 blocks through the TBC.
  • the control signal CTL has the phase shown in FIG. 7E for the read-out block address RA of FIG. 7A and the reproduced block address BA becomes as shown in FIG. 7F.
  • the ROM 29 generates the write-in block address WA as shown in FIG. 7G.
  • the reproduced control signal CTL and the reproduced block address BA have a constant phase relation and this has nothing to do with the lock mode. But, if any positional displacement between the data track TD and the control track TC takes place due to the skew of the magnetic tape, the above phase relation is varied. For example, there may occur such a case that relative to the control signal CTL shown in FIG. 7E, the reproduced block address BA delayed by one block as shown in FIG. 7H is generated occasionally. Even in such case, the ROM 29 can generate the write-in block address WA shown in FIG. 7I on the basis of the conversion table shown in FIG. 6B.
  • FIGS. 8A to 8G When the reproduced data WDT shown in FIG. 8A is supplied from the delay circuit 15 to the CRC checker 18, this CRC checker 18 produces at the timing of the end of one block the error detection output EDT representing whether or not the block contains error shown in FIG. 8B.
  • FIG. 8A of the reproduced data WDT, there are illustrated two blocks in which the block addresses BA as [1] and [2]. Accordingly, the error detection output EDT shown in FIG. 8B is concerned with the blocks of the preceding block addresses of [0] and [1], and when the block contains error, the error detection output EDT takes a value "1" as shown by broken lines in FIG. 8B.
  • the playback sync pulse PSY shown in FIG. 8D is delivered from the delay circuit 15.
  • the bit pattern of the sync signal SYNC is selected not to appear in the data and is discriminated from the data, and so the sync signal detection circuit 14 detects this bit pattern and then produces the sync pulse PSY.
  • the sync pulse PSY is delayed by the delay circuit 27 so as to have the timing substantially coincident with that of the error detection output EDT and thereby produced from the delay circuit 27 as a sync pulse PSY' shown in FIG. 8E.
  • the bit address counter 20 is cleared up by this sync pulse PSY' and the write-in block address WA from the ROM 29 is loaded in the block address counter 21 by the sync pulse PSY'. If as mentioned before, the reproduced data is locked to the 0-th mode and contains therein no jitter, in response to the block address BA of the reproduced data WDT' being varied to [0] and [1], the write-in block address WA is varied into 4 and 5, respectively.
  • the sync pulse PSY' is applied to the enable terminal EN of the flip-flop circuit 28, the write-in control pulse WE therefrom is changed as shown in FIG. 8G.
  • the data is delayed by the delay circuit 17 such that the data is supplied to the RAM 16 after the error detection for that block was carried out. If the error detection output EDT is at "1", the data of that block is inhibited from being written.
  • the error flag memory 30 stores therein the output from the multiplexer 31 which the output becomes at "0" when the RAM 16 is in the write-in operation mode and at "1" in other mode.
  • This error flag memory 30 is a memory of 8 bits having 8 addresses from 0 to 7 which are made coincident with the block address of the RAM 16 by supplying the write-in block address WA appearing at the output from the block address counter 21 to the controller 33.
  • the error flag memory 30 is adapted to perform the write-in operation after it is confirmed that the write-in bit address of the RAM 16 takes the maximum value.
  • the reading of the error flag memory 30 is started from the address that is coincident with the read-out block address RA from the counter 24.
  • the read-out bit address is used to control the read-out timing of the memory 30 and the latch timing of the latch 32.
  • the timing is controlled such that after one bit of the predetermined address of the specified block is read out from the beginning thereof, the latch operation is performed, thus the error flag EFLG being produced from the latch 32.
  • the read-out data RDT from the RAM 16 and the error flag EFLG are synchronized with each other and so, in the encoder of the next stage, the error correction is performed by using the error flag EFLG.
  • the parity word is used as the error correction code and one word error in one code block can be corrected by the mod.2 addition of other PCM words and the parity word, requiring no error word for error correction.
  • the polyphase PLL servo is employed, even when there exist plurality of relations between the reference signal and the reproduced data, it is possible to realize the TBC capable of preventing the correction range from being narrowed. Moreover, according to this invention, the delay amount of the TBC itself can be prevented from being varied by the lock mode so that in the case of sync-recording, no disadvantage will take place.
  • the error flag memory 30 is provided separate from the RAM 16 for data, the data and the error flag may be stored in a common memory.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Error Detection And Correction (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
US06/465,462 1982-02-15 1983-02-10 Time base correcting apparatus Expired - Fee Related US4492989A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP57-22290 1982-02-15
JP57022290A JPS58139317A (ja) 1982-02-15 1982-02-15 メモリ装置

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US4492989A true US4492989A (en) 1985-01-08

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US06/465,462 Expired - Fee Related US4492989A (en) 1982-02-15 1983-02-10 Time base correcting apparatus

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US (1) US4492989A (fr)
EP (1) EP0086658B1 (fr)
JP (1) JPS58139317A (fr)
CA (1) CA1193025A (fr)
DE (1) DE3371829D1 (fr)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4613908A (en) * 1982-04-16 1986-09-23 Victor Company Of Japan, Ltd. Digital video signal reproducing apparatus
US4622600A (en) * 1983-12-26 1986-11-11 Hitachi, Ltd. Rotary-head type PCM data recording/reproducing method and apparatus with a redundancy-reduced control data format
US4823207A (en) * 1987-01-27 1989-04-18 Hitachi, Ltd. PCM recording and playback with variable read and write speeds
US4937686A (en) * 1985-11-13 1990-06-26 Hitachi, Ltd. Method and apparatus for PCM recording and reproducing an audio signal having an asynchronous relation between the sampling frequency for the audio signal and the rotation frequency of a rotary head scanner
US5062010A (en) * 1984-12-27 1991-10-29 Sony Corporation Electronic still camera with remotely-controlled audio recording feature
US20040047608A1 (en) * 2001-04-19 2004-03-11 Masamichi Takayama Digital recording/reproducing apparatus

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07101541B2 (ja) * 1983-06-28 1995-11-01 ソニー株式会社 デイジタル情報信号の記録装置
NL8303061A (nl) * 1983-09-02 1985-04-01 Philips Nv Inrichting voor het uitlezen van een optisch uitleesbare registratiedrager.
NL8303765A (nl) * 1983-11-02 1985-06-03 Philips Nv Dataverwerkend systeem waarbij in het geheugen onbetrouwbare woorden zijn vervangen door een onbetrouwbaarheidsindicator.
JPH0690853B2 (ja) * 1986-12-23 1994-11-14 ソニー株式会社 デイジタル信号の時間軸補正装置
GB9008932D0 (en) * 1990-04-20 1990-06-20 British Broadcasting Corp Synchronisation of digital audio signals

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4398224A (en) * 1980-09-05 1983-08-09 Sony Corporation Time base correcting apparatus

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4145683A (en) * 1977-11-02 1979-03-20 Minnesota Mining And Manufacturing Company Single track audio-digital recorder and circuit for use therein having error correction

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4398224A (en) * 1980-09-05 1983-08-09 Sony Corporation Time base correcting apparatus

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4613908A (en) * 1982-04-16 1986-09-23 Victor Company Of Japan, Ltd. Digital video signal reproducing apparatus
US4622600A (en) * 1983-12-26 1986-11-11 Hitachi, Ltd. Rotary-head type PCM data recording/reproducing method and apparatus with a redundancy-reduced control data format
US5062010A (en) * 1984-12-27 1991-10-29 Sony Corporation Electronic still camera with remotely-controlled audio recording feature
US4937686A (en) * 1985-11-13 1990-06-26 Hitachi, Ltd. Method and apparatus for PCM recording and reproducing an audio signal having an asynchronous relation between the sampling frequency for the audio signal and the rotation frequency of a rotary head scanner
US4823207A (en) * 1987-01-27 1989-04-18 Hitachi, Ltd. PCM recording and playback with variable read and write speeds
US20040047608A1 (en) * 2001-04-19 2004-03-11 Masamichi Takayama Digital recording/reproducing apparatus
US7603190B2 (en) * 2001-04-19 2009-10-13 Sony Corporation Digital recording/reproducing apparatus

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DE3371829D1 (en) 1987-07-02
EP0086658A2 (fr) 1983-08-24
EP0086658B1 (fr) 1987-05-27
JPH05791B2 (fr) 1993-01-06
JPS58139317A (ja) 1983-08-18
CA1193025A (fr) 1985-09-03
EP0086658A3 (en) 1984-07-25

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