US4087640A - Data input control system - Google Patents

Data input control system Download PDF

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Publication number
US4087640A
US4087640A US05/715,141 US71514176A US4087640A US 4087640 A US4087640 A US 4087640A US 71514176 A US71514176 A US 71514176A US 4087640 A US4087640 A US 4087640A
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United States
Prior art keywords
control
processor
data
control data
data input
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Expired - Lifetime
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US05/715,141
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English (en)
Inventor
Kazuyuki Sato
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Toshiba Corp
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Tokyo Shibaura Electric Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7828—Architectures of general purpose stored program computers comprising a single central processing unit without memory
    • G06F15/7835—Architectures of general purpose stored program computers comprising a single central processing unit without memory on more than one IC chip
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

Definitions

  • This invention relates generally to a data processing system, and more particularly to a data input control system for providing a processor with control data from a control storage.
  • processors integrated on a one-chip semiconductor are adapted for use in various fields.
  • a processor 2 includes a control storage (ROM) 1 therein.
  • ROM control storage
  • This type of processor does not necessarily have the flexibility of a program control system and, thus, it is only applicable to restricted fields because of the relatively small capacity and unchangeability of the control storage.
  • the second type of system shown in FIG. 1B, comprises a processor 3 and a control storage (ROM) 4 located outside the processor 3 and connected therewith through ROM address lines 5 and ROM data lines 6, wherein the processor 3 and the control storage 4 are respectively integrated on one-chip semiconductor devices.
  • ROM control storage
  • the number of the ROM address lines 5, which depends on the memory space of the control stage 4, is 11, for example, and that of the ROM data lines 6, which depends on read-out data lengths of the control storage 4, is 16, then the total number of the terminals used for them will be 27 in spite of the fact that only 42 terminals (pins), for example, are provided on one-chip semiconductor devices for conventional processors of this type. Therefore, the number of terminals that can be used for data processing purposes, other than the ROM address and data lines 5 and 6, are substantially reduced, resulting in functional deteriorations of the data processing system.
  • the number of the terminals on the processor 3 could be increased in order to overcome such functional deteriorations, but this leads to a large chip size for the processor 3 and does not meet required standards or functions thereof.
  • a data input control system wherein a processor is provided with control data from a control storage in one memory cycle time of the control storage on a time-division basis.
  • FIGS. 1A and 1B are block diagrams of prior art data processing systems
  • FIG. 2 is a block diagram of a data input control system according to this invention.
  • FIG. 3 is a waveform diagram of the data input control system shown in FIG. 2.
  • a data input control system in accordance with this invention provides a processor with control data from a control storage in a memory cycle time thereof on a time-division basis, thereby reducing the number of the required terminals of the processor.
  • the number (C) of terminals for handling the control data is determined as follows:
  • A is the access time of the control storage
  • B is the memory cycle time of the control storage
  • C is the number of control data input terminals of the processor
  • D is the bit length of the control data
  • n is the number of division times (frequency) of the control data in one memory cycle
  • T is the period of a clock pulse of the data input control system.
  • a data input control system provides a processor 11 integrated on a one-chip semiconductor device receiving control data from a control storage or ROM 12 integrated on another one-chip semiconductor device.
  • the control data comprises 16-bit data including micro-instructions, and the control storage 12 has 16 output terminals for the control data.
  • the control data are divided four groups, wherein each group comprises 4-bit lengths of bit positions 0-3, 4-7, 8-11, or 12-15.
  • the memory cycle time of the control storage 12 is, as described above, preferably 400 n sec.
  • Gates 13 1 , 13 2 , 13 3 and 13 4 supply the control data to the processor 11 under the control of a 4-bit shift register 14.
  • the shift register 14 receives a clock pulse and sequentially enables the gates 13 1 , 13 2 , 13 3 and 13 4 .
  • the duration of the clock pulse, generated by an oscillator (not shown), is 100 n sec.
  • the processor includes a 4-bit shift register 17 with the same function as the shift register 14, a 3-stage buffer register 15 with 4-bit lengths per stage, and a 4-stage ROM data register 16 with a 4-bit lengths per stage.
  • the 4-input terminals P 0 - P 3 of the processor 11 are used for receiving the control data.
  • the input terminals P 0 - P 3 are connected with the gates 13 1 , 13 2 , 13 3 and 13 4 through ROM data lines (LD).
  • ROM address information is supplied from the processor 11 to the control storage 12 through ROM address lines (LA).
  • the access time of the control storage is 50 n sec. in this embodiment.
  • the operation of the data input control system will be described hereinafter with reference to the waveforms thereof shown in FIG. 3, wherein (a) shows a clock pulse, and (b), (c), (d), and (e) show outputs of each stage of the shift registers 14 through 17, respectively.
  • the control data are read out from the control storage 12 in response to the ROM address information.
  • the 16-bit control data are divided into four groups to be supplied to gates 13 1 , 13 2 , 13 3 and 13 4 , respectively.
  • the gate 13 1 is enabled to supply the first group (bit positions 0-3) of the control data to the terminals P 0 - P 3 of the processor 11 through the ROM data line (LD).
  • the gate 13 2 passes the second group (bit positions 4-7) of the control data to the terminals P 0 - P 3 .
  • the fourth group (bit positions 12-15) of the control data is directly stored in the fourth stage of the ROM data register.
  • the contents of the buffer register 15 are respectively transferred to the corresponding stages of ROM data register 16. Therefore, the same control data as derived from the control storage 12 are stored in the ROM data register 16 in the memory cycle time of 400 n sec.
  • an auxiliary control storage may be formed in the processor in addition to the control storage 12.
  • the buffer register 15 may be removed when the ROM data register 16 stores sequentially the control data in response to outputs of the shift register 17 and the contents of the ROM data register 16 are transferred to logic circuits in the processor 11 under the control of the fourth output of this shift register 17.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Executing Machine-Instructions (AREA)
  • Bus Control (AREA)
  • Communication Control (AREA)
US05/715,141 1975-08-21 1976-08-17 Data input control system Expired - Lifetime US4087640A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP50101497A JPS5225538A (en) 1975-08-21 1975-08-21 Input control system of control use data
JA50-101497 1975-08-21

Publications (1)

Publication Number Publication Date
US4087640A true US4087640A (en) 1978-05-02

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US05/715,141 Expired - Lifetime US4087640A (en) 1975-08-21 1976-08-17 Data input control system

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US (1) US4087640A (cg-RX-API-DMAC10.html)
JP (1) JPS5225538A (cg-RX-API-DMAC10.html)
DE (1) DE2637346C2 (cg-RX-API-DMAC10.html)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4249254A (en) * 1979-02-02 1981-02-03 U.S. Philips Corporation Arrangement for restituting selection signals

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3035197A1 (de) * 1980-09-18 1982-04-29 Robert Bosch Gmbh, 7000 Stuttgart Anschlussvorrichtung einer speichereinrichtung an einen datenbus

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3821480A (en) * 1973-05-29 1974-06-28 Datatrol Inc Multiplexer system
US3821477A (en) * 1971-08-07 1974-06-28 Tokai Rika Co Ltd System for multiplex transmission of electrical signals utilizing synchronized ring counters
US3952298A (en) * 1975-04-17 1976-04-20 Spectradyne, Inc. Clock gated digital data encoding circuit

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3691538A (en) * 1971-06-01 1972-09-12 Ncr Co Serial read-out memory system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3821477A (en) * 1971-08-07 1974-06-28 Tokai Rika Co Ltd System for multiplex transmission of electrical signals utilizing synchronized ring counters
US3821480A (en) * 1973-05-29 1974-06-28 Datatrol Inc Multiplexer system
US3952298A (en) * 1975-04-17 1976-04-20 Spectradyne, Inc. Clock gated digital data encoding circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4249254A (en) * 1979-02-02 1981-02-03 U.S. Philips Corporation Arrangement for restituting selection signals

Also Published As

Publication number Publication date
DE2637346C2 (de) 1987-03-26
JPS5248448B2 (cg-RX-API-DMAC10.html) 1977-12-09
DE2637346A1 (de) 1977-03-03
JPS5225538A (en) 1977-02-25

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