JPS5248448B2 - - Google Patents
Info
- Publication number
- JPS5248448B2 JPS5248448B2 JP50101497A JP10149775A JPS5248448B2 JP S5248448 B2 JPS5248448 B2 JP S5248448B2 JP 50101497 A JP50101497 A JP 50101497A JP 10149775 A JP10149775 A JP 10149775A JP S5248448 B2 JPS5248448 B2 JP S5248448B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7828—Architectures of general purpose stored program computers comprising a single central processing unit without memory
- G06F15/7835—Architectures of general purpose stored program computers comprising a single central processing unit without memory on more than one IC chip
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microcomputers (AREA)
- Executing Machine-Instructions (AREA)
- Bus Control (AREA)
- Communication Control (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50101497A JPS5225538A (en) | 1975-08-21 | 1975-08-21 | Input control system of control use data |
| US05/715,141 US4087640A (en) | 1975-08-21 | 1976-08-17 | Data input control system |
| DE2637346A DE2637346C2 (de) | 1975-08-21 | 1976-08-19 | Steuerschaltung für Daten |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50101497A JPS5225538A (en) | 1975-08-21 | 1975-08-21 | Input control system of control use data |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5225538A JPS5225538A (en) | 1977-02-25 |
| JPS5248448B2 true JPS5248448B2 (cg-RX-API-DMAC10.html) | 1977-12-09 |
Family
ID=14302270
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50101497A Granted JPS5225538A (en) | 1975-08-21 | 1975-08-21 | Input control system of control use data |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US4087640A (cg-RX-API-DMAC10.html) |
| JP (1) | JPS5225538A (cg-RX-API-DMAC10.html) |
| DE (1) | DE2637346C2 (cg-RX-API-DMAC10.html) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4249254A (en) * | 1979-02-02 | 1981-02-03 | U.S. Philips Corporation | Arrangement for restituting selection signals |
| DE3035197A1 (de) * | 1980-09-18 | 1982-04-29 | Robert Bosch Gmbh, 7000 Stuttgart | Anschlussvorrichtung einer speichereinrichtung an einen datenbus |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3691538A (en) * | 1971-06-01 | 1972-09-12 | Ncr Co | Serial read-out memory system |
| US3821477A (en) * | 1971-08-07 | 1974-06-28 | Tokai Rika Co Ltd | System for multiplex transmission of electrical signals utilizing synchronized ring counters |
| US3821480A (en) * | 1973-05-29 | 1974-06-28 | Datatrol Inc | Multiplexer system |
| US3952298A (en) * | 1975-04-17 | 1976-04-20 | Spectradyne, Inc. | Clock gated digital data encoding circuit |
-
1975
- 1975-08-21 JP JP50101497A patent/JPS5225538A/ja active Granted
-
1976
- 1976-08-17 US US05/715,141 patent/US4087640A/en not_active Expired - Lifetime
- 1976-08-19 DE DE2637346A patent/DE2637346C2/de not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE2637346C2 (de) | 1987-03-26 |
| US4087640A (en) | 1978-05-02 |
| DE2637346A1 (de) | 1977-03-03 |
| JPS5225538A (en) | 1977-02-25 |