US3978323A - Apparatus for achieving predetermined transfer characteristics - Google Patents

Apparatus for achieving predetermined transfer characteristics Download PDF

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US3978323A
US3978323A US05/565,390 US56539075A US3978323A US 3978323 A US3978323 A US 3978323A US 56539075 A US56539075 A US 56539075A US 3978323 A US3978323 A US 3978323A
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alternator
pulse
summation
output
pulses
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Wolfgang Friedrich Georg Mecklenbrauker
Petrus Josephus van Gerwen
Wilfred Andre Maria Snijders
Theodoor Antonius Carel Maria Claasen
Hendrik Arie VAN Essen
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US Philips Corp
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US Philips Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H04L25/03114—Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals
    • H04L25/03146—Arrangements for removing intersymbol interference operating in the time domain non-adaptive, i.e. not adjustable, manually adjustable, or adjustable only during the reception of special signals with a recursive structure
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0223—Computation saving measures; Accelerating measures
    • H03H17/0233—Measures concerning the signal representation
    • H03H17/0236—Measures concerning the signal representation using codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/06—Non-recursive filters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/04—Control of transmission; Equalising
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H2218/00—Indexing scheme relating to details of digital filters
    • H03H2218/10—Multiplier and or accumulator units

Definitions

  • the invention relates to an apparatus for achieving a predetermined transfer characteristic for processing information signals.
  • the apparatus comprises a delay device and an input circuit to which information pulses derived from the information signals in accordance with a clock frequency are applied, a control generator which is connected to the delay device and which operates at a control frequency equal to an integral multiple of the clock frequency, and a digital multiplier.
  • the digital multiplier is coupled to the delay device, which at each input pulse delivers a train of pulses in time sequence.
  • the digital multiplier is also coupled to a multiplication program under the control of which the pulses of each of the pulse trains produced which are derived from the delay device are digitally multiplied sequentially in the multiplier by successive digital multiplication coefficients which represent a differential code characteristic of the transfer characteristic to be achieved.
  • the output of the digital multiplier is connected to a storage device which sums the multiplication products obtained by digital multiplication of the pulses in the pulse trains, for example for use for purposes of equalising, filtering and wideband-phase-shifting both pulse signals and
  • the particularly advantageous shape of the desired transfer characteristic with the use of the comparatively restricted number of discrete multiplication coefficient according to the exponential number series 2 m and possibly the number 0 was found to be associated with a remarkable simplification of the digital multiplier and with optimum utilisation of the available internal processing time, while also the number of possible applications was increased.
  • the object of the present invention is to provide an apparatus of the aforementioned type in which, without appreciable modification of the simple structure and while avoiding any reduction of the available internal processing time, the high quality requirements with regard to the transfer characteristic are satisfied while furthermore the possibilities of use are further extended.
  • the apparatus according to the invention is characterized in that an alternator provided with a sign reversing device and a summation device is connected in the circuit which includes the storage device, which alternator forms the sums, which alternate in sign, of the multiplication products applies via the multiplier which lie within given time periods and of the multiplication products of the multiplier applied in the preceding given time periods according to a predetermined time pattern, which sums are derived as outputs from the apparatus including the alternator.
  • the input of the sign reversing device is connected to the output of the summation device which is fed by the sign reversing device via a re-circulating line and also by multiplication products of the multiplier which lie within given time periods.
  • FIG. 1 is a schematic circuit diagram of an apparatus according to the invention designed as a band-pass filter for analog signals, FIG. 2 showing illustrative time and frequency diagrams.
  • FIGS. 3, 4, 5 and 6 show modified embodiments of the apparatus according to the invention as shown in FIG. 1, and
  • FIGS. 7, 8, 9 and 10 show further embodiments of the apparatus according to the invention.
  • FIG. 1 shows there is shown an apparatus arranged for use as a band-pass filter for analog signals which enable the filtering process to be digitally performed; the incoming analog signals are first converted to digital form.
  • the analog signals received from a line 1 are sampled in a sampling device 2 by means of sampling pulses at clock frequency and then applied to an analog-to-digital converter 3 which comprises a parallel-output pulse group encoder, the output terminals of which are designated by 4, 5, 6, . . . respectively.
  • the clock frequency F is equal to 1/T, where T is a clock period.
  • the output terminals 4, 5, 6, . . . of the pulse group encoder 3 deliver a pulse group in parallel form which is characterized by binary pulses and which in a binary number system indicates the quantised amplitude value of the sampling. More particularly the pulses at the output terminal 4 characterize the amplitude value 2 0 , those at the output terminal 5 the amplitude value 2 1 , those at the output terminal 6 the amplitude value 2 2 , and so on.
  • a pulse group U.sub. ⁇ occurs, and if binary pulses which simultaneously appear at the output terminals 4, 5, 6, . . . are denoted by u.sub. ⁇ o , u .sub. ⁇ l , . . . . u.sub. ⁇ i , . . ., u.sub. ⁇ .sub.(k-1), where k is the number of output terminals 4, 5, 6, . . . of the pulse group encoder 3, the pulse group represents the numerical value: ##EQU1##
  • the output terminals 4, 5, 6, . . . of the pulse group encoder are connected to delay devices in the form of shift registers 8, 9, . . . each of which comprises a plurality of shift register elements, an input circuit and an output circuit, which shift registers 8, 9, . . . are constructed as circulating shift registers by means of recirculating circuits 10, 11, . . . respectively each connected between an input circuit and an output circuit.
  • shift registers 8 and 9 are shown in detail, because the remaining shift registers are equal thereto.
  • the apparatus shown includes a digital multiplier 16 having a parallel input comprising k input terminals 17, 18, . . . each of which is connected to an output circuit of one of the k shift registers 8, 9, . . . and a parallel input comprising p input terminals each of which is connected to one of output terminals 19, 20, 21, 22 . . . of a parallel-output multiplication program 23.
  • the multiplication program 23 comprises a plurality of circulating shift registers 24, 25, 26 each of which comprises n shift register elements, which shift registers 24, 25, 26 are controlled, similarly to the shift registers 8, 9, via line 15 by shift frequency nF.
  • the pulses of each of the pulse trains formed, which pulses are applied via the shift registers 8, 9 to the input terminals 17, 18, are successively multiplied digitally under the control of the multiplication program 23 by digital multiplication coefficients, the resulting multiplication products being applied for further processing via output terminals 28, 29, 30, . . . of the parallel-output digital multiplier 16 to input terminals 31, 32, 33, . . . of a storage device 34, which terminals correspond to numerical values 2 0 , 2 1 , 2 2 , . . . respectively.
  • the digital multiplier 16 is of the type described extensively in copending U.S. Patent Application Serial No. 474,810.
  • the pulse switch comprises parallel-connected pulse switch channels 35, 36; 37, 38 connected between the input terminals 17, 18, . . . and the output terminals 28, 29, 30, . . . of the digital multiplier 16 which is provided with a pulse switch setting circuit which is connected to the output terminals of the pulse switch setting program 23 and comprises NOT-AND gates 39, 40 and 41, 42, respectively.
  • the pulse switch channels 35, 36, 37, 38 further include sign stages 43, 44, 45 each of which comprises two parallel-connected branches, each branch including NOT-AND gates 46, 47; 48, 49; 50, 51 which are controlled by logically inverted sign pulses from output terminals 21, 22 of the setting program 23, and NOT-AND gates 52, 53, 54 which serve as inverters and are connected in cascade with the NOT-AND gates 47, 49, 51, respectively.
  • sign pulses are applied from the output terminal 21 of the pulse switch setting program 23 via a line 55 to an input terminal 56 of the storage device 34, while furthermore providing equality of the digital circuits situated between input terminals 17, 18 and output terminals 28, 29, 30 of the pulse switch 16.
  • the sign stage 43 of the first pulse switch channel 35 includes another NOT-AND gate 57 which further has no significance, because a fixed potential corresponding to "0" pulses is applied to this NOT-AND gate 57 via a line 58.
  • the pulse switch channels 35, 36, 37, 38 are set to the desired discrete multiplication coefficients by the control of the NOT-AND gates 39, 40; 41, 42, which coefficients in the embodiment under consideration are 0, 2 0 and 2 1 . More particularly, at the appearance of the pulse group 00 of the setting code none of the pulse switch channels 35, 36, 37, 38 will be rendered operative. At the appearance of the pulse group 01 the pulse switch channels 35, 37 will be rendered operative and at the appearance of the pulse group 10 the pulse switch channels 36, 38 will be rendered operative, corresponding to multiplication coefficients 0, 2 0 and 2 1 respectively.
  • pulse groups appear which, after digital-to-analog conversion in a digital-to-analog converter 62 controlled by control pulses and in a succeeding sampling device 63 controlled by sampling pulses, via a simple low-pass filter 64 serving to suppress signals from undesirable pass ranges produce the output signal from the apparatus described at an output terminal 65.
  • control pulses for the digital-to-analog converter 62, the sampling pulses for the sampling device 63 and all the remaining control pulses for the apparatus described are derived from a central control pulse generator 67 which is connected to a pulse generator 66, in particular the sampling pulses for the sampling device 2 and the control pulses for the analog-to-digital converter 3, while this central control pulse device 67 also includes the common shift pulse generator for the shift registers 8, 9 and for the pulse switch setting program 23 and the switch pulse generator for the switches 12 and 13.
  • FIG. 2a shows in a time diagram the pulse response I(t) which in accordance with the preceding has been built up differentially in that at the end of each of the clock intervals ( ⁇ +1)T, . . ., ( ⁇ +q-1)T, . . ., ( ⁇ +n-1)T a contribution or difference is added to the value attained at the end of the respective preceding clock interval ⁇ T, . . . , ( ⁇ +q-2)T, . . ., ( ⁇ +n-2)T of the pulse response and if the pulse group U.sub. ⁇ is standardized to unity value this contribution or difference is exactly equal to the multiplication coefficient C 1 , C 2 , . .
  • the pulse response will have a value equal to the sum of all the preceding multiplication coefficients so that, for example at the end of the clock interval pT the value of the pulse response is: ##EQU4##
  • the relevant spectrum component appears in the successive output pulses at time intervals T, 2T, 3T, . . ., qT, . . ., nT shifted by an amplitude equal to the initial amplitude multiplied by the numerical values of the pulses response at the said instants, i.e. an arbitrary component Ee j .sup. ⁇ T in the frequency spectrum of the input signal will produce at the output of the apparatus an output signal: ##EQU5## so that we find for the transfer characteristic H(): ##EQU6##
  • the transfer characteristic H( ⁇ ) is nothing but the transformation of the pulse response I(t) to the frequency domain
  • the pulse response I(t) is nothing but the transformation of the transfer characteristic H( ⁇ ) to the time domain.
  • a curve A( ⁇ ) shows the amplitude-frequency characteristic associated with the pulse response I(t) of FIG. 2a in a frequency diagram
  • the curve B( ⁇ ) shows the phase-frequency characteristic which in this event is linear.
  • the pulse response I(t) can be computed therefrom by means of Fourier analysis, and from this pulse response the multiplication coefficients C q may be computed, so that the apparatus described is completely defined.
  • FIG. 2c shows the transfer characteristic of a filter having an amplitude-frequency characteristic shown by A'( ⁇ ) and a phase-frequency characteristic shown by B'( ⁇ ), which filter has a pass band of 3.1 kHz and a center frequency equal to 18.15 kHz at a clock frequency of 40 kHz.
  • FIG. 2d shows the associated pulse response characteristic I'(t), from which it will be seen that the values of the differences or contributions have greatly increased as compared with those in the pulse response I(t) of FIG. 2a and that these differences even are greater than the ensuing values of the pulse response I'(t) itself, which is the cause of the reduction in exactness of the approximation to the transfer characteristic H'( ⁇ ).
  • the clock frequency must considerably be increased, for example by a factor of 10.
  • this increase of the clock frequency results in increased complexity of the structure of the apparatus and in a corresponding reduction of the available internal processing time.
  • an alternator 68 comprising a sign reversing device 69 and a summation device 70 is connected in the circuit which includes the storage device 34, which alternator 68 according to a prescribed time pattern forms the sum of the multiplication products which are supplied by the multiplier 16 within given time periods and of the multiplication products supplied by the multiplier 16 in the preceding time periods, which sum alternates in sign and is derived as the output signal from the apparatus including the alternator 68.
  • the alternator 68 is preceded in the storage device by an accumulator 71 which digitally adds together the multiplication products of the multiplier 16 which are produced within a time period of a clock interval T, whereupon in the alternator 68 the digital sum thus formed in each clock interval and the digital sum of the preceding clock intervals are added to form a sum of alternating sign in accordance with the clock period as prescribed time pattern.
  • Both the accumulator 71 and the alternator 68 are of the parallel type and each have a parallel input and a parallel output, the parallel output of the alternator 68 being connected to the input of the digital-to-analog converter 62.
  • the accumulator 71 is provided with a plurality of parallel digital summing stages 72, 73, 74 which each have a feedback loop 75, 76, 77 respectively which comprises a bistable trigger circuit 78, 79, 80 respectively as a delay element, which loop is connected between an output circuit of the parallel output and the input of the respective digital summation stage 72, 73, 74 while an output of each digital summation stage 72, 73, 74 is connected to an input of the respective next summation stage 73, 74, . . . for the carry pulses produced in the digital summation.
  • An input terminal 56 of the first summation stage 72 is connected via the aforementioned line 55 to the sign terminal 21 of the pulse switch setting program 23.
  • the resulting digital sum is supplied to the alternator 68 via an electronic switch 81, 82, 83 respectively and also the accumulator 71 is reset to the inoperative condition by means of reset pulses applied to all the bistable trigger circuits 78, 79, 80, . . ., after which the described cycle will repeat in the next clock period.
  • the control pulses for the electronic switches 81, 82, 83 and the reset pulses for the bistable trigger circuits 78, 79, 80 are derived from lines 84 and 84' respectively which are connected to the central control pulse generator 67.
  • the alternator 68 of the parallel type comprises a summation device 70 and a sign reversal device 69, which respectively comprise summation stages 88, 89, 90 included in parallel channels 85.
  • each summation stage 88, 89, 90 being connected to an input of an inverter stage 91, 92, 93 via a bistable trigger 94, 95, 96, respectively, while an input of each summation stage 88, 89, 90 is connected via a feedback loop 97, 98, 99 respectively to the output of the relevant inverter stage and also to an output terminal of the preceding accumulator 71.
  • the summation stage 88 also has "1" pulses applied to it from a NOT-AND gate 100 connected to a fixed potential, while an input of each of the summation stages 89 and 90 is connected to an output of the preceding summation stage 88 and 89 respectively for the carry pulses produced in the digital summation operation.
  • the bistable triggers 94, 95, 96 From the outputs of the bistable triggers 94, 95, 96 the output signal of the storage device 34 including the alternator 68 is derived and for this purpose the bistable triggers 94, 95, 96 are connected through lines having output terminals 59, 60, 61 to the digital-to-analog converter 62 for further processing.
  • the multiplication products of the digital multiplier 16 which are situated in each clock period T are first digitally added together in the accumulator 71 and then summed in the alternator 68 with alternating sign in accordance with the clock period.
  • the digital output signal of the summation device 70 is delayed in the bistable trigger circuit 94, 95, 96 by a clock period and has its sign reversed in the sign reversal device 69 and then is fed back via feedback loops 97, 98, 99 respectively to the summation device 70 for summation with the digital sum of multiplication products formed in the next clock period and supplied by the accumulator 71, whereupon the resulting output signal of the summation device 70 is again delayed by one clock period and again has its sign reversed and is again fed back via the feedback loops 97, 98, 99 to the input of the summation device 70.
  • the cycle described repeats each time and thus in the alternator 68 the sum of alternating sign is formed of the output signals of the accumulator which occur in accordance with the clock period, which sum of alternating sign is derived from the output terminals 59, 60, 61 and is applied to the digital-to-analog converter 62 for digital-to-analog conversion.
  • the sampling device 63 and the lowpass filter 64 the output signal of the apparatus is taken from the output terminal 65, and according to the foregoing this signal forms the input signal filtered according to the transfer function H'( ⁇ ) of FIG. 2c when the successive multiplication coefficients are suitably set in the digital multiplier 16.
  • the concept of the apparatus according to the invention is completely different from that of the known apparatus of the aforementioned type, for while in the known apparatus a desired transfer characteristic is obtained by starting directly from the pulse response the apparatus according to the invention starts from the pulse response P(t) of the corresponding low-pass filter which can be regarded as the envelope of the pulse response.
  • the transfer characteristic H'( ⁇ ) of FIG. 2c having the amplitude-frequency characteristic A'( ⁇ ) and the phase-frequency characteristic B'( ⁇ ) is not obtained by starting from the pulse response I'(t) of FIG. 2d but by starting from the envelope of the pulse response which is indicated in FIG.
  • the envelope P(t) of FIG. 2e is converted into the pulse response I'(t) of FIG. 2d, and in particular in the alternator the pulse response I'(t) is obtained by alternating summation of the standardized multiplication products and the standardized multiplication products of the preceding clock period, which standardized multiplication products, as has been set out hereinbefore, are exactly equal in magnitude to the multiplication coefficients C q .
  • the alternating sums of the preceding standardized multiplication products are produced at the output terminals 59, 60, 61 of the alternator 68 as the instantaneous values of the pulse response I'(t).
  • the pulse response is given by the formula: ##EQU7## or, expressed in the envelope P(t):
  • the apparatus according to the invention while having a particularly simple structure ensures a transfer characteristic H( ⁇ ) of high quality at a minimum clock frequency and hence with maximum available internal processing time, so that its field of use is considerably extended, permitting for example a considerable increase of the set of transfer characteristics which are obtainable in practice, especially towards higher frequency ranges, such as for band-pass filters, high-pass filters, phase shifters and the like.
  • the apparatus according to the invention is distinguished by its flexibility in that 23 different transfer characteristics are obtained by merely exchanging the multiplication program and also in the complete freedom with regard to the type of analog-to-digital converter used, enabling for example the pulse group encoder shown in FIG. 1 to be replaced by a delta modulator.
  • FIG. 3 shows a modified embodiment of the apparatus of FIG. 1, elements corresponding to those of FIG. 1 being designated by like reference numerals.
  • the storage device is of the parallel type comprising parallel channels 101, 102, 103, . . ., however, in this embodiment the storage device 34 comprises the combination of an integrator and an alternator, the storage device 34 being connected in each clock period as an integrator and as an alternator by means of electronic switches 104, 105, 106 which each have two change-over contacts 107, 108; 109, 110; 111, 112 respectively; if the switches 104, 105, 106 are connected to the change-over contacts 107, 109, 111 respectively, in the parallel channels 101, 102, 103 respectively summation stages 72, 73, 74, bistable trigger circuits 78, 79, 80, change-over contacts 107, 109, 111 and feedback loops 113, 114, 115 to the inputs of the summation stages 72, 73, 74 respectively together constitute the integrator.
  • switches 104, 105, 106 are connected to the change-over contacts 108, 110, 112 respectively, in the parallel channels 101, 102, 103 respectively summation stages 72, 73, 74 bistable trigger circuits 78, 79, 80, inverters 94, 95, 96 in the form of NOT-AND gates, summation stages 116, 117, 118 change-over contacts 108, 110, 112 and switches 104, 105, 106 fed back to an input of the summation stages 72, 73, 74 via feedback loops 113, 114, 115 respectively together constitute the alternator, in which case to an input terminal of the summation stage 116 connected to the inverter stage 94 in the first channel 101 there are also applied "1" pulses from a NOT-AND gate 119 connected to a suitable potential so as to provide digital sign reversal in a binary number system.
  • the sign reversing device comprises the NOT-AND gates 119, 94, 95, 96 and the summation stages 116, 117, 118 which each have an input connected to an output of the preceding summation stage 116, 117, . . . for the carry pulses produced in the digital summation.
  • the electronic switches 104, 105, 106 are controlled by control pulses from a line 120 connected to the central control pulse generator 67, and under the control of the electronic switches 104, 105, 106 by the integrating operation during the time in which the switches 104, 105, 106 are connected to the change-over contacts 107, 109, 111 respectively, similarly to the apparatus according to FIG. 1, the digital sum of the multiplication products is supplied as the output signal of the storage device 34, whereupon the alternating summation with the digital sums of the multiplication products produced in the preceding clock periods is effected by changing over the electronic switches 104, 105, 106 to the positions in which they are connected to the change-over contacts 108, 110, 112 respectively.
  • FIG. 4 shows another modified embodiment of the apparatus of FIG. 1, in which again elements corresponding to FIG. 1 are designated by the same reference numerals.
  • This is simply effected by including a second bistable trigger circuit 121, 122, 123 as a delay element in each of the parallel-connected alternator channels 85, 86, 87 respectively of FIG. 1, so that the overall delay in each of the alternator channels is equal to 2 clock periods, providing the apparatus shown in FIG. 4.
  • This step can be used to particular advantage to implement filters in which the center frequency of the pass band lies at about one quarter of the clock frequency, as is illustrated in a transfer characteristic H"( ⁇ ) which is shown in FIG. 2g and is associated with the aforementioned pulse response characteristic.
  • H"( ⁇ ) transfer characteristic which is shown in FIG. 2g and is associated with the aforementioned pulse response characteristic.
  • the amplitude-frequency characteristic and the phase-frequency characteristic of the filter are shown which now are designated by A"( ⁇ ) and B"( ⁇ ) respectively.
  • the pulse response I"(t) is built up from the envelope which, however, here is composed of two components, i.e. the pulse response component at each even-numbered clock instant and the component at each odd-numbered clock instant, which are illustrated in FIG. 2h by curves P" 1 (t) and P" 2 (t) respectively.
  • the envelope P(t) of FIG. 2e the two components P" 1 (t) and P" 2 (t) owing to their shapes are paricularly suitable to be differentially reproduced at a minimum clock frequency, which yields the important advantages mentioned with reference to FIG. 1 hereinbefore.
  • time patterns may also be used for the alternating summation in the alternator, for example in accordance with 3 times the clock period by including a third bistable trigger circuit as a delay element in the alternator 68, which is of advantage to obtain filter characteristics having a center frequency of about one sixth the clock frequency, and so on.
  • FIG. 5 shows an apparatus of the type shown in FIG. 4 in which the additional step shown in the Figure can be used to advantage as and if required.
  • the step consists of including an additional feedback loop 214, 215, 216, which is connected to a point of the delay circuit constituted by the bistable trigger circuit 94, 121; 95, 122; 96, 123 in the parallel connected alternator channels 85, 86, 87 respectively, and the output signal from this additional feedback loop 214, 215, 216 is added to the alternating sum produced in the alternator 68 by means of summation stages 217, 218, 219 which in the embodiment shown are connected to the output of the summation stages 88, 89, 90 respectively, or the carry pulses of these summation stages 217, 218, 219 an output of each stage is connected to an input of a summation stage 218, 219, ... respectively in a succeeding alternator channel 86, 87,... .
  • this additional feedback loop 214, 215, 216 included in the parallel-connected alternator channel 85, 86, 87 respectively is connected either directly or via a sign reversing stage 220, 221, 222 shown by broken lines, to an input of the summation stage 217, 218, 219 respectively, and in particular it was found that undesirable pass ranges are avoided by this step.
  • FIG. 6 also shows a modified embodiment of the apparatus of FIG. 1 in which, however, summation alternating in sign is performed in the storage device 34 including the alternator, without using an accumulator or integrator, in the period of the multiplication products formed in the digital multiplier 16 as the prescribed time pattern, i.e. in accordance with the pereiod of the control generator in the form of the shift-pulse generator of duration T/n.
  • the apparatus shown provides a considerable simplification. because a separate accumulator or integrator is dispensed with.
  • the storage device 34 including an alternator corresponds to the alternator which in FIG. 3 is formed when the electronic switches 104, 105, 106 are set to the positions in which they are connected to the change-over contacts 108, 110, 112 respectively.
  • the storage device 34 of the parallel type constituted by the alternator comprises a plurality of parallel-connected channels 124, 125, 126, while summation stages 72, 73, 74, bistable trigger circuits 78, 79, 80, inverters 94, 95, 96 in the form of NOT-AND gates, summation stages 116, 117, 118 fed back to inputs of the summation stages 72, 73, 74 via feedback loops 113, 114, 115 respectively together constitute the alternator and, similarly to the apparatus shown in FIG.
  • the storage device 34 which acts exclusively as an alternator is connected for digital-to-analog conversion to the digital-to-analog converter 62 which, similarly to what is the case in the above-described apparatus, is rendered operative in accordance with the clock period T by pulses from the control pulse generator 67.
  • alternating summation in accordance with the period of the control generator having a duration T/n is effected in the device 34. More particularly, in the alternator 34 the digital output signal from the summation device comprising the summation stages 72, 73, 74, after being delayed in the delay device comprising the bistable trigger circuits 78, 79, 80 and after being reversed in sign in the sign reversing device comprising the NOT-AND gates 119, 94, 95, 96 and summation stages 116, 117, 118 respectively, is fed back via feedback loops 113, 114, 115 to the summation device 72, 73, 74 for addition to the next subsequent multiplication product of the digital multiplier 16, whereupon the resulting output signal from the summation device 72, 73, 74 after being delayed again by T/n and after having its sign reversed again, is fed back to the input of the summation device 72, 73, 74 via feedback loops 113, 114, 115 to be added
  • the pulse response characteristic I'(t) of FIG. 2d is obtained to achieve the transfer characteristic H'( ⁇ ) of FIG. 2d.
  • the number of multiplication coefficients per clock period may be made odd, which may be performed in a particularly simple manner in that one multiplication coefficient of value zero, or in general an odd number of such multiplication coefficients, is added to the beginning or to the end of the series of multiplication coefficients.
  • the same results may be attained in another manner in that a sign reversing device is included after the circulating shift registers and another sign reversing device is included after the storage device 34 constituted by the alternator, which sign reversing devices effect sign reversal under control of an electronic switch in accordance with twice the clock period.
  • the binary pulse signals for example synchronous telegraphy signals, delta modulation signals and the like, are taken from a pulse source 124 which through a line 125 is controlled by clock pulses from the central control pulse generator 67.
  • a pulse source 124 which through a line 125 is controlled by clock pulses from the central control pulse generator 67.
  • clock pulses from the central control pulse generator 67.
  • the pulse signals from the pulse source 24 are applied in a manner similar to that described with reference to FIG. 1 to a shift register 126 which comprises shift register elements 127, 128, 129, 130 the contents of which are shifted via the line 15 in accordance with the clock frequency or a multiple thereof, while furthermore similarly to the apparatus shown in FIG. 1 care is taken to ensure that for digital multiplication each input pulse to the shift register 126 delivers a train of output pulses in time sequence.
  • an electronic switch 131 is used which within each shift period of the shift register 126 scans the terminals on the shift register elements 127 to 130 under the control of switch pulses supplied via a line 132 by the central control pulse generator 67, which switch pulses also form the control pulses of the multiplication program 23.
  • the digital multiplier 16 is in the form of a pulse switch having a plurality of pulse switch channels for digital multiplication of the pulses from the switch 31 by the multiplication coefficients 2 2 , 2 1 , 2 0 , 0, setting to the desired multiplication coefficient being effected by pulse code groups which appear at output terminals 133, 134, 135 of the multiplication program 23 in the form of a pulse switch setting program, while the setting of the sign is effected by sign pulses which appear at an output terminal 136, the digital sign reversal in a binary number system being performed in the digital multiplier 16 constituted by the pulse switch.
  • the pulse switch 16 comprises parallel NOT-AND gates 137, 138, 139, 140, 141 connected to the electronic switch 131, output terminals 133, 134, 135 of the multiplication program 23 being connected to the NOT-AND gates 140, 138 and 137, 139 respectively, and the sign terminal 136 being connected to the NOT-AND gates 139, 141, while further NOT-AND gates 146-149 are provided which are connected to output terminals 142-145 respectively and the inputs of which are connected to the NOT-AND gate 137, the NOT-AND gates 138, 139, the NOT-AND gates 140, 141 the NOT-AND gate 149, ..., respectively.
  • the alternator 34 is connected to a digital-to-analog converter 62 in the form of a pulse group decoder to the output of which is connected a sampling device 63, the output signal of the apparatus, which is the input signal filtered according to the desired transfer function, being produced via a low-pass filter 64 at the output terminal 65.
  • the complete freedom in the choice of the type of analog-to-digital conversion to be used provides the important advantage that the type of the analog-to-digital converter can be adapted to the nature of the input signal, for example according to whether speech signals, music signals or television signals are to be processed, while digital signals such, for example, as synchronous telegraphy signals can directly be used without analog-to-digital conversion. It is not absolutely necessary to convert the pulse groups at the output of the alternator into an analog signal in a digital-to-analog converter 62, but these pulse groups may be used for further processing, for example for digital modulation.
  • shift registers or random access memories may be used, which for the purpose of obtaining a series of successive output pulses from a single inpput pulse may have different forms, for example may be circulating shift registers, shift registers using electronic switches and the like, as was described hereinbefore with reference to the preceding Figures.
  • FIG. 8 shows another embodiment of the apparatus according to the invention which differs from the aforedescribed embodiment in that the digital multiplier 16 need not be in the form of a pulse switch but may be of a more usual type.
  • the multiplication program 23 takes the form of a coefficient program the pulse groups derived from its output terminals 151, 152, 153, 154, and 155 defining the multiplication coefficient with regard to sign and magnitude, and similarly to the preceding embodiments the multiplication coefficients characterize, in a differential code, the transfer characteristic to be obtained.
  • circulating shift registers 8, 9 are used and the multiplication products produced in a binary number system by digital multiplication of the pulse groups from the circulating shift registers 8, 9 according to sign and magnitude by the coefficients of the coefficient program 23 appear at the output terminals 28, 29, 30 to be applied to the storage device 34 in the form of an alternator which forms the alternating sum of the applied multiplication products and the preceding multiplication products.
  • the digital-to-analog converter 62 the output circuit of which includes the sampling device 63 and the succeeding low-pass filter 64, the output signal of the device appears at the output terminal 65, which signal just like in the preceding apparatus forms the input signal filtered in accordance with the desired transfer function.
  • the alternator 34 used is equal to the devices described hereinbefore and it similarly comprises a summation device 70 made up of summation stages 88, 89, 90 and a sign reversing device 69 made up of sign reversing stages provided with inverter stages 91 92, 93 in the form of NOT-AND gates for logical inversion of the applied pulse groups and summation stages 116, 117, 118, the summation stages 88, 89, 90 included in the alternator channels 124, 125, 126 being connected through bistable trigger circuits 78, 79, 80 to the inputs of the sign reversing stages 91-93; 116-118, while the outputs of the sign reversing stages are connected through feedback loops 113, 114, 115 to inputs of the summation stages 88, 89, 90 respectively.
  • the input terminals 31, 32, 33 of the summation stages 88, 89, 90 are connected to the output terminals 28, 29, 30 respectively of the digital multiplier, while an inpput terminal of each of the summation stages 89, 90 is connected to an output terminal of the preceding summation stage 88 and 89 and an input terminal of each of the summation stages 117, 118 of the sign reversing stages is connected to an output of the preceding stages 116, 117, rspectively for the carry pulses which are produced in the digital summation.
  • the digital sign reversing device 69 in the alternator 34 of this embodiment differs from that of the embodiments shown in the preceding Figures in that in the latter digital sign reversal is effected by the addition, after logical inversion, of a pulse group having the value +1, whereas in the apparatus shown in FIG. 8 digital sign reversal is effected in that prior to logical inversion a pulse group having the value -1 is added which in a binary number system is represented by a pulse group 111 ... .
  • the digital multiplier may take different forms, for example that of a pulse switch or a more usual design, and the same applies to the form of the multiplication program, which may be a pulse switch setting program or a coefficient program and may be differently implemented, for example as shift registers, read only memories composed of magnetic cores, transistor arrays and the like.
  • the multiplication coefficients used for digital multiplication in the digital multiplier must always characterize the desired transfer characteristic in a differential code.
  • FIG. 9 shows a modified embodiment of the apparatus shown in FIG. 6 which similarly to that shown in FIG. 6 effects summation of alternating sign in the period of the multiplication products formed in the digital multiplier 16.
  • the use of a storage network arranged to change over in each clock period provides the pulse response characteristic I"(t) as illustrated in FIG. 2f and obtained by means of the apparatus of FIG. 4, which characteristic corresponds to a center frequency of the transfer characteristic H"( ⁇ ) at one quarter of the clock frequency or thereabout.
  • the storage device 34 designed as an alternator comprises parallel-connected channels 124, 125, 126 provided with a summation device having summation stages 72, 73, 74 and with a sign reversing device comprising inverters 94, 95, 96 connected to summation stages 116, 117, 118 and a NOT-AND gate 119 which is connected to the summation stage 116 and continuously produces "1" pulses, outputs of the summation stages 116, 117, 118 in the sign reversing stages being connected through feedback loops 113, 114, 115 to the summation stages 72, 73, 74 respectively.
  • a storage network which is capable of being changed over in each clock period and comprises single-pole electronic switches 195, 196, 197 and double-pole electronic switches 198, 199, 200 respectively, which in each clock period are simultaneously changed over via a line 201, and parallel delay elements which are included between the switches and take the form of bistable triggers 202, 203; 204, 205; 206, 207, respectively.
  • Each of the parallel-connected channels 124, 125, 126 includes one of the bistable triggers 202, 203; 204, 205; 206, 207 respectively between the relevant summation stage and sign reversing stage in the same manner as in FIG. 6, while the other bistable trigger is connected as a circulating store by means of a recirculating circuit 208, 209; 210, 211; 212, 213 respectively.
  • the alternating summation of the multiplication products is effected via the bistable triggers 203, 205, 207, and at the end of the clock period the switches 195-197, 198-200 are switched to their other positions by means of a switch pulse on the line 201.
  • the digital sum produces is stored, at the end of the clock period, in the bistable triggers 203, 205, 207 which then are connected as circulating stores, while the alternating summation takes place via the bistable triggers 202, 204, 206, the first value being the digital sum stored in these triggers at the end of the preceding clock period.
  • the cycle described repeats in each clock period in that the switches 195-197, 198-200 are switched by means of a switching pulse on the line 201.
  • the location of the pass band of the filter relative to the clock frequency is adjustable, and if, for example, a passband is desired at one sixth of the clock frequency the switches 198-200 take the form of three-pole switches and the single-pole switch has three change-over contacts to each of which a bistable trigger is connected, the summation stage in the relavent alternator channel being connected to the associated sign reversing stage via one of the triggers while the remaining bistable triggers are switched as circulating stores.
  • FIG. 10 shows an apparatus in which an alternator 34 of the series type is used.
  • analog signals coming in via a line 1 are applied to a sampling device 2 controlled by sampling pulses at clock frequency, the samples being applied to an analog-to-digital converter 159 which is in the form of a pulse group encoder having a series output.
  • pulse groups are obtained which are constituted by constituent pulses which succeed one another in time, corresponding constituent pulses of successive pulse groups occurring in accordance with the block frequency, while the constituent pulses which succeed one another in time in a pulse group characterize successive numbers in a binary number system, and in this embodiment the first constituent pulse corresponds to the number 2 0 , the second to the number 2 1 , and so on.
  • the time interval between two successive pulse groups is equal to 4 times the interval ⁇ between two successive pulses in a group.
  • the pulse groups generated in the pulse group encoder 159 are applied to a circulating shift register 8 provided with a recirculating circuit 10 and an electronic switch 12 for generating a series of successive pulse groups as a result of each pulse group applied to the input circuit of the shift register 8, which successive pulse groups are applied to a digital multiplier in the form of a pulse switch 16 which comprises a plurality of parallel-connected pulse switch channels 160, 161, 162, 163, 164 and a pulse switch setting circuit 23 which includes a switch 165 which is controlled by a setting code of the pulse switch setting program and has change-over contacts 166-170 provided on the pulse switch channels 160-164 respectively.
  • the pulse switch channel 160 is at a fixed potential which corresponds to "0" pulses, corresponding to a multiplication coefficient 0, the remaining pulse switch channels 161-164 being connected to the output of the circulating shift register 8, the channel 161 directly and the other channels via delay elements 171, 172, 173 respectively in the form of shift registers having delay times equal to once, twice and four times the space ⁇ of two successive constituent pulses in a pulse group, corresponding to multiplication coefficients 2 0 , 2 1 , 2 2 and 2 4 respectively, because a time delay of m ⁇ effects digital multiplication by a multiplication coefficient 2 m .
  • the electronic switch 165 is connected to a sign stage 174 comprising two parallel branches one of which includes a NOT-AND gate 175 acting as an inverter, and a sign setting circuit comprising an electronic switch 176 which is controlled by sign pulses from the pulse switch setting program 23 and has change-over terminals 178 and 179 each connected to one of the parallel branches.
  • a pulse corresponding to the value 2 0 is added to obtain a pulse group of opposite sign in a binary number system, which pulse similarly to FIG. 1 is in the form of a sign pulse derived via the line 55 from the pulse switch setting program 23.
  • the pulse groups from the circulating shift register 8 are digitally multiplied by the multiplication coefficients in differential code which appertain to the positions of the two electronic switches 165 and 176 and the multiplication products which as a result are produced at the output terminal of the digital multiplier 16 are applied for further processing to the alternator in the storage device 34, which alternator will be described hereinafter.
  • the alternator 34 used is of the series type.
  • the alternator 34 comprises a summation device 181 and a sign reversing device 182, which latter device is constituted by a NOT-AND gate 183 which serves as an inverter and by a summation device 184, an output of the sign reversing device 182 being connected via a feedback loop 215 to an input of the summation device 181 while an output of this summation device 181 is connected, via a delay element 185 in the form of a shift register, to an output of the sign reversing device 182, the output signal of the alternator 34 being derived from the output of the shift register 185.
  • Outputs of the summation devices 181, 184 are connected by carry lines for carry pulses via delay elements in the form of shift registers 186, 187 and electronic switches 188, 189 having change-over terminals 191, 192; 193, 194 respectively to inputs of the relevant summation devices 181, 184 respectively.
  • the delay time of the shift register 185 is made equal to the time period of two successive pulse groups which in the embodiment shown is equal to the clock period T, while the delay time of the shift registers 186, 187 is made equal to the time spacing ⁇ of two successive constituent pulses in a pulse group.
  • the electronic switches 188, 189 are switched to the change-over terminals 192, 194 respectively and the carry pulses formed in the summation devices 181, 184 are applied via the carry lines to the inputs of the summation devices 181, 184 respectively, so that by means of the digital summation device 181 and the digital sign reversing device 182 in the alternator the alternating sum is formed which is derived from an output terminal 217 for further processing.
  • the alternator may be of various types, for example of series and parallel types, which moreover each may be differently designed, however, there are further possibilities, for example constructing the alternator according to analog techniques, inter alia for use in a sequence exchange of storage device and digital-to-analog converter, at least partial combination of elements of the summation device and the sign reversing stage or possibly the digital multiplier, and the like.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Control Of Eletrric Generators (AREA)
  • Filters And Equalizers (AREA)
  • Networks Using Active Elements (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Manipulation Of Pulses (AREA)
  • Analogue/Digital Conversion (AREA)
US05/565,390 1974-04-18 1975-04-07 Apparatus for achieving predetermined transfer characteristics Expired - Lifetime US3978323A (en)

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NLAANVRAGE7405238,A NL179619C (nl) 1974-04-18 1974-04-18 Digitale signaalverwerkingsinrichting voor het realiseren van een vooraf bepaalde overdrachtskarakteristiek.
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JP (1) JPS5831770B2 (ja)
BE (1) BE828057A (ja)
CA (1) CA1025126A (ja)
DE (1) DE2514875C3 (ja)
FR (1) FR2268412B1 (ja)
GB (1) GB1509795A (ja)
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4773034A (en) * 1985-05-09 1988-09-20 American Telephone And Telegraph Company Adaptive equalizer utilizing a plurality of multiplier-accumulator devices
US20050132164A1 (en) * 2003-10-01 2005-06-16 Moore George S. Pipelined accumulators
US20220294468A1 (en) * 2019-11-21 2022-09-15 Huawei Technologies Co., Ltd. Multiplier and operator circuit

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL178469C (nl) * 1976-07-06 1986-03-17 Philips Nv Niet-recursief discreet filter.
JPH0233220A (ja) * 1988-07-23 1990-02-02 Ryoichi Mori スプライン関数発生回路

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3624562A (en) * 1969-03-26 1971-11-30 Fujitsu Ltd Automatic equalizer for random input signals
US3703632A (en) * 1966-06-10 1972-11-21 Amoco Prod Co Recursion filter
US3706076A (en) * 1970-12-21 1972-12-12 Bell Telephone Labor Inc Programmable digital filter apparatus
US3736414A (en) * 1971-06-30 1973-05-29 Ibm Transversal filter equalizer for partial response channels

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3703632A (en) * 1966-06-10 1972-11-21 Amoco Prod Co Recursion filter
US3624562A (en) * 1969-03-26 1971-11-30 Fujitsu Ltd Automatic equalizer for random input signals
US3706076A (en) * 1970-12-21 1972-12-12 Bell Telephone Labor Inc Programmable digital filter apparatus
US3736414A (en) * 1971-06-30 1973-05-29 Ibm Transversal filter equalizer for partial response channels

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4773034A (en) * 1985-05-09 1988-09-20 American Telephone And Telegraph Company Adaptive equalizer utilizing a plurality of multiplier-accumulator devices
US20050132164A1 (en) * 2003-10-01 2005-06-16 Moore George S. Pipelined accumulators
US7424503B2 (en) * 2003-10-01 2008-09-09 Agilent Technologies, Inc. Pipelined accumulators
US20220294468A1 (en) * 2019-11-21 2022-09-15 Huawei Technologies Co., Ltd. Multiplier and operator circuit
US11855661B2 (en) * 2019-11-21 2023-12-26 Huawei Technologies Co., Ltd. Multiplier and operator circuit

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JPS50140031A (ja) 1975-11-10
NL179619B (nl) 1986-05-01
JPS5831770B2 (ja) 1983-07-08
SE7504284L (sv) 1975-10-20
GB1509795A (en) 1978-05-04
NL179619C (nl) 1987-05-18
DE2514875A1 (de) 1975-10-30
AU8026475A (en) 1976-10-21
BE828057A (fr) 1975-10-17
CA1025126A (en) 1978-01-24
SE399346B (sv) 1978-02-06
FR2268412A1 (ja) 1975-11-14
FR2268412B1 (ja) 1978-07-13
DE2514875B2 (de) 1979-06-07
DE2514875C3 (de) 1980-02-07
NL7405238A (nl) 1975-10-21

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