US3878474A - Phase locked loop - Google Patents

Phase locked loop Download PDF

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Publication number
US3878474A
US3878474A US479604A US47960474A US3878474A US 3878474 A US3878474 A US 3878474A US 479604 A US479604 A US 479604A US 47960474 A US47960474 A US 47960474A US 3878474 A US3878474 A US 3878474A
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United States
Prior art keywords
phase
locked loop
phase locked
signal
oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US479604A
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English (en)
Inventor
Peter Klaus Runge
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AT&T Corp
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Bell Telephone Laboratories Inc
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Filing date
Publication date
Priority to US479604A priority Critical patent/US3878474A/en
Application filed by Bell Telephone Laboratories Inc filed Critical Bell Telephone Laboratories Inc
Priority to CA218,926A priority patent/CA1021411A/en
Publication of US3878474A publication Critical patent/US3878474A/en
Application granted granted Critical
Priority to SE7506561A priority patent/SE7506561L/xx
Priority to GB24990/75A priority patent/GB1507734A/en
Priority to BE157262A priority patent/BE830155A/xx
Priority to NL7507013A priority patent/NL7507013A/xx
Priority to DE19752526513 priority patent/DE2526513A1/de
Priority to IT24357/75A priority patent/IT1038921B/it
Priority to FR7518804A priority patent/FR2275062A1/fr
Priority to JP50072808A priority patent/JPS584850B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/24—Automatic control of frequency or phase; Synchronisation using a reference signal directly applied to the generator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/083—Details of the phase-locked loop the reference signal being additionally directly applied to the generator

Definitions

  • This invention relates to phase locked loops.
  • Phase controlled oscillators also known as phase locked oscillators or phase locked loops (PLL) are commonly used to recover timing information in pulsecode-modulated (PC M communication systems.
  • a phase locked loop includes a phase detector for measuring small differences in phase between an incoming signal and a voltage controlled local oscillator (VCO). Any difference thus detected generates an error signal which is then applied to the local oscillator and serves to tune the latter so as to minimize the measured phase difference.
  • VCO voltage controlled local oscillator
  • phase locked loop When used in a PCM system to recover timing information.
  • one of the more important operating characteristics of a phase locked loop is the ability of the local oscillator to track accurately the phase of the incoming signal in the presence of noise. To the extent that it does not. an uncertainty or time jitter is produced which. ultimately. imposes a limit upon the physical length of the communication system. If extended beyond this limit. the error rate tends to increase to an unacceptable level.
  • phase locked loops are so-called "second order loops. While the jitter performance can be improved by going to third order loops. the latter are not unconditionally stable and. hence. are not preferred.
  • the present invention utilizes phase locked loops with signal injection directly into the voltage controlled oscillator (PLLI).
  • the amplitude and phase of the input signal coupled to the VCO are specifically selected to minimize the jitter bandwidth.
  • the optimum phase angle lies within the range between and The amplitude of the injected signal is. in turn. a function of the phase angle.
  • the resulting jitter bandwidth is reduced by as much as 75 percent.
  • FIG. 1 shows. in block diagram. a phase locked loop in accordance with the present invention
  • FIG. 2 shows the transfer function of a second orderloop as a function of frequency for different damping factors
  • FIG. 3 shows the time jitter as a function of the damping factor of a phase locked loop when adjusted in accordance with the prior art and when adjusted in accordance with the present invention
  • FIG. 4 shows the spectral density distribution at the output of a second order loop when adjusted in accordance with the prior art for three different damping factors. and when adjusted in accordance with the present invention
  • FIGS. 5 and 6 show a circuit diagram of a phase locked loop in accordance with the present invention.
  • FIG. 7 is a key figure showing the relationship between FIGS. 5 and 6.
  • FIG. 1 shows in block diagram a phase locked loop 10 with input signal injection to the voltage controlled oscillator (VCO) in accordance with the present invention.
  • a phase locked loop comprises a phase detector 11; a filter I2: and a voltage controlled oscillator 13.
  • phase detector 11 measures the phase difference between the input signal e and the VCO signal E. and generates an error signal V which is a function thereof.
  • the error signal is fed back to the VCO by means of filter 12 in a manner so as to minimize the measured phase difference and. thereby. reduce the magnitude of the error signal.
  • a component of input signal is coupled to the VCO so as to increase the pull-in range of the phase locked loop as taught in US. Pat. No. 3.189.825.
  • signal injection to the VCO is made through a phase shifter 14 which serves to control the phase of the injected signal. and an attenuator 15 which controls the amplitude of the injected signal.
  • A is a proportionality constant
  • K is the loop gain
  • a is the filter constant.
  • Equation l is illustrated graphically in FIG. 2 which shows the variation of the transfer function H(s). expressed in dB. as a function of frequency. normalized with respect to the natural frequency of the loop w,,,,.
  • the transfer function tends to be flat at the lower frequencies. However, it has an undesirable sharp peak at the higher frequencies. as shown by curve 20.
  • This characteristic peak of a second order loop can be suppressed by increasing the damping factor However. as can be seen by curves 2] and 22, as the damping factor is increased the loop noise bandwidth is also increased.
  • This involves the addition of a second integrator to the loop filter. in which case the filter transfer function is given by F(s) l+a/s+b/s 3 and the closed loop transfer function is given by H(S) (AKsaAKs bAK/s AKA tL-IKS bAK 13) While the added degree of freedom available in a third order loop permits one to eliminate the transfer function peak without incurring any bandwidth penalty.
  • a third order loop lacks the unconditional stability of a second order loop and. hence. is not preferred.
  • the preferred characteristics of both the second and third order phase locked loops are realized by controlling the amplitude of the component of input signal injected into the VCO. and its phase relative to the phase of the oscillator signal at the point of injection.
  • the improvement in performance can be readily observed by first adjusting the phase locked loop in accordance with the prior art wherein the angle 6 of the injection signal to the VCO is zero. When this is done. and the noise power at the output due to time jitter is measured as a function of signal injection. one obtains a curve 30 of the type shown in FIG. 3.
  • the time jitter variance is a minimum for 0 when the damping factor. is equal to 0.5. where is proportional to the amplitude of the injected signal.
  • the amplitude of the injected signal is increased until a second. deeper minimum is obtained.
  • the phase angle can then be reset and a second adjustment made of the injected signal amplitude.
  • further optimizing i.e.. minimizing) the time jitter.
  • Curves 40, 41 and 42 show the spectral density distribution at the output of a second order loop with signal injection when adjusted in accordance with the prior art for three different damping factors. while curve 43 shows the spectral density for the same phase locked loop when adjusted in accordance with the present invention. It will be noted. as indicated hereinabove. that as the damping is increased in accordance with the prior art. the bandwidth tends to increase as the peaks are suppressed. By contrast. in a phase locked loop in accordance with the present invention. the peaks are eliminated with no increase in bandwidth.
  • S is the cross spectral density
  • equation (5) can be rewritten in terms of 6 as follows:
  • FIGS. 5 and 6 included for purposes of illustration. show the circuit diagram of a phase locked loop constructed by applicant and used to obtain the abovede scribed data. Using the same identification numerals as were used in FIG. 1 to identify corresponding components.
  • the circuit diagram of FIGS. 5 and 6 includes a phase detector 11, a loop filter 12. and a VCO 13. Because phase detector ll is a Hewlett-Packard (HP5082-2997) balanced diode quad. the input signal. which is an unbalanced binary signal. is first converted to a balanced signal by means of a splitter-inverter 51. and then amplified by means of an amplifier 52, before being applied to detector 11. Similarly. the unbalanced signal derived from VCO 13 is converted to a balanced signal by means of a second splitter-inverter before being applied to detector 11.
  • phase detector ll is a Hewlett-Packard (HP5082-2997) balanced diode quad.
  • the input signal. which is an unbalanced binary signal.
  • phase shifter 14A and 14B are used in this embodiment. With phase shifter 14A adjusted for zero phase shift. phase shifter 14B is adjusted for Zero injection angle (0 0). Phase shifter 14A is used thereafter as a means of adjusting the injection angle. Attenuator 15 is used. as explained hereinabove. to adjust the amplitude of the injection signal.
  • a phase locked loop including:
  • phase detector for generating an error signal
  • phase angle. 0. of the component of input signal injected into said oscillator. relative to the phase of the oscillator signal at the point of injection. is substantially different than zero in order to significantly reduce the jitter bandwidth of the said phase locked loop.
  • phase locked loop according to claim 1 where signal injected into said oscillator is related to said said phase angle lies within the range between -l5 phase angle 6 by and l,- M/ V1 N Sin 0.

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
US479604A 1974-06-17 1974-06-17 Phase locked loop Expired - Lifetime US3878474A (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
US479604A US3878474A (en) 1974-06-17 1974-06-17 Phase locked loop
CA218,926A CA1021411A (en) 1974-06-17 1975-01-29 Phase locked loop
SE7506561A SE7506561L (sv) 1974-06-17 1975-06-09 Faslast slinga.
GB24990/75A GB1507734A (en) 1974-06-17 1975-06-11 Phase locked loop circuits
BE157262A BE830155A (fr) 1974-06-17 1975-06-12 Boucle a blocage
NL7507013A NL7507013A (nl) 1974-06-17 1975-06-12 Fase geblokkeerde lus.
DE19752526513 DE2526513A1 (de) 1974-06-17 1975-06-13 Phasenstarre schleifenschaltung
IT24357/75A IT1038921B (it) 1974-06-17 1975-06-13 Anello a fase bloccata per il trattamento di informazione
FR7518804A FR2275062A1 (fr) 1974-06-17 1975-06-16 Boucle a blocage
JP50072808A JPS584850B2 (ja) 1974-06-17 1975-06-17 イソウロツクル−プ

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US479604A US3878474A (en) 1974-06-17 1974-06-17 Phase locked loop

Publications (1)

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US3878474A true US3878474A (en) 1975-04-15

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US479604A Expired - Lifetime US3878474A (en) 1974-06-17 1974-06-17 Phase locked loop

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US (1) US3878474A (it)
JP (1) JPS584850B2 (it)
BE (1) BE830155A (it)
CA (1) CA1021411A (it)
DE (1) DE2526513A1 (it)
FR (1) FR2275062A1 (it)
GB (1) GB1507734A (it)
IT (1) IT1038921B (it)
NL (1) NL7507013A (it)
SE (1) SE7506561L (it)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4015083A (en) * 1975-08-25 1977-03-29 Bell Telephone Laboratories, Incorporated Timing recovery circuit for digital data
US4631497A (en) * 1984-06-05 1986-12-23 Plessey South Africa Limited Injection locked RF oscillator with control hoop
EP0420667A2 (en) * 1989-09-29 1991-04-03 Kabushiki Kaisha Toshiba Phase-synchronous controller for production of reference clock signal in optical disk drive system
US5414741A (en) * 1993-10-14 1995-05-09 Litton Systems, Inc. Low phase noise oscillator frequency control apparatus and method
US20020193085A1 (en) * 2001-06-15 2002-12-19 Telefonaktiebolaget Lm Ericsson Systems and methods for amplification of a communication signal

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57107902U (it) * 1980-12-23 1982-07-03
JPH01171966U (it) * 1988-05-26 1989-12-06
JP5701149B2 (ja) * 2011-05-24 2015-04-15 三菱電機株式会社 高周波発振源
JP5634343B2 (ja) * 2011-07-05 2014-12-03 三菱電機株式会社 注入同期発振装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3189825A (en) * 1962-03-29 1965-06-15 Abbott W Lahti Phase-locked-loop coherent fm detector with synchronized reference oscillator
US3359505A (en) * 1965-04-03 1967-12-19 North American Phillips Compan Relaxation oscillator having combined direct and indirect synchronization
US3395360A (en) * 1965-12-24 1968-07-30 Philips Corp Circuit for combined direct and indirect synchronization of an oscillator
US3534285A (en) * 1968-06-19 1970-10-13 Honeywell Inc Digital phase control circuit for synchronizing an oscillator to a harmonic of a reference frequency
US3534284A (en) * 1967-11-15 1970-10-13 Bell Telephone Labor Inc Automatic phase-locking circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3189825A (en) * 1962-03-29 1965-06-15 Abbott W Lahti Phase-locked-loop coherent fm detector with synchronized reference oscillator
US3359505A (en) * 1965-04-03 1967-12-19 North American Phillips Compan Relaxation oscillator having combined direct and indirect synchronization
US3395360A (en) * 1965-12-24 1968-07-30 Philips Corp Circuit for combined direct and indirect synchronization of an oscillator
US3534284A (en) * 1967-11-15 1970-10-13 Bell Telephone Labor Inc Automatic phase-locking circuit
US3534285A (en) * 1968-06-19 1970-10-13 Honeywell Inc Digital phase control circuit for synchronizing an oscillator to a harmonic of a reference frequency

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4015083A (en) * 1975-08-25 1977-03-29 Bell Telephone Laboratories, Incorporated Timing recovery circuit for digital data
US4631497A (en) * 1984-06-05 1986-12-23 Plessey South Africa Limited Injection locked RF oscillator with control hoop
EP0420667A2 (en) * 1989-09-29 1991-04-03 Kabushiki Kaisha Toshiba Phase-synchronous controller for production of reference clock signal in optical disk drive system
EP0420667A3 (en) * 1989-09-29 1993-08-18 Kabushiki Kaisha Toshiba Phase-synchronous controller for production of reference clock signal in optical disk drive system
US5414741A (en) * 1993-10-14 1995-05-09 Litton Systems, Inc. Low phase noise oscillator frequency control apparatus and method
US20020193085A1 (en) * 2001-06-15 2002-12-19 Telefonaktiebolaget Lm Ericsson Systems and methods for amplification of a communication signal
US7068984B2 (en) * 2001-06-15 2006-06-27 Telefonaktiebolaget Lm Ericsson (Publ) Systems and methods for amplification of a communication signal

Also Published As

Publication number Publication date
JPS584850B2 (ja) 1983-01-28
FR2275062B1 (it) 1977-12-09
DE2526513A1 (de) 1976-01-02
IT1038921B (it) 1979-11-30
BE830155A (fr) 1975-10-01
NL7507013A (nl) 1975-12-19
CA1021411A (en) 1977-11-22
JPS5112761A (it) 1976-01-31
GB1507734A (en) 1978-04-19
FR2275062A1 (fr) 1976-01-09
SE7506561L (sv) 1975-12-18

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