US3844831A - Forming a compact multilevel interconnection metallurgy system for semi-conductor devices - Google Patents

Forming a compact multilevel interconnection metallurgy system for semi-conductor devices Download PDF

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US3844831A
US3844831A US00301570A US30157072A US3844831A US 3844831 A US3844831 A US 3844831A US 00301570 A US00301570 A US 00301570A US 30157072 A US30157072 A US 30157072A US 3844831 A US3844831 A US 3844831A
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layer
metal
metallurgy
dielectric layer
forming
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US00301570A
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E Cass
W Enichen
J Havas
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International Business Machines Corp
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International Business Machines Corp
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Priority to US00301570A priority Critical patent/US3844831A/en
Priority to FR7330996A priority patent/FR2204891B1/fr
Priority to CA180,181A priority patent/CA1089112A/en
Priority to DE2346565A priority patent/DE2346565C2/de
Priority to IT29047/73A priority patent/IT998625B/it
Priority to JP48105119A priority patent/JPS5246799B2/ja
Priority to GB4432073A priority patent/GB1433624A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the method consists of forming a first dielectric layer on a semiconductor substrate, forming the first interconnection metallurgy level on the first layer, depositing a second dielectric layer over the metallurgy layer wherein the second dielectric layer is a material different from the material of the first dielectric layer, forming via holes in the second dielectric layer of a diameter substantially equal to or larger than the width of the underlying interconnection lines of the first metallurgy pattern, and forming a second interconnection metallurgy system over the second dielectric layer with the conductive lines of the second metallurgy layer having a uniform width over the via holes.
  • FIG.1A A first figure.
  • This invention relates to the fabrication of semiconductor devices and, more particularly, to the fabrication of improved interconnection metallurgy systems for semiconductor devices that permits a more dense interconnection metallurgy pattern.
  • the device is conventionally fabricated on a master slice which is a small piece of semiconductor material, typically silicon, approximately one-eighth of an inch square, having thousands of diffusions capable of being connected together to form various circuits.
  • the individual devices are connected into circuits and to input-output terminals by a complex interconnection metallurgy system commonly employing two or three separate levels of circuitry separated by dielectric layers of material.
  • the first interconnecting metallurgy layer of the logic device interconnects the devices, both active and passive, into circuits and also provides a plane for introducing the circuits to circuit communications. The latter function usually consists of parallel lines connected to the individual circuits.
  • the second layer conventionally completes the circuit-to-circuit connection and makes contact to terminals which are connectable to a support such as a module substrate or card.
  • the second level usually consists primarily of parallel lines that are transverse to the aforementioned parallel lines of the underlying interconnection metallurgy level.
  • the support area for the metallurgy is the primary factor in determining its size.
  • the area occupied by the actual active and passive semiconductor devices utilized in the various circuits occupies a small amount of total area of the chip.
  • the lower limits of the width of an interconnection metallurgy stripe are imposed primarily by the photolithographic technology.
  • the line widths are on the order of 0.15 mils with a separation on the order of 0.15 mils for long lines.
  • the via pads on the underlying metallurgy layer are provided to prevent etching through the dielectric layer underlying the first level metallurgy when making via holes through the overlying second dielectric layer. If the pads are not provided, any misalignment of the mask forming the via holes would result in etching directly through the second overlying layer and also possibly the underlying dielectric layer.
  • a pad is provided on the second overlying metallurgy layer to prevent etching the underlying metallurgy stripe during subtractive etching of the upper layer. If the pad was not provided and a misalignment of the stripe over the via hole occurred, the etchant might etch away and break the conductive line in the lower underlying metallurgy system.
  • An object of this invention is to provide a new method for fabricating a multi-level interconnection metallurgy system for integrated semiconductor devices.
  • Another object of this invention is to provide a new method for fabricating multi-level interconnection metallurgy systems which permits greater circuit densities.
  • Another object of this invention is to provide a new method for fabricating multi-level interconnection metallurgy systems wherein the possibility of forming sharp projections on the passivating glass layer surfaces is minimized.
  • Yet another object of this invention is to provide a method of fabricating multi-level interconnection metallurgy systems without utilizing via pads.
  • a first layer of dielectric material is deposited on the surface of the semiconductor substrate, a first layer of metal deposited and formed into an interconnection metallurgy system by selective removal of portions of the layer of metal, a second dielectric layer deposited over the first metallurgy layer and underlying dielectric layer, which material of the second dielectric layer is dissimilar from the material of the first dielectric layer, forming via holes in the second dielectric layer of a diameter substantially equal to or larger than the width of the underlying conductive lines of the first metallurgy pattern using an etchant that is selective to the material of the second dielectric layer, forming a second metallurgy layer over the first dielectric layer wherein the second metallurgy layer has uniform width lines over the via holes.
  • FIG. IA is a top plan view illustrating via pad structure of interconnection metallurgy systems as practiced in the prior art.
  • FIG. 1B is an elevational view in cross-section taken on line 18 of FIG. 1A.
  • FIGS. 2 through 5 show a sequence of elevational views in broken cross-section of a multi-level interconnection metallurgy system illustrating the steps of the subject invention.
  • FIGS. 1A and 18 a via connection typical of the prior art between two layers of interconnection metallurgy.
  • Substrate is a semiconductor body having embodied therein various diffusions which form active and passive devices.
  • Body 10 as best shown in FIG. 1A, is covered with a passivating layer 12 typically thermal SiO
  • a first metallurgy layer 14 rests on layer 12 and makes contact to the various devices in body 10 through openings not shown.
  • a second overlying passivating layer 16 is deposited over metallurgy layer 14 and contains openings 18, commonly referred to as via holes.
  • a second metallurgy level 20 is deposited over dielectric layer 16 and extends through via hole 18 to make contact with the underlying metallurgy layer 14.
  • a third passivating layer 22 is deposited over second level metallurgy layer 20.
  • additional metallurgy layers can be deposited which are separated by dielectric layers containing via holes for establishing contact between the various layers. As is best shown in FIG. 1A, it is a common practice in the prior art to provide enlarged portions in each of the stripes, commonly referred to as via pads, about and below the via hole 18. These pads are shown in FIG. 1 by 14A as the via pad of the lower level metallurgy l4 and 20A as the via pad on the upper level metallurgy 20.
  • pads are provided to minimize the effect of minor mask misalignment.
  • Pad 14A in the first metallurgy level is provided so that in the event of a mask misalignment in forming the via hole, the etchant for etching through the first passivating layer l6 would not continue to etch through the underlying passivating layer 12. This is a possibility when the via hole is not directly over the lower stripe.
  • the lower via pad 14A acts therefore as an etchant stop.
  • the upper via pad 20A is provided so that in the event the stripe 20 is not directly over and covering the entire via hole, the etchant used in subtractive etching the blanket metal layer will not cut the underlying first level metallurgy stripe 14.
  • the diameter of the via pads in the metallurgy stripes must be significantly larger than the width of the stripe even though the misalignment probability may be relatively small.
  • a sharp lip is formed in the dielectric layer which is very detrimental to mask life. There is thus a minimum radial width between the via hole and the overlapping edge of the pad which must be maintained to prevent forming the sharp lip in the overlying passivating layer.
  • the aspect limiting the size of an integrated circuit device is the space required for supporting the necessary interconnection metallurgy circuitry. It can easily be seen that when parallel lines contain via pads, the spacing must be significantly increased. Further, in designing the metallurgy circuitry it must be designed to accommodate the possibility of two pads on adjacent parallel stripes occurring in side-by-side relation.
  • FIGS. 2 throughS there is illustrated a sequence of cross-sectional views illustrating the process of the invention for forming a more dense metallurgy system through the elimination of via pads.
  • FIG. 2 shows a typical semiconductor substrate 10 having a surface passivating layer.
  • the passivating layer overlying the surface of device 10 consists of a lower layer 30 of thermal SiO and an overlying layer 32 of saw...
  • Deposited on the surface of layer 32 is a first interconnection metallurgy layer 34 formed by conventional fabrication techniques.
  • FIG. 2 illustrates only a single stripe of an interconnection metallurgy layer which stripe extends longitudinally in a direction transverse to the plane of the drawing.
  • Metallurgy layer 34 can be fabricated by any suitable technique, as for example, masking with a resist and subtractive etching, masking and sputter etching, or by lift-off techniques, known to the prior art.
  • a significant aspect of the metallurgy system 34 is that no via pads are provided under the via openings.
  • a second dielectric layer 36 is deposited over first metallurgy layer 34 and a via hole 38 made through layer 36 over the stripe 34. Opening 38 is made by conventional photolithographic techniques and subtractive etching.
  • An important aspect of this invention is providing dissimilar materials for layers 32 and 36. The etchant used for forming via opening 38 in layer 36 must not significantly affect the material of layer 32.
  • a suitable combination of such layers is layer 32 of Si N and layer 36 of SiO:.
  • An etchant for SiO which is typically hydrofluoric acid buffered with ammonium fluoride, does not significantly affect silicon nitride. Thus, a mask misalignment which results in exposing the lower layer to the etchant of the upper layer will not result in openings in the lower layer.
  • the materials of the two layers could be reversed with layer 36 being silicon nitride, which could be etched by hot ammonium dihydrogen phosphate at 200C. While this etchant affects SiO it does not do so at a significant rate.
  • Al O for the first dielectric layer and the second layer formed of SiO
  • the etchant for SiO i.e., a buffered HF solution, does not significantly affect Al- O
  • another combination is forming the first dielectric layer of thermal oxide, and the second dielectric layer of pyrolytically deposited SiO at relatively low temperatures of the range of 400-550C.
  • the pyrolytically deposited layer of SiO etches at a very significantly higher rate than the SiO layer formed by thermal oxidation.
  • the upper level interconnection metallurgy system is fabricated preferably by a lift-off technique.
  • a layer of photoresist 40 is deposited on the surface of dielectric layer 36 after via holes 38 have been formed, and the resist exposed and developed to form a reverse pattern of the desired second level metallurgy.
  • a blanket layer 42 of metal is then deposited over the surface of the resultant substrate as shown in FIG. 4. Where portions of the resist layer 40 have been removed, the layer of metal 42 is in direct contact with the dielectric layer 36 and the first level metallurgy 34 through the via hole 38.
  • the substrate is exposed to a resist solvent which removes the layer 40 and all the overlying portions of metal layer 42.
  • the second level metallurgy 42 can be fabricated without exposing the first level metallurgy 34 to an etchant which significantly affects same. Any slight misalignment of the mask for forming the upper interconnection metallurgy pattern will have no adverse affect on the underlying metallurgy.
  • Any suitable type of resist can be utilized including organic photoresists and metals, such as aluminum. When the first and second metallurgy levels are of aluminum, obviously aluminum cannot be used as a resist. However, there are other types of metals which are dissimilar and which can be utilized.
  • a third dielectric layer 44 is deposited over the second level metallurgy interconnection pattern 42 and dielectric layer 36. If necessary or desirable, the same basic procedures could be utilized to form a third level of metal.
  • the first level metallurgy conductive pattern 34 does not employ via pads as is common in the prior art as illustrated in FIGS. 1A and 1B.
  • the stripe can have substantiallythe same or slightly greater width than the diameter of the via hole.
  • both first and second metallurgy interconnection patterns are formed of aluminum, or aluminum alloys such as aluminum-copper, aluminum-silicon (as described in US. Pat. No. 3,382,568), or aluminumcopper-silicon.
  • aluminum alloys such as aluminum-copper, aluminum-silicon (as described in US. Pat. No. 3,382,568), or aluminumcopper-silicon.
  • other metals or composite laminated metal layers such as Cr-Ag-Cr, Cr-Cu-Cr (as disclosed in US. Pat. No. 3,46l,357), or Ta-Au-Ta (as disclosed in U.S. Pat. No. 3,617,816), and the like, could be utilized.
  • a modification of the aforedescribed process consists of utilizing in the second underlying metallurgy layer a metal or combination of metals dissimilar from the first metal interconnection metal.
  • the lower first metallurgy level can be formed of a composite laminated layer consisting of a layer of silver sandwiched between layers of chromium, and the second overlying metallurgy layer formed of aluminum or aluminum alloys.
  • the aluminum etchant used for subtractively etching the upper overlying metallurgy layer must be an etchant which does not materially affect chromium or silver.
  • a suitable etchant for aluminum is a solution of hydrogen peroxide and ammonium fluoride.
  • Another combination of metallurgies is a lower composite layer consisting of a layer of copper sandwiched between layers of chromium, and an overlying second level metallurgy of aluminum or aluminum alloys. The same aluminum etch described previously does not significantly affect copper.
  • Another example of a metallurgy combination is a first lower composite layer consisting of a layer of gold sandwiched between layers of tantalum, and an overlying second metallurgy level consisting of a layer of silver sandwiched between layers of chromium.
  • Suitable chromium and silver etchants are chromate etchants and ferric chloride solutions for gold and potassium permanganate solutions, and potassium ferric cyanide solutions for chromium, which will be used to fabricate the upper level since they do not significantly affect the lower tantalum and gold layers.
  • the tantalum and gold layers of the first level are preferably formed by sputter etching.
  • Another combination of metals suitable for use in the method of the invention is a lower first level composite layer of gold sandwiched between layers of tantalum, and a second overlying layer of copper sandwiched between layers of chromium.
  • the important aspect of the aforedescribed embodiments is that the two metallurgies be dissimilar and that an etchant be used on the upper level of metal in a subtractive etching process whereby the lower metallurgy level is not affected by the etchants for the upper metals in the event that there is a misalignment of masks which might leave a portion of the lower metallurgy level exposed through the via opening.
  • a method of fabricating a multi-level interconnection metallurgy system for an integrated semiconductor device comprising forming a first dielectric layer on the surface of a semiconductor substrate,
  • first layer of first metal on said first dielectric layer, forming a first metallurgy interconnection pattern having uniform width stripes in the first layer of metal by selective removal of portions thereof,
  • said semiconductor substrate is silicon
  • said first dielectric layer is formed by thermal oxidation of said silicon substrate
  • said second dielectric layer is formed by pyrolytically depositing a layer of SiO at relatively low temperatures in the range of 400-550C.
  • a method of fabricating a multi-level interconnection metallurgy system for an integrated semiconductor device comprising forming a first dielectric layer on the surface of a semiconductor substrate,
  • first layer of metal on said first dielectric layer, forming a first metallurgy interconnection pattern having uniform width lines in the first layer of metal by selective removal of portions thereof,
  • first and second metallurgy layers are selected from the group consisting of aluminum and aluminum alloys.
  • said first layer of metal is formed of Ag, sandwiched between layers of Cr, and
  • said second layer of metal is formed of a metal selected from the group consisting of Al and Al aloys.
  • said first layer of metal is formed by depositing an initial layer of Cr, an intermediate layer of Cu, and a top layer of Cr, and
  • said second metal layer is formed of a metal selected from the group consisting of Al and Al alloys.
  • said first layer of metal is formed by depositing an initial layer of Ta, an intermediate layer of Au, and a top layer of Ta, and
  • said second layer of metal is formed by depositing an initial layer of Cr, an intermediate layer of Ag, and a top layer of Cr.
  • said first layer of metal is formed by depositing an initial layer of Ta, an intermediate layer of Au, and a top layer of Ta, and
  • said second layer of metal is formed by depositing an initial layer of Cr, an intermediate layer of Cu, and a top layer of Cr.
  • said first layer of metal is formed by depositing an initial layer of Cr, an intermediate layer of Ag, and a top layer of Cr, and
  • said second layer of metal is formed by depositing a layer of Al.
  • said second metal layer is formed of a metal dissimilar from the metal of said first metal layer, and said second metal layer is subtractively etched with an etchant that does not materially affect the metal of said first metal layer.

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US00301570A 1972-10-27 1972-10-27 Forming a compact multilevel interconnection metallurgy system for semi-conductor devices Expired - Lifetime US3844831A (en)

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Application Number Priority Date Filing Date Title
US00301570A US3844831A (en) 1972-10-27 1972-10-27 Forming a compact multilevel interconnection metallurgy system for semi-conductor devices
FR7330996A FR2204891B1 (cs) 1972-10-27 1973-08-22
CA180,181A CA1089112A (en) 1972-10-27 1973-09-04 Method of forming a compact multi-level interconnection metallurgy system for semiconductor devices
DE2346565A DE2346565C2 (de) 1972-10-27 1973-09-15 Verfahren zur Herstellung von leitenden Verbindungen zwischen übereinanderliegenden Metallisierungslagen bei integrierten Halbleiteranordnungen
IT29047/73A IT998625B (it) 1972-10-27 1973-09-18 Procedimento per la fabbricazione di sistemi di collegamento perfezio nati in particolare per dispositivi semiconduttori
JP48105119A JPS5246799B2 (cs) 1972-10-27 1973-09-19
GB4432073A GB1433624A (en) 1972-10-27 1973-09-21 Multi-level interconnection system

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US00301570A US3844831A (en) 1972-10-27 1972-10-27 Forming a compact multilevel interconnection metallurgy system for semi-conductor devices

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JP (1) JPS5246799B2 (cs)
CA (1) CA1089112A (cs)
DE (1) DE2346565C2 (cs)
FR (1) FR2204891B1 (cs)
GB (1) GB1433624A (cs)
IT (1) IT998625B (cs)

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US3983284A (en) * 1972-06-02 1976-09-28 Thomson-Csf Flat connection for a semiconductor multilayer structure
DE2709986A1 (de) * 1976-04-29 1977-11-17 Ibm Verfahren zum herstellen von koplanaren schichten aus duennen filmen
DE3034900A1 (de) * 1979-09-17 1981-04-09 Mitsubishi Denki K.K., Tokyo Verfahren zur herstellung einer halbleitervorrichtung
DE3033513A1 (de) * 1979-10-09 1981-04-30 Mitsubishi Denki K.K., Tokyo Verfahren zur herstellung einer mehrheitschichtverbindung
US4296272A (en) * 1979-11-30 1981-10-20 Rca Corporation Composite substrate
US4307179A (en) * 1980-07-03 1981-12-22 International Business Machines Corporation Planar metal interconnection system and process
US4311727A (en) * 1976-05-06 1982-01-19 Compagnie Internationale Pour L'informatique Cii Honeywell Bull (Societe Anonyme) Method for multilayer circuits and methods for making the structure
US4321284A (en) * 1979-01-10 1982-03-23 Vlsi Technology Research Association Manufacturing method for semiconductor device
US4331700A (en) * 1979-11-30 1982-05-25 Rca Corporation Method of making a composite substrate
US4423547A (en) 1981-06-01 1984-01-03 International Business Machines Corporation Method for forming dense multilevel interconnection metallurgy for semiconductor devices
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WO1991007775A1 (en) * 1989-11-16 1991-05-30 Polycon Hybrid circuit structure and methods of fabrication
US5096124A (en) * 1990-10-05 1992-03-17 Halliburton Company Burner apparatus
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US5282922A (en) * 1989-11-16 1994-02-01 Polycon Corporation Hybrid circuit structures and methods of fabrication
US5416278A (en) * 1993-03-01 1995-05-16 Motorola, Inc. Feedthrough via connection
US5453401A (en) * 1991-05-01 1995-09-26 Motorola, Inc. Method for reducing corrosion of a metal surface containing at least aluminum and copper
US5612254A (en) * 1992-06-29 1997-03-18 Intel Corporation Methods of forming an interconnect on a semiconductor substrate
US5635423A (en) * 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure
US5736457A (en) * 1994-12-09 1998-04-07 Sematech Method of making a damascene metallization
US5739579A (en) * 1992-06-29 1998-04-14 Intel Corporation Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections
US5828121A (en) * 1994-07-15 1998-10-27 United Microelectronics Corporation Multi-level conduction structure for VLSI circuits
US6190928B1 (en) * 1998-08-14 2001-02-20 Mosel Vitelic Incorporated Method for actually measuring misalignment of via

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US4045594A (en) * 1975-12-31 1977-08-30 Ibm Corporation Planar insulation of conductive patterns by chemical vapor deposition and sputtering
US4029562A (en) * 1976-04-29 1977-06-14 Ibm Corporation Forming feedthrough connections for multi-level interconnections metallurgy systems
DE2642471A1 (de) * 1976-09-21 1978-03-23 Siemens Ag Verfahren zur herstellung von mehrlagenverdrahtungen bei integrierten halbleiterschaltkreisen
DE2936724A1 (de) * 1978-09-11 1980-03-20 Tokyo Shibaura Electric Co Halbleitervorrichtung und verfahren zu ihrer herstellung
JPS55138868A (en) * 1979-04-17 1980-10-30 Toshiba Corp Bipolar integrated circuit and method of fabricating the same
DE3218309A1 (de) * 1982-05-14 1983-11-17 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von integrierten mos-feldeffekttransistoren mit einer aus metallsiliziden bestehenden zusaetzlichen leiterbahnebene
JPH0644593B2 (ja) * 1984-11-09 1994-06-08 株式会社東芝 半導体集積回路装置
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US3597667A (en) * 1966-03-01 1971-08-03 Gen Electric Silicon oxide-silicon nitride coatings for semiconductor devices
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Cited By (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3983284A (en) * 1972-06-02 1976-09-28 Thomson-Csf Flat connection for a semiconductor multilayer structure
DE2709986A1 (de) * 1976-04-29 1977-11-17 Ibm Verfahren zum herstellen von koplanaren schichten aus duennen filmen
US4350743A (en) * 1976-05-06 1982-09-21 Compagnie Internationale Pour L'informatique Cii-Honeywell Bull (Societe Anonyme) Structure for multilayer circuits
US4311727A (en) * 1976-05-06 1982-01-19 Compagnie Internationale Pour L'informatique Cii Honeywell Bull (Societe Anonyme) Method for multilayer circuits and methods for making the structure
US4321284A (en) * 1979-01-10 1982-03-23 Vlsi Technology Research Association Manufacturing method for semiconductor device
DE3034900A1 (de) * 1979-09-17 1981-04-09 Mitsubishi Denki K.K., Tokyo Verfahren zur herstellung einer halbleitervorrichtung
DE3033513A1 (de) * 1979-10-09 1981-04-30 Mitsubishi Denki K.K., Tokyo Verfahren zur herstellung einer mehrheitschichtverbindung
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GB1433624A (en) 1976-04-28
DE2346565A1 (de) 1974-05-02
JPS4975290A (cs) 1974-07-19
FR2204891A1 (cs) 1974-05-24
DE2346565C2 (de) 1983-11-10
JPS5246799B2 (cs) 1977-11-28
FR2204891B1 (cs) 1977-08-05
CA1089112A (en) 1980-11-04
IT998625B (it) 1976-02-20

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