US3797222A - Digital electronic timepiece having a perpetual calendar display device - Google Patents

Digital electronic timepiece having a perpetual calendar display device Download PDF

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Publication number
US3797222A
US3797222A US00295194A US3797222DA US3797222A US 3797222 A US3797222 A US 3797222A US 00295194 A US00295194 A US 00295194A US 3797222D A US3797222D A US 3797222DA US 3797222 A US3797222 A US 3797222A
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Prior art keywords
month
signals
date
signal
day
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US00295194A
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English (en)
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T Kato
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Seiko Instruments Inc
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Seiko Instruments Inc
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Priority claimed from JP46078115A external-priority patent/JPS4843671A/ja
Priority claimed from JP46078116A external-priority patent/JPS4843672A/ja
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G9/00—Visual time or date indication means
    • G04G9/0082—Visual time or date indication means by building-up characters using a combination of indicating elements and by selecting desired characters out of a number of characters or by selecting indicating elements the positions of which represents the time, i.e. combinations of G04G9/02 and G04G9/08
    • G04G9/0094—Visual time or date indication means by building-up characters using a combination of indicating elements and by selecting desired characters out of a number of characters or by selecting indicating elements the positions of which represents the time, i.e. combinations of G04G9/02 and G04G9/08 using light valves, e.g. liquid crystals
    • G—PHYSICS
    • G04—HOROLOGY
    • G04G—ELECTRONIC TIME-PIECES
    • G04G9/00—Visual time or date indication means
    • G04G9/02—Visual time or date indication means by selecting desired characters out of a number of characters or by selecting indicating elements the position of which represent the time, e.g. by using multiplexing techniques
    • G04G9/025—Visual time or date indication means by selecting desired characters out of a number of characters or by selecting indicating elements the position of which represent the time, e.g. by using multiplexing techniques provided with date indication

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  • a digital electronic timepiece having a perpetual calendar display device comprises a standard oscillator for producing a pulse signal having a frequency high enough to serve as a time reference base, a divider circuit connected to the oscillator for dividing the pulse signal into a one-second signal having a frequency of one pulse per second, a series of counters, for counting the one-second signals and developing appropriate second, minute and hour signals and applying same to a display panel for displaying the time in seconds, minutes and hours, and a perpetual calendar display device for receiving the signals from the last of the series of counters and automatically and correctly displaying the month and the date of the month.
  • the perpetual calendar display device comprises a day counter for successively delivering a date signal on each successive day, a shift register connected to the day counter for providing an output signal corresponding to each successive month of the year, and electronic circuitry responsive to both the date signals and the signals from the shift register to automatically reset the day counter to commence counting at the first day and to shift the register to the proper month.
  • a display panel receives the date signals from the day counter and the month signals from the register and displays the correct month and date of the month.
  • FIG. 4 I l2-BIT 'I-BIT 3l-ABIC SHIFT REGISTER SHIFT REGISTER COUNTER I8 30 050005 ⁇ ? DRIVER DECODERIDRIVER ?)l 33 T -6a 7 SUN MON TUE WED THU FRI SAT MATRIX 8 9 IO M I2 l3 l4 l5 I6 l7 l8 I9 20 2
  • the present invention relates generally to a digital electronic timepiece and more particularly to a digital electronic time piece having a perpetual calendar display device for automatically displaying the month and the correct date of each month irrespective of the different number of dates in the various months.
  • a perpetual calendar display device comprising a standard oscillator for producing a pulse signal having a frequency high enough to serve as a time reference base;
  • a divider circuit for dividing the pulse signal into 1- second signal having a frequency of one pulse per secend, a series of counters for counting the l-second signals and developing appropriate second, minute and hour signals and applying same to a display panel for displaying the time in seconds, minutes and hours, and perpetual calendar display means receptive of a oneday signal from the last of the series of counters for automatically and correctly displaying the month and the date of the month.
  • the perpetual calendar display means comprises a day counter for successively delivering a 1-day signal on each successive day, a shift register for providing an output signal at each successive month of the year, electronic circuitry responsive to the one-day signal and the signals from the shift register to automatically reset the day counter to commence counting at the first day and to shift the shift register to the proper month, and a display panel receptive of the one-day signals from the day counter and the output signals from the shift register to correctly display the month and date of the month.
  • FIG. 1 is a block diagram showing the electronic circuitry of one embodiment of a digital electronic timepiece having a perpetual calendar display device according to the present invention
  • FIG. 2 is a block diagram showing the electronic circuitry of another embodiment of a digital electronic timepiece having a perpetual calendar display device according to the present invention
  • FIG. 3 is a schematic view of a display panel connected to the electronic circuitry shown in either FIGS. 1 or 2; 4
  • FIG. 4 is a block diagram showing another portion of the electronic circuitry of a perpetual calendar display device according to the present invention.
  • FIG. 5 is a fragmentary view showing the details of a date display panel employed in the perpetual calendar display device of the present invention.
  • FIG. 1 One embodiment of the electronic circuitry employed in the electronic timepiece having a perpetual calendar display device of the present invention is shown in FIG. 1.
  • An oscillator 1 generates a pulse sig-' nal having a frequency high enough to serve as a time reference base and this pulse signal is applied to a divider circuit 2.
  • the divider circuit 2 divides the pulse signal into a one-second signal having a frequency of one pulse per second.
  • the l-second signal is fed to a 60-abic counter. 3 which delivers a corresponding succession of onesecond signals to an output line 3a and the counter 3 counts 60 such l-second signals and then delivers a corresponding l-minute signal to a 60-abic counter 4.
  • the counter 4 delivers a succession of l-minute signals to an output line 4a and counts 60 such l-minute signals and then supplies a l-hour signal to a 24-abic counter 5.
  • the counter 5 delivers a succession of l-hour signals to an output line 5a and counts 24 such l-hour signals and then delivers a l-day signal and applies same to a day counter 6.
  • the day counter 6 comprises a 3 l'-abic counter having 31 output terminals corresponding to the 31 maximum possible days in a month. In FIG. 1, only the last four output terminals are shown and these correspond to the 28th day, 29th day, 30th day and 31st day of a month.
  • the counter 6 counts the l-day signals from the counter 5 delivers a date signal once each successive day along a line 6a commonly connected to the output terminals.
  • Each signal produced from the outputs of the counters 3-6 are transmitted through a driver circuit (not shown in the drawings) along the lines 3a 6a to a display panel 12, such as shown in FIG. 3.
  • the display panel 12 comprises a plurality of individual display elements 8 11 each connected to one of the lines 3a-6a for displaying the appropriate time and date information.
  • the display element 8 includes in the upper right corner the letter S and is connected to the line 30 for displaying the time in seconds.
  • the display element 9 includes in the upper right corner the letter M and is connected to the line 4a for receiving the l-minute signal and accordingly displaying the time in minutes.
  • the display elements 10 and 11 include respectively the letters H and D and are connected to the lines 5a and 6a for respectively displaying the time in hours and the numerical date.
  • the counters 3-6 are of well-known construction and may comprise a series of flip-flop circuits connected in cascade and feeding the outputs in suitable stages back to the preceding stages or a series of gate circuits may be used.
  • the details of the display panel 12 and the correspond ing driving circuits are of conventional construction and therefore will not be further described.
  • the day counter 6 shown in FIG. 1 also includes a set of output lines 6b, 6c, 6d and 62 connected respectively to the output terminals 28, 29 30 and 31 corresponding to the 28th, 29th, 30th and 31st day of a month.
  • output lines 6b, 6c and 6e are respectively connected to gate circuits 13, 14 and 15 for the purpose hereinafter described.
  • the output line 6e is connected a 12-bit shift register 17 having 12 output terminals 1 12 corresponding respectively to the months from January through December.
  • a set oflines 17b, 17c, 17d and 17s are respectively connected to the output terminals 4, 6, 9 and 11 and these output terminals correspond to the months having only 30 days, i.e., April, June, September and November.
  • the lines 17b 17e are connected to the AND gate 15 and to an AND gate 16.
  • An output line 17a is connected to the output terminal 2 corresponding to the month of February which has either 28 or 29 days depending upon the presence of leap year and the output line 17a is connected to both the AND gate 13 and the AND gate 14.
  • An output line 17f is connected to the output terminal 12 corresponding to the month of December and connects the output terminal 12 to a four-abic counter 18.
  • the counter 18 counts four successive month signals appearing on the output terminal 12 and delivers a corresponding leap'year signal on a line 18a which is connected through a NOT gate 19 to the AND gate 13 and the line 18a is also connected directly to the AND gate
  • the AND gate 16 has three inputs including one input connected to the lines 17b-17e, another input connected to the outputs of the AND gates 13 and 14, and a third input for continuously receiving clock pulses during use of the device. Whenever a signal is present on all three inputs, the AND gate 16 will deliver clock pulses to the day counter 6 along a line 16a.
  • a date signal or l-day signal is delivered from theday counter 6 and applied to the display panel 12 which responds to the date signal and displays the correct date.
  • the date signal is also applied to the line 6b and fed to the AND gate 13. Since the shift register 17 is in the position corresponding to the month of January, no output signal appears on the output terminal 2 and consequently no signal is fed to the AND gate 13 and therefore the AND gate remains in its blocking state and no output signal is fed therefrom to the AND gate 16.
  • the date signals appearing on the lines 60 and 6d are blocked by the respective AND gates 15 and 14 due to the position of the shift register 17.
  • the date signal appearing on the line 6e is fed to the shift register 17 to shift the register to a state wherein an output month signal is produced at the output terminal 2 corresponding to the month of February.
  • the date signal appearing on the line 6e is also fed back to the counter as a reset signal to reset the counter in acondition to begin counting again at the first day. 1
  • each successive day is counted by the day counter 6 and a corresponding date signal is applied to the display panel 12 which displays the correct date.
  • the date signal appearing-on the line 6b is fed to the AND gate 13 coincidently with the output signal from the output terminal 2 to the shift register 17 and coincidently with the signal delivered from the NOT gate 19. Since signals are applied simultaneously to all of the inputs of the AND gate 13, the AND gate is placed in its gating state and delivers an output signal to the AND gate 16.
  • the AND gate 16 thus simultaneously receives three input signals comprising the output signal from the line 17a, the output signal from the AND gate 13 and the clock pulse signal whereby the AND gate 16 is placed in its gating state and passes the clock pulse signal on the line 16a to rapidly drive the day counter 6 and place same in a condition to begin counting with the first day.
  • three clock pulses are applied to the counter 6 to quickly drive the counter from the 28th day to the 31st day whereupon a reset signal appears at the output terminal 31.
  • the reset signal is fed back tothe counter to reset same in a condition to commence counting at the first day and the reset signal is applied to the register 17 to shift same to a condition wherein the output month signal is delivered from the terminal 3 corresponding to the month of March.
  • the gate circuit 16 When the shift register is in this state, the gate circuit 16 is maintained in its blocking state since the output terminal 3 is not connected to the line 17a and therefore this line does not deliver an input signal to the AND gate 16.
  • the day counter 6 commences counting from the first day in March and the days of March are counted in the same manner as those in J anuary and at the end of the 3 1st day, a reset signal is delivered along the line 6e to reset the shift register 17 to the output terminal 4 corresponding to the month of April and to also reset the day counter 6 to begin countingat the first day of the month of April.
  • the output terminal 4 corresponding to the month of April is connected via the line 17b to the AND gates 15 and 16 and thus on the 30th day of April, the signal produced on the line 6d cooperates with the signal from the output terminal 4 of the shift register 17 to operate the AND gate 15 which then delivers a signal to the AND gate 16.
  • the AND gate 16 simultaneously receives three input signals thereby enabling the clock pulse signal to be applied along the line 16a to the day counter 6 to cause a reset signal to be produced on the line 6e to thereby reset the day counter 6 and shift the shift register 17 to the output terminal 5 corresponding to the month of May.
  • the days in the months of May, July, August, October and December are counted and displayed in the same manner as those in January, and March whereas the days in the months of June, September and November are counted and displayed in the same manner as those in the month of April.
  • the clock pulse signal is used to produce the reset signal on the line 6e on the 30th day of each month.
  • the counter 6 is reset on the 3 1st day of each month and the shift register 17 shifts the signal to the next succeeding output terminal.
  • the output terminal 12 of the shift register 17 applies a signal to the counter 18 once each year.
  • the counter 18 counts four signals and then applies a leap year signal along the line 18a to operate the gate circuit 14 on the 29th day of February during each leap year.
  • the date signal appearing on the line 66 coacts with the output signal from the output terminal 2 of the shift register 17 to operate the AND gate 14 and place same in its gating state whereby the AND gate 14 delivers a signal to the AND gate 16.
  • the AND gate 16 is placed in its gating state in response to the simultaneous application of the signal from the output terminal 2 of the shift register 17, the clock pulse signal, and the output signal from the AND gate 14 whereupon the AND gate 16 delivers a signal along the line 16a to the day counter 6 to quickly drive the day counter 6 to the 31st day as delineated above.
  • the leap year signal is applied to the NOT gate 19 and the NOT gate does not then deliver an output signal to the AND gate 13 and therefore the AND gate 13 is maintained in its blocking state on the 28th day of February thereby preventing operation of the AND gate 16.
  • FIG. 2 Another embodiment of the electronic circuitry employed in the electronic timepiece having a perpetual calendar display device according to the present invention is shown in FIG. 2.
  • This circuitry is similar to that shown in FIG. 1 except that a' resetting circuit 16a is employed instead of the AND gate circuit 16.
  • the resetting circuit 16a has an output connected to both the day counter 6 to reset the counter and to the shift register 17 to reset the register.
  • the AND gates 13, 14 and 15 each have and output line connected to the resetting circuit 16a and an output of the day counter 6 is also applied as an input to the resetting circuit 16a.
  • the AND gate 13 is connected on its input side to the output terminal 2 corresponding to the month of February of the shift register 17; the AND gate 14 is connected on its input side to the output terminal 2 of the shift register 17 as well as to the counter 18; and the AND gate 15 is connected on its input side to the output terminals 4, 6, 9, 11 of the shift register 17 corresponding respectively to the months of April, June, September and November.
  • the day counter 6 produces an output signal at the output terminal 28 and this signal is applied along the line 6b to the AND gate 13.
  • the output terminal 2 of the shift register 17 applies a signal along the line 17a to the AND gate 13 thereby placing the gate in its gating state whereupon an output signal is applied to the resetting circuit 16a.
  • the resetting circuit then delivers a reset signal to the day counter 6 to reset the counter in a condition to begin counting at the first day and also delivers a reset signal to the shift register 17 to shift the register into a state wherein an output month signal is produced at the output terminal 3 corresponding to the month of March.
  • the days of March are counted in the same manner as those in January and at the end of the 31st day, a reset signal is delivered from the output terminal 31 of the day counter 6 and applied along the line 6e to the shift register 17 to shift same into a state wherein an output signal is delivered at the output terminal 4 corresponding to the month of April.
  • an output signal is produced at the output terminal 30 of the day counter 6 and applied along the line 6d to the AND gate 15.
  • an output signal is present on the output terminal 4 of the shift register 17 and applied along the line 17h to the AND gate 15 to place the AND gate in its gating state whereupon the gate passes a signal to the resetting circuit 16a which in turn applies a reset signal to both the shift register 17 to shift same into a state wherein an output signal is produced at the output terminal 5 and at the same time to the day counter 6 to reset same.
  • the circuitry shown in FIG. 2 also corrects for the 1 day difference in the number of days in a leap year and for this purpose, the output terminal 12 of the shift register 17 corresponding to the month of December is connected to a four-abic counter 18 which counts four successive signals appearing on the output terminal 12 and then delivers a leap year signal along a line 18a.
  • the line 18a is connected to the AND gate 14 and to the NOT gate 19 and therefore the presence of the leap year signal on the lines 18a maintains the AND gate 13 in its blocking state on the 28th day of February and places the AND gate 14 in its gating state on the 29th day of February.
  • the display portion comprises a display panel 20 composed of a day display section 21 for displaying the day of the week, a date display section 22 for displaying the date, a month display section 23 for display- 7 ing the month, and 'a leap year section 24 for displaying the presence of a leap year.
  • the date display section 22 is shown in more detail in FIG; and comprises a covering panel 25 made of opaque material having formed therein an array of date numerals indicating the 31 possible dates of a month.
  • a series of photoelectric elements 27 is disposed beneath the covering panel 25 and function to emit light for making visible the date numerals in response to individual energization of the photoelectric elements.
  • the photoelectric elements may comprise liquid crystals or light-emitting diodes or any other similarly functioning photoelectric components.
  • Two electrode sheets 26 and 28 are disposed on opposite faces of the photoelectric elements 27 and function to apply suitable voltage to the photoelectric elements to energize them.
  • the date signal produced by the day counter 6 is applied along the line 6a through a matrix circuit 29 to the date display section 22 to sequentially energize the photoelectric elements 27 to successively display the numerical dates.
  • the correct date is always displayed on the display panel.
  • the output terminal 31 of the day counter 6 is connected to a seven-bit shift register 30 which responds to the signal appearing at the terminal 31 to shift through a succession of seven different states.
  • the seven different output signals from the shift register 30 are applied through a decoder driver circuit 31 to the day display section 21 whereupon the seven days of the week are successively displayed.
  • the output signal from the output terminal 31 of the day counter 6 is also applied to the shift register 17 and the register 17 applies its output month signals through a decoder driver circuit 32 to the month display section 23 for displaying the correct month.
  • the output terminal 12 of the shift register 17 is connected through a decoder driver circuit and a driver circuit 33 to the leap year display section 24 for displaying the leap year.
  • the digital electronic timepiece having a perpetual calendar display device provides many advantages.
  • the first date of the month is automatically displayed after all of the dates of the preceding month have been displayed.
  • the device automatically corrects for the extra day appearing in each leap year
  • the device displays numerous types of time information such as the time in seconds, minutes and hours and the actual date in numerical date, day of the week, month and year.
  • an electronic timepiece having means for displaying the time in minutes and hours: means for continuously generating a succession of electric signals at a rate of one signal per day; and date display means receptive of said succession of signals for numerically displaying during each successive day the correct date of the month in numerical form, said date display means comprising resettable counting means receptive of said succession of electric signals for counting same and delivering a corresponding succession of electric date signals in successive groups corresponding respectively to the months of a year with each goup containing therein from 28 to 31 date signals corresponding respectively to the different dates in a month and operative in response to an electric reset signal to begin a new group, electric circuit means responsive to the date signals for developing said reset signal and applying same to said resettable counting means after the last date of each month to effect resetting of said resettable counting means and including means for driving said resettable counting means through 31 states corresponding to the 31 possible date signals during those months containing less than 31 dates and then developing said reset signal, and a date display section responsive to each group of date signals for successively
  • said electric circuit means includes leap year counting means for developing an electric leap year signal every 4 years, and means responsive to said leap year signal for developing said reset signal on the 29th day of February.
  • An electronic timepiece including month display means responsive to a succession of month signals for displaying the correct month; and wherein said electric circuit means includes means for repeatedly developing a succession of month signals corresponding respectively to the 12 months of the year and successively applying same to said month display means at the first day of each month.
  • An electronic timepiece according to claim 3; wherein said means for repeatedly developing a succession of month signal includes a shift register having 12 states corresponding to the 12 months of a year.
  • said means for driving said resettable counting means through 31 states comprises an AND gate having blocking and gating states and having an input side connected to receive the last date signal delivered by said resettable counting means in each group of date signals which contains from 28 to 30 date signals and connected to receive a series of high frequency clock pulses and having an output side connected to said resettable counting means for applying clock pulses thereto when said AND gate is in said gating state to drive same whereby'the clock pulses rapidly drive said resettable counting means through said 31 states to reset same at the end of those months having 28 to 30 days.
  • said means for driving said resettable counting means through 31 states includes a 12-bit shift register operative to develop a separate electric month signal during each month, and means connecting said shift register to said AND gate to apply only those electric month signals corresponding to months having a maximum of from 28 to 30 days to said input side of said AND gate to effect shifting of said AND gate from said gating state to said blocking state only when said last date signals and said electric month signals corresponding to months having a maximum of from 28 to 30 days are simultaneously applied thereto.

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  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
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US00295194A 1971-10-05 1972-10-05 Digital electronic timepiece having a perpetual calendar display device Expired - Lifetime US3797222A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP46078115A JPS4843671A (de) 1971-10-05 1971-10-05
JP46078116A JPS4843672A (de) 1971-10-05 1971-10-05

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US3797222A true US3797222A (en) 1974-03-19

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US (1) US3797222A (de)
CH (2) CH1453972A4 (de)
DE (1) DE2248872A1 (de)
FR (1) FR2156015B1 (de)
GB (1) GB1368866A (de)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3969886A (en) * 1971-06-30 1976-07-20 Kabushiki Kaisha Daini Seikosha Digital electronic watch for displaying both time and the time remaining within a preselected time period
US3975846A (en) * 1975-01-27 1976-08-24 Wecker Leon S Electronic calendar system
US4055749A (en) * 1976-11-26 1977-10-25 Kraushaar Jonathan M Electronic Hebrew calendar and date calculator
US4067185A (en) * 1974-09-23 1978-01-10 Ebauches S.A. Timepiece
US4102122A (en) * 1975-11-04 1978-07-25 Kabushiki Kaisha Daini Seikosha Electronic watch
US4152768A (en) * 1976-08-04 1979-05-01 Shinshu Seiki Kabushiki Kaisha Electronic apparatus with calendar
US4194196A (en) * 1977-10-25 1980-03-18 Mohiuddin Mohammed S Illuminated master calendar and message recording system
US4270194A (en) * 1974-10-31 1981-05-26 Citizen Watch Company Limited Electronic alarm timepiece
EP0063771A1 (de) * 1981-04-22 1982-11-03 Olympus Optical Co., Ltd. Schaltjahrkompensationssystem

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH613336B (fr) * 1976-10-04 Ebauches Sa Piece d'horlogerie electro-mecanique a calendrier.
DE2648160A1 (de) * 1976-10-08 1978-04-13 Bbc Brown Boveri & Cie Fluessigkristallanzeige fuer eine elektronische armbanduhr
JPS6037437B2 (ja) * 1977-03-30 1985-08-26 カシオ計算機株式会社 カレンダ表示装置
FR2421433A1 (fr) * 1978-03-30 1979-10-26 Casio Computer Co Ltd Dispositif d'affichage electronique
US4274146A (en) * 1978-06-12 1981-06-16 Casio Computer Co., Ltd. Calendar data display device for an electronic device
EP0008234A1 (de) * 1978-08-11 1980-02-20 Mackay, Simon Brooke, The Baron Tanlaw Elektronische Kalenderanordnung
JPS5587084A (en) * 1978-12-25 1980-07-01 Casio Comput Co Ltd Electronic watch

Citations (3)

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Publication number Priority date Publication date Assignee Title
US3333410A (en) * 1965-04-02 1967-08-01 Instr For Industry Inc Electronic clock-calendar
US3477222A (en) * 1967-04-24 1969-11-11 Lau Chun Leung Calendar clock device
US3516242A (en) * 1968-02-23 1970-06-23 Sprague Electric Co Visual display of time variable electric information

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3333410A (en) * 1965-04-02 1967-08-01 Instr For Industry Inc Electronic clock-calendar
US3477222A (en) * 1967-04-24 1969-11-11 Lau Chun Leung Calendar clock device
US3516242A (en) * 1968-02-23 1970-06-23 Sprague Electric Co Visual display of time variable electric information

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3969886A (en) * 1971-06-30 1976-07-20 Kabushiki Kaisha Daini Seikosha Digital electronic watch for displaying both time and the time remaining within a preselected time period
US4067185A (en) * 1974-09-23 1978-01-10 Ebauches S.A. Timepiece
US4270194A (en) * 1974-10-31 1981-05-26 Citizen Watch Company Limited Electronic alarm timepiece
US3975846A (en) * 1975-01-27 1976-08-24 Wecker Leon S Electronic calendar system
US4102122A (en) * 1975-11-04 1978-07-25 Kabushiki Kaisha Daini Seikosha Electronic watch
US4152768A (en) * 1976-08-04 1979-05-01 Shinshu Seiki Kabushiki Kaisha Electronic apparatus with calendar
US4055749A (en) * 1976-11-26 1977-10-25 Kraushaar Jonathan M Electronic Hebrew calendar and date calculator
US4194196A (en) * 1977-10-25 1980-03-18 Mohiuddin Mohammed S Illuminated master calendar and message recording system
EP0063771A1 (de) * 1981-04-22 1982-11-03 Olympus Optical Co., Ltd. Schaltjahrkompensationssystem
US4447160A (en) * 1981-04-22 1984-05-08 Olympus Optical Co., Ltd. Leap year compensation circuit

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FR2156015A1 (de) 1973-05-25
CH588110B5 (de) 1977-05-31
DE2248872A1 (de) 1973-04-12
GB1368866A (en) 1974-10-02
CH1453972A4 (de) 1976-08-31
FR2156015B1 (de) 1975-09-12

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