US3735109A - System for discovering a critical path in a network - Google Patents

System for discovering a critical path in a network Download PDF

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US3735109A
US3735109A US00148835A US3735109DA US3735109A US 3735109 A US3735109 A US 3735109A US 00148835 A US00148835 A US 00148835A US 3735109D A US3735109D A US 3735109DA US 3735109 A US3735109 A US 3735109A
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chain
gate
node
elements
signal
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J Berthelemy
P Boue
J Sauvan
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Moteurs SA D Et Const
SA D Etude De Construction De Moteurs fr
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06Q—INFORMATION AND COMMUNICATION TECHNOLOGY [ICT] SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES; SYSTEMS OR METHODS SPECIALLY ADAPTED FOR ADMINISTRATIVE, COMMERCIAL, FINANCIAL, MANAGERIAL OR SUPERVISORY PURPOSES, NOT OTHERWISE PROVIDED FOR
    • G06Q10/00—Administration; Management
    • G06Q10/06—Resources, workflows, human or project management; Enterprise or organisation planning; Enterprise or organisation modelling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/10—Geometric CAD
    • G06F30/18—Network design, e.g. design based on topological or interconnect aspects of utility systems, piping, heating ventilation air conditioning [HVAC] or cabling

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  • a plurality of node elements are interconnected by link elements together with an appropriate control center for simulating or modelling a network.
  • Three categories of lines interconnect and pass through the node elements.
  • One, a B chain conveys signals from node element to node element via respective link elements in a direction through the network.
  • a second, a 7 chain conveys signals in the direction opposite to the direction of the B chain.
  • the third, an B chain conveys signals in the same direction as the B chain and effectively forms a validation in the network-modelling circuit which is necessary for operation of the corresponding B chain.
  • Signals are advanced stepwise under supervision of a clock (part of the control center).
  • the networkmodelling circuit includes a circuit which is arranged to detect amongst the several link elements connected to each node element the first one, or the last one, or both the first and last ones which are reached by the B signal. This detection is employed to progressively validate the 7 line. Loops are detected either by exciting signals in the a chain before B excitation from a target point of the network and interrupting the excitation after a signals have progressed as far as they can, or alternatively by artificially rendering all the y lines conductive before B excitation and exciting the y chain from a target point and then interrupting the y excitation after -y signals have progressed as far as they may. in either case the loops and the parts of the circuit downstream of the loops remain capable of passing signals.
  • SHEET 2 (IF 5 T'IqnZ rengrawrmmm PATENTEU MAY 2 2197s SHEET S []F 5
  • the networks consists of a number of points or nodes or junctions interconnected by vectors or links.
  • the links can be weighted by values representative of steps, or power of advance required to pass from any node to an adjacent node; if this advance or progression is intermittent and stepwise, the weighting given any link indicates the number of steps necessary to progress through the link.
  • the origin of any link will be called the predecessor node and the end of any link will be called the successor node.
  • Operating a network to solve a problem usually means searching for a path in the network between a starting-point node and a target-point node.
  • Some problems may have more than one starting point and more than one target point. Given any starting point and any target point, there are usually a number of paths between them. Determining the shortest path between these points may be one problem, whereas other problems involve determining the longest path, also called the critical path or maximum path i.e., the path having the greatest number of steps. The latter kind of problem occurs inter alia in programming tasks using PERT (Program Evaluation Research Task) diagrams.
  • Network-modelling facilities for carrying out minimum and maximum path research or scheduling are known and usually comprise logic circuits grouped in two categories of elements allotted to the network nodes and links and called node elements and link elements respectively and interconnected by lines.
  • Path research comprises simulating the network path by transmitting signals which advance stepwise between consecutive node elements and dwell at each link element for a number of steps equal to the weight of such link element, as disclosed e.g., by U.S. Pat No.
  • each node element is provided with an AND-gate having )1 inputs, n denoting the number of links leading to the corresponding node.
  • the AND-gate opens only when the n lines extending from the n link elements preceding the node element are excited, whereafter the AND-gate output, which is connected to the p link elements after the node, delivers the signals into such link elements.
  • the node set as target point is therefore reached after a number of steps equal to the number of steps in the critical or maximum path between the starting point and the target point.
  • the link elements have means for detecting the last one of the link elements leading to a given node element which had provided an output signal to the AND-gate of this node element, for only this last link element has any chance of forming part of the critical path.
  • a network-modelling circuit having a plurality of node elements interconnected by link elements.
  • the link elements provide, with the node elements, three categories of lines interconnecting and passing through the node elements:
  • a first category forming a B chain for conveying signals from node element to node element via respective link elements in a predetermined direction through the network
  • a second category forming a 'y chain adapted to convey signals in a direction opposite to the said predetermined direction
  • a third category forming an a chain adapted to convey signals in the same direction as the B chain and extending through the node elements by way of OR gates and forming in the network a preset condition, or validation necessary for operation of the corresponding B chain.
  • a control center with a clock for supervising stepwise advance of signals along the B chain has means to initiate energization of the 7 chain at the end of such advance.
  • the B chain comprises in each node element an AND gate to whose inputs are connected the B lines from the several link elements connected to such node element.
  • the several link elements have associated therewith a circuit adapted to detect and select from the group of such several link elements the one which was the first one reached by a B signal; or the one which was the last one reached by a B signal (which may be termed the limiting link elements) or both the first and last ones reached by a B signal.
  • an AND gate on the 7 line extending through the link element so selected is energized, or validated.
  • the invention also provides a method of detecting loops in a network by exciting signals in a chain before any starting of the clock by triggering a chain, e.g., the a chain from at least one extreme (target or starting) point of the network and for a. time sufficiently long for the signal to travel as far as the end of the chain; and
  • FIG. 1 shows a network
  • FIG. 2 is a diagram showing critical path finding in the network of FIG. 1;
  • FIG. 3 shows another network in which critical path finding is difficult
  • FIG. 4 shows a network containing a loop
  • FIG. 5 shows an embodiment of node elements and link elements of a system according to the invention
  • FIG. 6 shows a predecessor node and the links extending therefrom
  • FIG. 7 shows an improved mesh or link element of use for loop detection in a network
  • FIG. 8 shows a variant of a node element for a special finding problem
  • FIG. 9 is a diagram showing how a node element can be adapted to minimum path finding in a network.
  • FIG. 10 shows a node element adapted as shown in FIG. 9.
  • the critical path A.E.F.C.D. in the example selected is determined with certainty.
  • a signal going from G to F along the link FG can never pass through F since the AND-gate within the node element Ii has two inputs, one connected to the link element F6 and the other connected to link element FC, and no signal frgm G can ever return along FC since the links BC and FC are dead-ends as regards paths between A and G. Consequently, the signaLcan never travel back along EF nor, therefore, along AE, and so the circuit cannot provide the longest path between A and G. In the case shown in FIG. I the same difficulty would have arisen if the target point chosen had been a node other than the node D. To determine critical, or maximum path, this system therefore has a serious shortcoming.
  • This invention is for improvements in or relating to critical path scheduling systems which can inter alia obviate these disadvantages and adapt such systems for the solution of a wide range of problems.
  • gates marked are OR-gates
  • gates marked 9 are AND-gates
  • a mesh or link element M of a system has on one side a predecessor node element N and on the other side a successor node element N Each node element is placed inside a solid-line frame, the element M being indicated by a symbolic arrow and the node elements N N being indicated each by a circle of hatching. Connections between node elements and mesh or link elements can be broken down into three categories B, y and 0: indicated by braces. The 6 connections are responsible for transferring critical path finding signals from the target point back to the starting point; this procedure is known as ,8 backwards finding.
  • connections are responsible for transferring a signal which originates at the starting point and which travels exclusively via links or meshes previously detected as able to form part of the critical path.
  • the function of the 0: connections will be described hereinafter.
  • the network is therefore embodied by a system comprising node elements, mesh or link elements and B, y and or lines forming what are called B, 'y and a chains.
  • Each node element has an AND-gate n 1 having n inputs E on the B chain, n denoting the number of meshes or links extending from the particular node concerned.
  • the output of gate 9 I is connected via OR-gate U12 to output S of the node element; the OR- gate U12 can also be energized from input E of the element through which the ,8 signal is applied if such element is the target point of the sought-for path as selected on a program switch board 300.
  • As many [3 interrogation lines 50 extend from output 8;, as links or meshes adjoin the node.
  • the interrogation lines 50' are connected to the mesh-element inputs E and extend to AND-gate n 3.
  • AND-gate 3 has clock signals from clock 262 applied to input l-Io of the mesh element M when AND-gate 3 is enabled by its other inputs, the Ho clock signals are applied to a backwards counter D 31 consisting of flip-flops, the transmission depending upon the following conditions being satisfied.
  • the successor node N has transmitted the B signal so that E is energized
  • the predecessor node Np has still not transmitted the B signal i.e., mesh-element input E, is energized.
  • the latter input is connected by a B setting line 51 to output S of the predecessor node element N
  • Output S is energized over an inverter l 2i provided that AND gate n 1 of element N is blocked (nonconductive), a condition which is detected at the output of OR-gate U12, and
  • the backwards counter D 31 is not in a state in which it must be blocked.
  • AND-gate n 7 whose function will be described in greater detail hereinafter detects the state of the counter 31 and connects, over inverter l 23 the last energization signal to AND-gate 3.
  • counter D 31 is set at a value equal to the weight allotted to the link, M.
  • a signal is then applied to input E of the node element of the target point and the clock supervising the advance of such signal along the ,8 chain is started.
  • AND-gate n 3 is open(conductive) and the counter 31 counts 1 step backwards at each clock pulse until the value is reached.
  • This 0 state is detected by AND-decoding gate a 4 which is connected to output 3 of link element M via OR-gate U11.
  • the 7 chain is formed of OR-gates 2 receiving at inputs E and 7 lines coming from the link elements extending to the particular node element concerned, each OR-gate 2 having another input E which is energized when a particular node element is to be the starting point.
  • the y lines enter link elements M via inputs E connected to output S of OR-gate U 2 of the predecessor elements N 1: leave the element M at S, which are connected to E of the successor node element N
  • the 7 line has an AND-gate n therein which is normally validated by inverters l 22 (whose function will be described hereinafter).
  • AND-gate 5 opens (becomes conductive) only if the output of decoding AND-gate n 4 of backwards counter D 31 indicates that the same has returned to 0, this condition being transmitted by line 49.
  • a signal applied to the starting-point node element via input E or OR-gate U 2 can travel over the lines of the 'y chain only when the B signal has reached the starting point after having energized the AND-gates 245 of the links along which it has travelled.
  • any given predecessor node only the AND-gate Q 5 of the last link element M to pass the )8 signal need be validated.
  • This two-state device need not be provided if the backwards counters D 31 cease backwards counting not only when they have reached the 0 state but only when the next clock pulse has returned all their two-state devices to the 1 state.
  • This state corresponds to the highest binary number which the backwards counter can represent (2" 1 in the case of n two-state devices). This state will hereinafter be called the 1 state for convenience.
  • AND-gate n 7 detects that all the two-state devices are in the l position and delivers a signal which acts via I 23 to inhibit AND-gate 0 3 and to block the backwards counter D 31 in this 1 state. Simultaneously the AND-gate n 7 keeps output S energized via OR-gate U 11 (line 71), taking the place of the signal output from AND-gate 244..
  • the backwards counter D 31 of a link element decreases by l at each clock pulse if the following conditions exist:
  • the ,8 signal passes through a node element Q 1 validated) when all the backwards counters of the links for which it is the predecessor are at either 0 or l;
  • the AND-gate n 5 of the 7 line of a link element M is validated only by the 0 state of the backwards counter.
  • Path length is indicated by the number of steps made by the clock as counted in counter 200 between the start of search and the time at which search is stopped by the appearance of the B signal at output 8;, of the node marked as starting point.
  • the clock stops only when the backwards counter of the last link extending from the starting point has returned to 0.
  • the 7 signal travels for one clock signal period along a path other than the longest. The speed of the system is such that this event does not affect a display system controlled from the 'y lines.
  • the system includes a control center 201 including the clock 202, the clock pulse counter 200, and connecti'ons for stopping the clock when the B signal has passed through the AND-gate 1 of the startingpoint node element. This stopping can be under the control of an ordinary AND-gate which detects coincidence between the selection of the node considered to be the starting point and the passage of the B signal through such node.
  • the control center has other automatic functions which will be mentioned hereinafter; it is of conventional construction and uses logic circuits and flip-flops.
  • the circuits hereinbefore referred to can be built using any appropriate technology. More particularly in the case of an electronic system, the backwards counter can take the form of master-slave type flipflops which change their state at the end of the clock pulse. Using JK two-state devices or any other flip-flop system would merely require reversal of clock signal polarity.
  • the critical path indicated by the path of travel of the 7 signal can be recorded or displayed; in the latter event the display can be formed either by the nodeelement outputs or by the link-element outputs or by both on the 7 chain.
  • the display can therefore be obtained by sampling at the outputs S and/or 8,.
  • Link display gives a fuller indication of the critical path, but node display is cheaper than link display since there are fewer nodes than links or meshes in a network.
  • FIG. 5 also shows a link hierarchy circuit.
  • two or more backwards counters D 31 may return to zero simultaneously and also be the last to pass the B signal towards the predecessor node element N,.. .
  • the two backwards counters remain simultaneously blocked in the state at the end of path finding and do not change over to the l state and so they will validate two AND-gate n on the 7 lines which leave the predecessor node element at S thus giving an indication that there are two critical paths having the same number of steps.
  • the 7 signal will travel via these two paths and cause them to be displayed or recorded.
  • a hierarchy line 61 extends through all the link elements having the same predecessor, entering via input EH and leaving via SH, such link elements being classified along the hierarchy line 61 in a predetermined hierarchic order. The upstream and downstream ends of the line 61 are free.
  • a link element inhibitor can be used if it is required to study modifications of a network.
  • Such link element validates the corresponding input E2 of the AND-gate 241 of its predecessor node element Np right at the start of the B search. Its ANDgate n 5 in the -y path can never be validated, everything proceeding as if the B signal had passed along such link before passing along any other link.
  • means are provided for automatically inhibiting some link elements in dependence upon problem data and inter alia upon the selected target point and starting point.
  • the B signal must be able to go back from the target point along all the network links accessible from the starting point. This condition does not always exist, and F 16. 5 shows an a chain circuit which, once the starting point and the target point have been selected, automatically selects links suitable for requirements before search starts and inhibits all the other link elements i.e., all such link elements from which the target point is inaccessible.
  • OR-gate U 8 of a node element drives AND-gate n 14 in each link element connected to that node element and the output of AND-gate n 14 feeds an input of OR-gate U 8 of a predecessor node element to which the link is connected.
  • a second input of AND gate 0 14 is connected to an input W via which a link element validation signal is normally operative, arbitrary suppression of the latter signal causing the element to be inhibited.
  • an a signal arriving at E from output 8 passes through AND-gate n 14 and cancels the standing inhibition in which the backwards counter D 31 is maintained by the inverter 1 24.
  • the a signal continues on to output S and then to an input of a OR-gate U 8 of the predecessor element.
  • an input of the OR-gate U 8 of the node selected as target point can be energized to cancel the inhibition of the link elements from which such node is accessible.
  • Such excitation proceeds from the input E of the node element via which the B signal is injected into the target OR- gate U 12 via the line 81 entering OR-gate 8. Selectionof all the links from which the target point is accessible therefore occurs automatically as a result of selecting of the target node.
  • the system which includes the OR- gates U 8 of the node elements and the AND-gaten 2414 of the link elements is called the a chain.
  • FIG. also shows a display element 100 of the link element M, the element 100 being connected to output SV of OR-gate U 13 having two inputs, one of which is energized by the output of the AND-gate Q 5 on the 7 chain while the other is connected to the output of AND-gate O 20 which can be externally controlled via its input E, for indicating that the link in the network is selected by the a chain for energization.
  • finding the longest path in a network with a loop is nonsensical since the length of paths comprising one or more links of the loop is indeterminate because they can be lengthened as desired by the loop being passed around more than once. If the starting point and target point in a network of this kind are so chosen that the or each loop is not on any path interconnecting the, no erroneous result occurs, for if the loops are not accessible from the starting point they will not prevent the [3 signal from returning thereto, and if the target point is not accessible from the loops the same are eliminated by the a chain.
  • the a chain is a means of automatically detecting loops; OR-gate U 8 of the node element of the target point is energized in a loopless network, the signal travels at electronic speed along the a chain. If there is a loop in the network the first node element of the loop to be reached by the a signal receives the same again after it has gone round the loop, with the result that the chain formed by the OR-gate U 8 and AND-gate 14 of the loop nodes and links are self-holding. If the energization of the OR-gate U 8 of the target-point node element is interrupted by disappearance of the signal at E the or element persists along the chain in the loop node and link elements and in those other node and link elements from which the loop is accessible.
  • the OR-gate U 8 of the target-point node element can be energized in a first phase, hereinafter called the a phase, whereafter this validation can be interrupted. If there is a loop from which the target point is accessible, none of the output signals of the AND-gates Q 14 and OR-gates U 8 cease. If the display facilities are actuated by the outputs of the AND-gate 14, the links forming the or each loop and all the links from which such loop or at least one of such loops is accessible is indicated.
  • the OR-gate U 13 controls display (output SV) by means of the a signal when the AND-gate Q 20 is validated via input E-,.
  • a chain of this kind is already avail able in the form of the 'y chain if some way can be devised of systematically validating the AND-gates Q 5 of the uninhibited links so that the OR-gates U 2 of the nodes within the network OR-gate a signal applied to the gate U 2 of the starting-point node element along all the accessible loops.
  • the chain of gates which would normally be used just for the 7 phase is therefor used.
  • FIG. 7 shows a link element meeting all these requirements.
  • the link validation signal arriving via input W now acts also on AND-gate Q 5 via line 52. This does not disturb normal operation since any link element not receiving the validation W has its backwards counter D 31 blocked at l and its AND-gate Q 4 will never validate AND-gate O S.
  • the hierarchy can be inhibited by AND-gate '0 16 by suppression of a validation normally applied to input IH.
  • the zero state of the backwards counter D 31 can be imitated for the AND-gate Q 5 by OR-gate U 15 by the application of a signal to input E OR-gates U 17, U 18 and AND- gate .0 l9 serve as means for operating a display system connected to the output SV by means of the following signals:
  • the AND-gate O 7 has an extra input E whose function will be described hereinafter.
  • More than one starting and/or target point can be selected, in which event the or each loop accessible from at least one starting point or from which at least one target point is accessible or which is disposed on any path between any starting point and any target point is obtained.
  • the backwards counters are not used for any of these problems (the only purpose of the link weighting facility is to set the backwards counters of the uninhibited links to a value other than -l).
  • the system operates purely passively and is merely a set of gates. Solving these problems is only a minor feature of the system, its
  • OR-gate U 15 is not now energized via E and so AND-gate Q 5 can continue to operate only if the backwards counter D 31 is at 0.
  • the starting point and target point are set up normally. Setting-up or selecting the starting point not only energizes the node element input E but also connects its output S 3 to the control center.
  • the link weightings and the inhibitions are se lected, whereafter the clock is started, the whole system being controlled simultaneously by a single interrogation signal.
  • the B signal goes back step by step along all the possible paths, as hereinbefore described, and stops the clock immediately when it appears at output S 3 of the starting-point node element.
  • the longest path is immediately set up determined and the number of clock pulses (indicated by counter 200) equals the number of steps in such path.
  • any one node is taken as starting point and two or more other points are taken as target points, the target point connected to the starting point by the longest path can be determined and the longest path set up.
  • the system is interrogated in just the same way as in 8 except that two or more target points are set up.
  • the path displayed will lead to the furthest target point. Paths which on the way to a target point pass through some other target point are eliminated; this is the usual procedure since the idea behind the problem is to have a goal or aim consisting of two or more target points re quired to be reached as late as possible, and the first element of this aim is the one that counts.
  • the last starting point to be reached by the B signal is by definition the starting point of the longest of the critical paths found between the target point and each starting point.
  • the clock must therefore stop when the [3 signal has reached the gates 1 of all the nodes set up as starting points. However, the gate 0 1 of every starting point reached before the final starting point has been validated. If the input E of the OR-gate U 2 is energized, the critical paths from all the corresponding nodes are set up. The clock pulse counter will therefore indicate the number of steps in the sought-for path but there is no way of knowing the starting point.
  • the control system has provision for blocking the clock whenever the a signal appears at the output S 3 of a node element set up as starting point; if the operator releases the clock manually, e.g., by means of a push-button, after each blocking, the critical paths are set up consecutively in order of increasing length at each operation of the button. The final starting point from which a path is displayed on the display panel is the required starting point.
  • Another way is for the control system to have more elaborate provision such that the input E is energized only for the starting point whose AND-gate 241 was the last to have been reached by the B signal.
  • a 3-count backwards counter (2two-state devices) is suitable for the maximum number of nodes required to be set up simultaneously as starting points.
  • a backwards counter is allotted to each starting point by switching. At interrogation these backwards counters are in the 1 state (01).
  • the finding signal has reached a starting point, its backwards counter changes over to the state (00), and then in the next clock phase to the 1 state (1 1).
  • the control center has a set of gates serving to stop the clock when all the backwards counters to which starting points are allotted are in the O or l state.
  • the or each last starting point reached by the finding signal has its backwards counter blocked at 0 whereas the others are blocked at l. If energization of the starting-point inputs B is initiated by the 0 state of the respective backwards counter, the 7 signal can go only from the or each starting point which is the last to have been reached by the search signal.
  • This system therefore has the advantage of setting up the true longest critical path, and therefor of determining its starting point, without operator action.
  • the furthest starting point is the origin of more than one critical path, either all such paths can be set up or just one can be selected on a hierarchy basis.
  • N o path extending from a starting point to the target point via some other starting point can be set up since all starting points are inaccessible.
  • the OR-gate U 32 can restore the continuity of the a chain even though the node has been set up as starting point. This is essential to be able to deal with the problems mentioned in paragraph 2 and paragraph 3 in the case of more than one starting point.
  • the system hereinbefore described with its node elements and its link elements, can be used, if a few minor I additions are made to it, for finding the shortest path between a starting point and a target point in the network or even the starting-point/target-point pair connected by the shortest path in cases in which more than one starting point and more than one target point are set up.
  • the basic idea for this kind of searching is disclosed by US. Pat. No. 3,558,868 and involves a backwards B search in which any predecessor node element blocks all the link elements extending from it immediately the B signal has passed over one of such link elements.
  • inhibiting a link element is to prevent it from counting backwards so that its backwards counter D 31 never reaches 0. Blocking the backwards counter at 1 has the same effect.
  • each predecessor must gate the B signal of the first link energized thereby and not of the last link energized thereby.
  • the AND-gate (l 1 can be replaced by the circuit shown in FIG. 9. There can be seen the normal inputs 42, the output 43 and a control input 44. If the input 44 is in the 0 state, the circuit behaves like an AND-gate having an input 42 and an output 43, whereas if input 44 is energized the circuit is equivalent to an OR-gate.
  • the inputs 44 of all the points are connected to a general line whose logic state determines the kind of searching:
  • FIG. 10 shows a correspondingly modified node element, where the OR-gate U 12 previously used to set up the target point now forms the system output OR- gate. If input E 44 is at 0, the output of gate U 1b is not used and only the signal of AND-gate la appears at output S 3. If E is in the 1 state, a single signal at an input E causes 8,, tobe energized via OR-gate 1b and AND-gate 9 1c (with the output of OR-gate U 1b, any output from AND-gate 0 1a is merely redundant).
  • the display system can be lightened or supplemented by display of the nodes through the paths passed.
  • the node elements can include the circuit of the OR-gates U 17, U 18 and AND-gate Q 19 which prepare the display signal (output SV) in the link elements.
  • OR-gate U 17 always has applied to it the 'y signal which in the node element is the output of OR-gate U 2 (output S and OR-gate U 18 always has applied to its input the a signal which in the node element is the output of OR-gate U 8 (output S” leads to the node elements shown in FIG. 10.
  • the associated link elements are exactly the same as the link elements of FIG. 7, The previous elements are a means of solving and setting up solutions for all the network problems hereinbefore referred to.
  • a network-modelling circuit having a plurality of node elements (N,,, N,) interconnected by link elements (M), the link elements providing with the node elements three categories of lines interconnecting and passing through the node elements,
  • a first category forming a B chain for conveying signals from node element to node element via respective link elements in a predetermined direction through the network
  • a second category forming a 7 chain adapted to convey signals in a direction opposite to the said predetermined direction
  • a third category forming an a chain adapted to convey signals in the same direction as the B chain and extending through the node elements; OR gates (8) included in the a chain and forming in the network a validation necessary for operation of the corresponding B chain; and a control center (201) comprising a clock (202) for supervising a stepwise advance of signals along the B chain and for initiating energization of the "y chain at the end of such advance;
  • the B chain comprising in each node element an AND gate (1,) to whose inputs (E2) are connected the B lines (50) from the several link elements (M) connected to such node element, and said several link elements having associated therewith a circuit (3, 31, 4, 7, 11) adapted to detect and select from such several elements, the first one reached by a B signal, or the last one reached by a B signal or both the first and last ones reached by a Bsignal, and adapted, in response to such detection, to validate an AND gate (5) on the 7 chain extending through the link element so selected.
  • control center (201) includes circuit, means for transmitting a signal (E6; 0:) to the a chain for a time sufficient for such signal to travel along all the lines of the a chain which are accessible to the signal.
  • each link element comprises a circuit for rendering the -y chain conductive through the respective link element (M) in the absence of energization of the B chain, and wherein the control center (201) includes circuit means for transmitting a signal to the 7 chain for a time sufficient for such signal to travel along all the lines of the 7 chain which are accessible to the signal 4.
  • each of the link elements (M) is provided with an output or .display element (SV) connected both to the a chain and to the 7 chain by way of an AND gate (13; 19).
  • each of the node elements (N,,, N is provided with an output or display element (SV) connected both to the a chain and to the y chain by way of an AND gate.
  • SV output or display element
  • each B line effectively define a reverse direction through the network from respective successor node elements (N,) to respective predecessor node elements (N and wherein each B line comprises in each link element an AND gate (3) which is arranged to be validated by the output of the AND gate (1) of the predecessor node element (N periodically by the clock (202; Ho), the output of the said link AND gate (3) being connected to a counter (31) counting for a value corresponding to the weight attributed to the particular link element concerned, and a decoding gate (4) arranged to detect a pretermined count of the counter (31) and having an output (S2) which is connected to the B line of the predecessor node element (N,,) and which is arranged to validate and AND gate (5) in the 7 line.
  • a second decoding state (7) is connected to the output side of the counter (31), and is arranged to detect the occurrence of an extra pulse in the backwards counter after its count to the predetermined number to produce an output signal, the output signal being connected to replace the output signal of the first decoding gate (4) at the B input of the predecessor node element (N,,) and being connected to act via an inverter (23) to invalidate the said link AND gate (3).
  • link elements (N) are arranged to be inhibited by blocking of the counter in the extra pulse state by an inverter (24) controlled by the a chain.
  • each link element (M) is provided with an input for blocking the second decoding gate (7); and wherein each node element comprises an AND gate and an OR gate (1b) which is connected to be interrupted (1c) in response to external instructions (E44), said AND gate (10) and said OR gate (1b) being connected in parallel with the input (E2) of the B chain in the node element.
  • control center (201) is connected to initiate a signal in the -y chain after interruption of the clock (202).
  • a method of detecting loops in a network comprising the steps of:
  • the network-modelling circuit having a plurality of node elements (N,,, N.) interconnected by link elements (M), the link elements providing with the node elements three categories of lines interconnecting and passing through the node elements, a. a first category forming a B chain for conveying signals from node element to node element via respective link elements in a predetermined direction through the network,
  • a second category forming a 7 chain adapted to convey signals in a direction opposite to the said predetermined direction
  • a third category forming an or chain adapted to convey signals in the same direction as the B chain and extending through the node elements by way of OR gates (8) and forming in the network a validation necessary for operation of the corresponding B chain;
  • the control center comprising a clock (202) for supervising a stepwise advance of signals along the B chain and for initiating energization of the 7 chain at the end of such advance;
  • Method according to claim 15, comprising the step of artificially rendering all the 7 lines conductive before the clock (202) is started;

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US00148835A 1970-06-01 1971-06-01 System for discovering a critical path in a network Expired - Lifetime US3735109A (en)

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Cited By (7)

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EP0363017A2 (en) * 1988-09-09 1990-04-11 Matsushita Electric Industrial Co., Ltd. Schematic diagram generator and schematic diagram generating method
EP0517953A2 (en) * 1991-06-13 1992-12-16 Matsushita Electric Industrial Co., Ltd. Method for resource allocation and scheduling, and system therefor
US5561790A (en) * 1992-03-24 1996-10-01 International Business Machines Corporation Shortest path determination processes for use in modeling systems and communications networks
US5563994A (en) * 1994-03-11 1996-10-08 Harmon; Samuel T. System for graphically generating the sequence and temporal relationship between tasks in a project
US6038390A (en) * 1997-10-21 2000-03-14 Mci Communications Corporation Method of selecting spans for fiber cut simulations
US6917596B1 (en) * 2000-11-08 2005-07-12 Nortel Networks Limited Method of addressing physical problems of a topological network using a topology engine
US20090007040A1 (en) * 2005-01-17 2009-01-01 International Business Machines Corporation Apparatus for analyzing post-layout timing critical paths

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US3474240A (en) * 1965-02-12 1969-10-21 Charles F Marquis Apparatus for analyzing graphically plotted information
US3558868A (en) * 1966-02-26 1971-01-26 Snecma Method and system for finding or plotting an optimum path

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3474240A (en) * 1965-02-12 1969-10-21 Charles F Marquis Apparatus for analyzing graphically plotted information
US3558868A (en) * 1966-02-26 1971-01-26 Snecma Method and system for finding or plotting an optimum path

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0612021A3 (en) * 1988-09-09 1996-05-15 Matsushita Electric Ind Co Ltd Procedure for assigning levels among nodes in a network diagram.
EP0363017A3 (en) * 1988-09-09 1991-04-10 Matsushita Electric Industrial Co., Ltd. Schematic diagram generator and schematic diagram generating method
EP0612020A3 (en) * 1988-09-09 1996-07-17 Matsushita Electric Ind Co Ltd Node positioning procedure in a network diagram.
EP0612022A3 (en) * 1988-09-09 1996-08-07 Matsushita Electric Ind Co Ltd Node positioning procedure in a network diagram.
EP0612021A2 (en) * 1988-09-09 1994-08-24 Matsushita Electric Industrial Co., Ltd. Method for assigning levels to nodes of a net diagram
EP0612022A2 (en) * 1988-09-09 1994-08-24 Matsushita Electric Industrial Co., Ltd. Method for placement of nodes in a net diagram
EP0612020A2 (en) * 1988-09-09 1994-08-24 Matsushita Electric Industrial Co., Ltd. Method for placement of nodes in a net diagram
EP0363017A2 (en) * 1988-09-09 1990-04-11 Matsushita Electric Industrial Co., Ltd. Schematic diagram generator and schematic diagram generating method
US5550714A (en) * 1988-09-09 1996-08-27 Matsushita Electric Industrial Co. Ltd. Schematic generator and schematic generating method
EP0517953A2 (en) * 1991-06-13 1992-12-16 Matsushita Electric Industrial Co., Ltd. Method for resource allocation and scheduling, and system therefor
EP0517953A3 (en) * 1991-06-13 1993-12-22 Matsushita Electric Ind Co Ltd Method for resource allocation and scheduling, and system therefor
US5440675A (en) * 1991-06-13 1995-08-08 Matsushita Electric Industrial Co., Ltd. Method for resource allocation & scheduling, and system therefor
US5561790A (en) * 1992-03-24 1996-10-01 International Business Machines Corporation Shortest path determination processes for use in modeling systems and communications networks
US5563994A (en) * 1994-03-11 1996-10-08 Harmon; Samuel T. System for graphically generating the sequence and temporal relationship between tasks in a project
US6038390A (en) * 1997-10-21 2000-03-14 Mci Communications Corporation Method of selecting spans for fiber cut simulations
US6917596B1 (en) * 2000-11-08 2005-07-12 Nortel Networks Limited Method of addressing physical problems of a topological network using a topology engine
US7712063B2 (en) * 2005-01-17 2010-05-04 International Business Machines Corporation Apparatus for analyzing post-layout timing critical paths
US20090007040A1 (en) * 2005-01-17 2009-01-01 International Business Machines Corporation Apparatus for analyzing post-layout timing critical paths

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FR2093080A5 (US06589383-20030708-C00041.png) 1972-01-28
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