US3140530A - Method of making semiconductor units and the like - Google Patents

Method of making semiconductor units and the like Download PDF

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Publication number
US3140530A
US3140530A US90587A US9058761A US3140530A US 3140530 A US3140530 A US 3140530A US 90587 A US90587 A US 90587A US 9058761 A US9058761 A US 9058761A US 3140530 A US3140530 A US 3140530A
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US
United States
Prior art keywords
flanges
members
metal
cold
elements
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US90587A
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English (en)
Inventor
Anthony J Certa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Maxar Space LLC
Original Assignee
Philco Ford Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to BE562206D priority Critical patent/BE562206A/xx
Priority to GB34716/57A priority patent/GB869935A/en
Application filed by Philco Ford Corp filed Critical Philco Ford Corp
Priority to US90587A priority patent/US3140530A/en
Application granted granted Critical
Publication of US3140530A publication Critical patent/US3140530A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H01L23/045—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body the other leads having an insulating passage through the base
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K20/00—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating
    • B23K20/22—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating taking account of the properties of the materials to be welded
    • B23K20/233—Non-electric welding by applying impact or other pressure, with or without the application of heat, e.g. cladding or plating taking account of the properties of the materials to be welded without ferrous layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J5/00—Details relating to vessels or to leading-in conductors common to two or more basic types of discharge tubes or lamps
    • H01J5/20—Seals between parts of vessels
    • H01J5/22—Vacuum-tight joints between parts of vessel
    • H01J5/28—Vacuum-tight joints between parts of vessel between conductive parts of vessel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2893/00—Discharge tubes and lamps
    • H01J2893/0033—Vacuum connection techniques applicable to discharge tubes and lamps
    • H01J2893/0037—Solid sealing members other than lamp bases
    • H01J2893/0044—Direct connection between two metal elements, in particular via material a connecting material

Definitions

  • This invention pertains to a metal-working method, It has been developed in connection with problems of the fabrication of encapsulated semiconductor units of the power transistor type; but the invention relates more broadly to operations for strongly joining metallic members to one another, It includes a novel and characteristic utilization, in a cold-working process, of a generally known, plating treatment of metallic parts.
  • a specific object of the invention is connected with the encapsulation of delicate devices between metallic members; and still more particularly, the invention is concerned with mass-fabrication of the product.
  • At least one of the encapsulating members which also serves as a mounting member for the device to be encapsulated, is plated with a special, chemical-resistant substance on surfaces which include a peripheral joint area; and the members can then be effectively joined together without the conventional but difficult scratch-brushing, by cold- Welding said area to an opposite area of the other member.
  • the entire fabrication of small and delicate devices, such as semiconductor units, is greatly facilitated by this procedure; yet the strength and the sealing effects of the joints produced can be at least as good as those heretofore available.
  • a second specific object is to provide for the fabrication, including the hermetic encapsulation, of highly effective and dependable electronic devices, by a novel sequence of batch-continuous operations and the like, involving a minimum of time loss and complexity in connection with set-up procedures.
  • the method makes the difficult processes of producing said devices at least relatively simpler and thereby cheaper, mainly in their massfabrication.
  • FIGURE l is an enlarged cross-section of a typical semiconductor encapsulated by the new method.
  • FIG- URE 2 is an additionally enlarged, fragmentary, crosssectional view of an encapsulating mounting element.
  • FIGURE 3 is a similar View of encapsulating llange elements, these flange elements being shown in the left hand portion of the gure as they appear prior to the encapsulation process, and in the right hand portion of the figure as they appear pursuant thereto.
  • FIGURE 4 is a block diagram of a process for fabricating semiconductor units, according to this invention.
  • FIGURE l Before the new method is described, reference may best be made to the completed semiconductor unit illustrated in FIGURE l.
  • a cold-worked ange 3,140,53@ Patented July I4, 1964 structure 20 joins a peripheral part of a slug 11, a central part of which has a power transistor 12 thereon, with'the wall 13 of an overlying hat 14.
  • the slug provides a relatively large thermal mass of high conductivity to dissipate heat, generated during the use of the transistor.
  • Both the slug and the hat desirably consist of oxygen-free high conductivity copper.
  • the encapsulation of the transistor may be facilitated by an annular groove 15, machined into the transistor-mounting surface 16 of the slug, adjacent and concentrically with the flange structure 20, as more fully explained in Patent Number 2,932,684 of Kenneth R. Hales and Harry E. Godshall, which patent is assigned to the assignee of the present invention.
  • the present invention relates to the preparation of the elements of such and similar flange structures 20, for the cold-working thereof.
  • FIGURE 2 A small portion of a suitably prepared top surface 16 of slug 11, including a small portion of the groove 15, is shown in FIGURE 2; and it will be noted that the surface is provided with a plated surface layer 17.
  • This layer consists of so-called electroless nickel, that is, nickel containing from about three to about eleven percent of phosphorus, preferably the higher amount, such material probably containing phosphorus as a dissolved nickelphosphorus compound, and being applied to the copper by chemical procedures, not including electro-plating- Heretofore, preparation for the cold-working of similar structures was generally effected by scratch-brushing both members to be joined: slug 11 and hat 14.
  • FIGURE 3 is limited to illustrations, before and after the joining process, of metal portions which are forcibly squeezed in this process.
  • a more complete sectional representation o'f the an'ge Vstructure 20, including portions thereof which are deformed in particular ways, may have, for instance, either of the forms shown in the Hales- Godshall patent mentioned above.
  • the original total thickness of this structure (left hand portion) may in a typical example amount to about .03; it may be locally reduced (right hand portion) to a fraction thereof, such as about .004.
  • the flange structure 20 so produced is substantially homogeneous, from a top surface 21 to a bottom surface 22 thereof.
  • This structure 20 comprises intermingled copper particles of both original flange bodies 1S, 19, as schematically indicated by double cross hatching; and the actual metallic cross-section of body 20, which can be seen if a semiconductor unit is destroyed for purposes of inspection, shows the appearance of metal of the type known as mingled by cold-working. No separation between original ange elements is recognizable, even on strong magnification of the sectioned surfaces. Likewise, so far as appears on observation with magnifications up to almost 1000 diameters, no visible trace of the coating 17 of phosphorus-containing nickel remains in the mingled copper 20. On the other hand the original coating 17 is readily recognizable everywhere, in metallic cross-sections of the original copper slug, as diagrammatically represented in FIGURES 2 and 3.
  • this member may also be scratch-brushed immediately before cold-welding, or it may be plated with electroless nickel at any time.
  • a hermetic seal is obtained by properly squeezing a nickel-phosphorus plated and otherwise untreated copper iiange 18, together with a copper ange 19 similarly prepared or freshly bright-dipped or scratch-brushed. No such seal, as mentioned, was obtained by merely squeezing two freshly bright-dipped anges, or two flanges freshly scratch-brushed and bright-dipped respectively.
  • the present method may involve the use of nickel-phosphorus plating 17 either on the flanges of the slug 11 alone, with bright-dipping of the hat 14, as is preferred, or the use of such plating on the flanges of the slug 11 and of the hat 14, among other variations.
  • FIG- URE 4 designates a series of fabricating stations for the preparation of and work upon the copper slugs 11, while 24 designates a similar but simpler sequence of fabricating stations for the copper hats 14.
  • station 25 for machining slugs 11 and mounting certain connector parts thereon
  • station 26 for electroless nickel plating of the slugs
  • station 27 for mounting and preparing the transistors 12 on the plated slugs 11
  • scratch-brushing-station 28 for vacuum-baking the slugs and transistors.
  • the line 24 has a station 29 for bright-dipping hats 14-in lieu of scratch-brushing; and a station 30 for vacuum-baking the bright-dipped hats.
  • the two lines merge in a cold-working station 31. around the stations 26, 28, 29 and 30 that high precautions must be applied at those points.
  • a triple line frame around station 27 indicates the necessity of relatively extreme precautions for providing each slug 11, and particularly a pedestal 32 on its surface 16 (FIG- URE l), with a transistor 12 comprising a thin collector 33, a blank 34 of germanium or the like, and an emitter 35, so as to properly connect the emitter and collector, directly or indirectly, with lead wires 36 previously installed on the slug in station 25, and for finally preparing the transistor by certain cleaning operations and the like.
  • the transistor assembling, mounting and preparing station 27 must be operated under strict control; and this again, is best achieved by running station 27 as a batch-series operation, wherein a predetermined number of slugs 11, suitably mounted, are initially received and are then successively operated upon, under strictly controlled operating conditions as to atmosphere and the like. This results in the gradual production of a corresponding batch of semilinished slug and transistor combinations.
  • This latter batch according to the present method, can be transferred directly and readily into the vacuum-baking station 28, which may provide most effectively a plain batch operation.
  • said mounting elements are metallic slugs having surface grooves concentric with their anges, and wherein said cold-working displaces part of said metal portions into said grooves.
  • a method of hermetic, non-contaminating encapsulation of semiconductor devices and the like comprising the steps of plating annular flanges of metallic base elements for such devices with a phosphorus-containing metal; mounting said devices on such base members; brightdipping matching anges of housing elements formed of substantially pure copper, so as to expose the substantially pure copper of the latter flanges; and immediately thereupon joining plated flanges of base elements having said devices mounted thereon, to bright-dipped flanges of housing elements by compressing and thereby intermingling plated and bright-dipped metal portions of the respective flanges, at sufficiently low temperatures thereof to prevent evaporation of any portions and traces of such materials.
  • plating metal support means for said device including a ductile metal flange of said support means, with a corrosion-resistant, phosphorus-containing metal; mounting the device on the plated support means; disposing a ductile metal ange of a cover means opposite the plated support means; and then cold-working said flanges, without substantial extraneous application of heat, whereby ductile metal portions of said flanges are commingled and said phosphorus-containing metal substantially disappears into the commingled metal.
  • a metal-working method comprising: chemically lining at least one of a pair of solid surfaces of ductile metal members with a frangible coating of phosphoruscontaining metal and then applying pressure to said surfaces of said members without substantial extraneous application of heat.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Mechanical Engineering (AREA)
  • Chemically Coating (AREA)
  • Casings For Electric Apparatus (AREA)
US90587A 1956-11-07 1961-02-16 Method of making semiconductor units and the like Expired - Lifetime US3140530A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
BE562206D BE562206A (enrdf_load_stackoverflow) 1956-11-07
GB34716/57A GB869935A (en) 1956-11-07 1957-11-07 Improvements in and relating to the cold-working of metals
US90587A US3140530A (en) 1956-11-07 1961-02-16 Method of making semiconductor units and the like

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US62082256A 1956-11-07 1956-11-07
US90587A US3140530A (en) 1956-11-07 1961-02-16 Method of making semiconductor units and the like

Publications (1)

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US3140530A true US3140530A (en) 1964-07-14

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Application Number Title Priority Date Filing Date
US90587A Expired - Lifetime US3140530A (en) 1956-11-07 1961-02-16 Method of making semiconductor units and the like

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US (1) US3140530A (enrdf_load_stackoverflow)
BE (1) BE562206A (enrdf_load_stackoverflow)
GB (1) GB869935A (enrdf_load_stackoverflow)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3249683A (en) * 1963-12-19 1966-05-03 Texas Instruments Inc Transistor step-header
US5540378A (en) * 1993-09-27 1996-07-30 Olin Corporation Method for the assembly of an electronic package
WO2010017798A1 (de) * 2008-08-12 2010-02-18 Gsi Helmholtzzentrum Für Schwerionenforschung Gmbh Werkstückanordnung
US10319654B1 (en) * 2017-12-01 2019-06-11 Cubic Corporation Integrated chip scale packages

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
None *

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3249683A (en) * 1963-12-19 1966-05-03 Texas Instruments Inc Transistor step-header
US5540378A (en) * 1993-09-27 1996-07-30 Olin Corporation Method for the assembly of an electronic package
US5563442A (en) * 1993-09-27 1996-10-08 Olin Corporation Leadframe having exposed, solderable outer lead ends
WO2010017798A1 (de) * 2008-08-12 2010-02-18 Gsi Helmholtzzentrum Für Schwerionenforschung Gmbh Werkstückanordnung
US20110206940A1 (en) * 2008-08-12 2011-08-25 Gsi Helmholtzzentrum Für Schwerionenforschung Gmbh Workpiece arrangement
US9027823B2 (en) 2008-08-12 2015-05-12 Gsi Helmholtzzentrum Fuer Schwerionenforschung Gmbh Workpiece arrangement
US10319654B1 (en) * 2017-12-01 2019-06-11 Cubic Corporation Integrated chip scale packages
US10553511B2 (en) * 2017-12-01 2020-02-04 Cubic Corporation Integrated chip scale packages

Also Published As

Publication number Publication date
BE562206A (enrdf_load_stackoverflow)
GB869935A (en) 1961-06-07

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