US20220149244A1 - Pixel, display device including same, and manufacturing method therefor - Google Patents

Pixel, display device including same, and manufacturing method therefor Download PDF

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Publication number
US20220149244A1
US20220149244A1 US17/602,138 US202017602138A US2022149244A1 US 20220149244 A1 US20220149244 A1 US 20220149244A1 US 202017602138 A US202017602138 A US 202017602138A US 2022149244 A1 US2022149244 A1 US 2022149244A1
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electrode
sub
electrodes
light emitting
disposed
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Won Ho Lee
Jong Hyuk KANG
Hyun Deok Im
Hyun Min Cho
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Samsung Display Co Ltd
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Samsung Display Co Ltd
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Assigned to SAMSUNG DISPLAY CO., LTD. reassignment SAMSUNG DISPLAY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHO, HYUN MIN, IM, HYUN DEOK, KANG, JONG HYUK, LEE, WON HO
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/387—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body

Definitions

  • Embodiments relate to a pixel, a display device including the pixel, and a method of fabricating the display device.
  • a technique of manufacturing a subminiature light emitting element using a material having a reliable inorganic crystal structure and manufacturing a light emitting device using the light emitting element has been developed.
  • a technique of fabricating subminiature light emitting elements having a small size corresponding to a range from the nanometer scale to the micrometer scale, and forming light sources of various light emitting devices, for example, pixels of display devices using the subminiature light emitting elements has been developed.
  • this background of the technology section is, in part, intended to provide useful background for understanding the technology.
  • this background of the technology section may also include ideas, concepts, or recognitions that were not part of what was known or appreciated by those skilled in the pertinent art prior to a corresponding effective filing date of the subject matter disclosed herein.
  • An object of the disclosure is to provide a pixel including a light emitting element, a display device including the pixel, and a method of fabricating the display device.
  • a pixel may include electrode pairs successively disposed in a first direction, and each of the electrode pairs including a first sub-electrode and a second sub-electrode successively disposed in the first direction; light emitting elements, each of the light emitting elements being electrically connected between the first sub-electrode and the second sub-electrode of any one of the electrode pairs; a first connection electrode electrically connected between the first sub-electrode of a first electrode pair of the electrode pairs and a first power supply; and a second connection electrode electrically connected between the second sub-electrode of a last electrode pair of the electrode pairs and a second power supply.
  • the second sub-electrode of a remaining electrode pair other than the last electrode pair of the electrode pairs is spaced apart from the first sub-electrode of a subsequent electrode pair with at least one first sub-electrode or at least one second sub-electrode disposed therebetween, and is electrically connected to the first sub-electrode of the subsequent electrode pair.
  • respective first sub-electrodes and respective second sub-electrodes of two electrode pairs successively disposed among the electrode pairs may be disposed in opposite directions such that the respective first sub-electrodes of the two electrode pairs or the respective second sub-electrodes of the two electrode pairs are adjacent to each other.
  • a first sub-electrode and a second sub-electrode of each odd numbered electrode pair among the electrode pairs may be successively disposed in the first direction.
  • a first sub-electrode and a second sub-electrode of each even numbered electrode pair among the electrode pairs may be disposed in reverse order in the first direction.
  • each of the light emitting elements may include a first end electrically connected to the first sub-electrode of one of the electrode pairs; and a second end electrically connected to the second sub-electrode of one of the electrode pairs.
  • each of the light emitting elements may be a P-type end and an N-type end, respectively.
  • Each of the light emitting elements may be electrically connected in a forward direction between the first sub-electrode and the second sub-electrode of one of the electrode pairs.
  • the pixel may further include first contact electrodes respectively disposed on first sub-electrodes of the electrode pairs and electrically and respectively connecting each of the first sub-electrodes to a first end of an adjacent light emitting element; and second contact electrodes respectively disposed on second sub-electrodes of the electrode pairs and electrically and respectively connecting each of the respective second sub-electrodes to a second end of an adjacent light emitting element.
  • the second sub-electrode of the remaining electrode pair other than the last electrode pair may be electrically connected to the first sub-electrode of the subsequent electrode pair through a corresponding one of intermediate connection electrodes.
  • each intermediate connection electrode may integrally extend from one of the second sub-electrode of the remaining electrode pair and the first sub-electrode of the subsequent electrode pair.
  • the first contact electrode or the second contact electrode that is disposed on a remaining sub-electrode of the second sub-electrode of the remaining electrode pair and the first sub-electrode of the subsequent electrode pair may include a protrusion protruding in a second direction intersecting the first direction and may be electrically connected to the each intermediate connection electrode.
  • each of the first sub-electrode and the second sub-electrode of the electrode pairs may include a reflective electrode layer including a reflective conductive material.
  • Each of the first contact electrode and the second contact electrode may include a transparent electrode layer including a transparent conductive material.
  • the pixel may further include an emission area enclosed by an opaque bank and including the electrode pairs and the light emitting elements.
  • the first direction may be a longitudinal direction of the emission area.
  • the electrode pairs may include three or more electrode pairs.
  • the light emitting elements may be dispersed and disposed in three or more serial stages including the respective electrode pairs, and may be electrically connected to each other in a series-parallel combination structure.
  • the pixel may further include an emission area enclosed by an opaque bank and including the electrode pairs and the light emitting elements.
  • the first direction may be a transverse direction of the emission area.
  • the electrode pairs may include two or more electrode pairs each including first sub-electrodes and second sub-electrodes extending in a longitudinal direction of the emission area.
  • the pixel may further include at least one of a first dummy electrode electrically isolated and disposed adjacent to the first electrode pair; and a second dummy electrode electrically isolated and disposed adjacent to the last electrode pair.
  • the pixel may further include banks respectively disposed below at least one of the first sub-electrode and the second sub-electrode of the electrode pairs.
  • a part of the banks may be respectively disposed below two first sub-electrodes or two second sub-electrodes successively disposed in the first direction among the first sub-electrodes and second sub-electrodes of the electrode pairs such that the part of the banks overlap the two first sub-electrodes or the two second sub-electrodes.
  • the banks may be individually separated and disposed below each of the first sub-electrodes and the second sub-electrodes of the electrode pairs.
  • a display device in accordance with an embodiment may include a pixel disposed in a display area.
  • the pixel may include electrode pairs successively disposed in a first direction, and each of the electrode pairs including a first sub-electrode and a second sub-electrode successively disposed in the first direction; light emitting elements, each of the light emitting elements being electrically connected between the first sub-electrode and the second sub-electrode of any one of the electrode pairs; a first connection electrode electrically connected between the first sub-electrode of a first electrode pair of the electrode pairs and a first power supply; and a second connection electrode electrically connected between the second sub-electrode of a last electrode pair of the electrode pairs and a second power supply.
  • the second sub-electrode of a remaining electrode pair other than the last electrode pair of the electrode pairs may be spaced apart from the first sub-electrode of a subsequent electrode pair with at least one first sub-electrode or at least one second sub-electrode disposed therebetween, and may be electrically connected to the first sub-electrode of the subsequent electrode pair.
  • a method of fabricating a display device in accordance with an embodiment may include forming, in an emission area of each pixel, electrode pairs each of the electrode pairs including a pair of a first sub-electrode and a second sub-electrode and successively disposed in a first direction, and a first alignment line and a second alignment line respectively electrically connected to the first sub-electrodes and the second sub-electrodes of the electrode pairs; supplying light emitting elements to the emission area, and applying alignment signals to the first alignment line and the second alignment line to align the light emitting elements; individually separating the first sub-electrodes and the second sub-electrodes of the electrode pairs; and re-connecting the first sub-electrodes and the second sub-electrodes of the electrode pairs such that the aligned light emitting elements are electrically connected in a forward direction between the first sub-electrodes and the second sub-electrodes of the electrode pairs.
  • the forming of the electrode pairs may include forming a double electrode pattern by successively disposing a first sub-electrode or a second sub-electrode of each of successive electrode pairs of the electrode pairs and forming the first sub-electrode or the second sub-electrodes of each of the successive electrode pairs to be integral with each other.
  • the individually separating of the first sub-electrodes and the second sub-electrodes of the electrode pairs may include separating the double electrode pattern into respective first sub-electrodes or respective second sub-electrodes.
  • a display device including the pixel, and a method of fabricating the display device, a light source unit may be formed efficiently using light emitting elements supplied to an emission area of each pixel, and the light emitting elements may be more uniformly arranged or disposed between electrode pairs of the light source unit. Consequently, the emission efficiency and the luminance of each pixel may be enhanced, and a failure rate may be reduced.
  • FIGS. 1A and 1B are respectively a schematic perspective view and a schematic cross-sectional view illustrating a light emitting element in accordance with an embodiment.
  • FIGS. 2A and 2B are respectively a schematic perspective view and a schematic cross-sectional view illustrating a light emitting element in accordance with an embodiment.
  • FIGS. 3A and 3B are respectively a schematic perspective view and a schematic cross-sectional view illustrating a light emitting element in accordance with an embodiment.
  • FIG. 4 is a schematic plan view illustrating a display device in accordance with an embodiment.
  • FIGS. 5A to 5G are schematic diagrams of an equivalent circuit each illustrating a pixel in accordance with an embodiment.
  • FIGS. 6A and 6B are schematic diagrams of an equivalent circuit each illustrating a pixel in accordance with an embodiment, and for example illustrate different embodiments of a pixel in which open failures have occurred due to different reasons.
  • FIG. 7 is a schematic plan view illustrating a pixel in accordance with an embodiment.
  • FIGS. 8 to 11 are schematic plan views each illustrating a pixel in accordance with an embodiment, and for example illustrate different modified embodiments of the pixel of FIG. 7 .
  • FIGS. 12A to 12D are schematic cross-sectional views each illustrating a pixel in accordance with an embodiment, and for example illustrate different embodiments of a cross-section of the pixel corresponding to line I-I′ of FIG. 11 .
  • FIG. 13 is a schematic cross-sectional view illustrating a pixel in accordance with an embodiment and for example illustrates an embodiment of a cross-section of the pixel corresponding to line II-II′ of FIG. 11 .
  • FIGS. 14 to 15 are schematic plan views each illustrating a pixel in accordance with an embodiment, and for example illustrate different modified embodiments of the pixel of FIG. 7 .
  • FIGS. 16A to 16D are schematic plan views sequentially illustrating a method of fabricating a display device in accordance with an embodiment and for example illustrate an embodiment of a method of fabricating a display device including the pixel of FIG. 11 .
  • the phrase “at least one of” is intended to include the meaning of “at least one selected from the group of” for the purpose of its meaning and interpretation.
  • “at least one of A and B” may be understood to mean “A, B, or A and B.”
  • first”, “second”, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the disclosure.
  • spatially relative terms “below”, “beneath”, “lower”, “above”, “upper”, or the like, may be used herein for ease of description to describe the relations between one element or component and another element or component as illustrated in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation depicted in the drawings. For example, in the case where a device illustrated in the drawing is turned over, the device positioned “below” or “beneath” another device may be placed “above” another device. Accordingly, the illustrative term “below” may include both the lower and upper positions. The device may also be oriented in other directions and thus the spatially relative terms may be interpreted differently depending on the orientations.
  • overlap or “overlapped” mean that a first object may be above or below or to a side of a second object, and vice versa. Additionally, the term “overlap” may include layer, stack, face or facing, extending over, covering, or partly covering or any other suitable term as would be appreciated and understood by those of ordinary skill in the art.
  • face and “facing” mean that a first element may directly or indirectly oppose a second element. Ina case in which a third element intervenes between the first and second element, the first and second element may be understood as being indirectly opposed to one another, although still facing each other.
  • first component or part may be not only directly on the second component or part but a third component or other components or part or parts may also intervene between them.
  • position used in the following description are defined in relative terms, and it should be noted that they may be changed into a reverse position or direction depending on a view angle or direction.
  • a singular form may include a plural form as well.
  • “About” or “approximately” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ⁇ 30%, 20%, 10%, 5% of the stated value.
  • FIGS. 1A, 1B, 2A, 2B, 3A, and 3B are schematic perspective views and schematic cross-sectional views each illustrating a light emitting element LD in accordance with an embodiment.
  • FIGS. 1A to 3B illustrate substantially cylindrical rod-type light emitting elements LD, the type and/or shape of the light emitting elements LD in accordance with the disclosure is not limited thereto.
  • a light emitting element LD in accordance with an embodiment may include a first conductivity type semiconductor layer 11 (also referred to as “first semiconductor layer”), a second conductivity type semiconductor layer 13 (also referred to as “second semiconductor layer”), and an active layer 12 interposed between the first and second conductivity type semiconductor layers 11 and 13 .
  • the light emitting element LD may include the first conductivity type semiconductor layer 11 , the active layer 12 , and the second conductivity type semiconductor layer 13 which may be successively stacked each other in a longitudinal direction.
  • the light emitting element LD may be provided in the form of a rod extending in one direction. If the direction in which the light emitting element LD extends is defined as a longitudinal direction, the light emitting element LD may have a first end and a second end with respect to the longitudinal direction.
  • one of the first and second conductivity type semiconductor layers 11 and 13 may be disposed on the first end of the light emitting element LD.
  • the other one of the first and second conductivity type semiconductor layers 11 and 13 may be disposed on the second end of the light emitting element LD.
  • the light emitting element LD may be a rod-type light emitting diode fabricated in the form of a rod on a wafer substrate by an etching scheme or the like, but the disclosure is not limited thereto.
  • the term “rod-type” embraces a rod-like shape and a bar-like shape such as a substantially cylindrical shape and a substantially prismatic shape extending in a longitudinal direction (for example, having an aspect ratio greater than 1), and the cross-sectional shape thereof is not limited to a particular shape.
  • the length L of the light emitting element LD may be greater than a diameter D thereof (or a width of the cross-section thereof).
  • the light emitting element LD may have a small size ranging from the nanometer scale to the micrometer scale.
  • each light emitting element LD may have a diameter D and/or a length L ranging from the nanometer scale to the micrometer scale.
  • the size of the light emitting element LD is not limited thereto.
  • the size of the light emitting element LD may be changed in various ways depending on design conditions of various devices, for example, a display device, which employs, as a light source, a light emitting device using a light emitting element LD.
  • the first conductivity type semiconductor layer 11 may include, for example, at least one N-type semiconductor layer.
  • the first conductivity type semiconductor layer 11 may include an N-type semiconductor layer which may include any one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and is doped with a first conductive dopant such as Si, Ge, or Sn.
  • a first conductive dopant such as Si, Ge, or Sn.
  • the material for forming the first conductivity type semiconductor layer 11 is not limited to this, and the first conductivity type semiconductor layer 11 may be formed of various other materials.
  • the active layer 12 may be disposed on the first conductivity type semiconductor layer 11 and have a single or multi-quantum well (MQW) structure.
  • a cladding layer (not shown) doped with a conductive dopant may be formed over and/or under or below the active layer 12 .
  • the cladding layer may be formed of an AlGaN layer or an InAlGaN layer.
  • a material such as AlGaN or AlInGaN may be used to form the active layer 12 , and various other materials may be used to form the active layer 12 .
  • the light emitting element LD may emit light by combination of electron-hole pairs in the active layer 12 . Since light emission of the light emitting element LD can be controlled based on the foregoing principle, the light emitting element LD may be used as a light source of various light emitting devices as well as a pixel of the display device.
  • the second conductivity type semiconductor layer 13 may be disposed on the active layer 12 and include a semiconductor layer having a type different from that of the first conductivity type semiconductor layer 11 .
  • the second conductivity type semiconductor layer 13 may include at least one P-type semiconductor layer.
  • the second conductivity type semiconductor layer 13 may include a P-type semiconductor layer which may include any one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and is doped with a second conductive dopant such as Mg.
  • the material for forming the second conductivity type semiconductor layer 13 is not limited to this, and the second conductivity type semiconductor layer 13 may be formed of various other materials.
  • the light emitting element LD may further include an insulating film INF provided or disposed at the surface of the light emitting element LD.
  • the insulating film INF may be formed at the surface of the light emitting element LD to enclose an outer circumferential surface of at least the active layer 12 , and may further enclose areas of the first and second conductivity type semiconductor layers 11 and 13 .
  • the insulating film INF may allow the opposite ends of the light emitting element LD that have different polarities to be exposed to the outside.
  • the insulating film INF may expose one end or an end of each of the first and second conductivity type semiconductor layers 11 and 13 that are disposed at the respective opposite ends of the light emitting element LD with respect to the longitudinal direction, for example, may expose two base sides of the cylinder (in FIGS. 1A and 1B , the top and bottom surfaces of the light emitting element LD) rather than covering or overlapping the two base sides.
  • the insulating film INF may include at least one insulating material of silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), aluminum oxide (Al 2 O 3 ), and titanium dioxide (TiO 2 ), but it is not limited thereto.
  • the material that forms the insulating film INF is not limited to a particular material, and the insulating film INF may be formed of various insulating materials.
  • the light emitting element LD may further include additional other components as well as the first conductivity type semiconductor layer 11 , the active layer 12 , the second conductivity type semiconductor layer 13 , and/or the insulating film INF.
  • the light emitting element LD may further include one or more fluorescent layers, one or more active layers, one or more semiconductor layers, and/or one or more electrode layers disposed on one end or an end of the first conductivity type semiconductor layer 11 , the active layer 12 , and/or the second conductivity type semiconductor layer 13 .
  • the light emitting element LD may further include at least one electrode layer 14 disposed on one end or an end of the second conductivity type semiconductor layer 13 .
  • the light emitting element LD may further include at least one electrode layer 15 disposed on one end or an end of the first conductivity type semiconductor layer 11 .
  • Each of the electrode layers 14 and 15 may be an ohmic contact electrode, but it is not limited thereto.
  • Each of the electrode layers 14 and 15 may include metal or metal oxide.
  • each of the electrode layers 14 and 15 may be formed of chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), oxides or alloys thereof, and/or transparent electrode materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO) alone or in combination.
  • the electrode layers 14 and 15 may be substantially transparent or translucent. Thereby, light generated from the light emitting element LD may be emitted to the outside after passing through the electrode layers 14 and 15 .
  • the insulating film INF may at least partially enclose the outer circumferential surfaces of the electrode layers 14 and 15 , or may not enclose the outer circumferential surfaces. In other words, the insulating film INF may be selectively formed on the surfaces of the electrode layers 14 and 15 . Furthermore, the insulating film INF may be formed to expose the opposite ends of the light emitting element LD that have different polarities, for example, may expose at least an area of each of the electrode layers 14 and 15 . As an example, in an embodiment, the insulating film INF may not be provided.
  • the active layer 12 may be prevented from short-circuiting with at least one electrode which is not shown (for example, at least one contact electrode of contact electrodes connected to the opposite ends of the light emitting element LD), etc., within the spirit and the scope of the disclosure. Consequently, the electrical stability of the light emitting element LD may be secured.
  • the term “connecting (or connection)” may comprehensively refer to physical and/or electrical connecting (or connection).
  • the term “connecting (or connection)” may comprehensively refer to direct and/or indirect connecting (or connection) and integral or non-integral connecting (or connection).
  • the insulating film INF at the surface of the light emitting element LD, occurrence of a defect on the surface of the light emitting element LD may be minimized, whereby the lifetime and efficiency of the light emitting element LD may be improved.
  • the insulating film INF is formed at the surface of each light emitting element LD, even in case that light emitting elements LD are disposed adjacent to each other, the light emitting elements LD may be prevented from undesirably short-circuiting.
  • a surface treatment process may be performed to fabricate the light emitting element LD.
  • each light emitting element LD may be surface-treated so that, in case that light emitting elements LD are mixed with a fluidic solution (or solvent) and supplied to each emission area (for example, an emission area of each pixel), the light emitting elements LD can be evenly dispersed rather than unevenly aggregating in the solution.
  • the insulating film INF itself may be formed of a hydrophobic film using hydrophobic material, or an additional hydrophobic film formed of the hydrophobic material may be formed on the insulating film INF.
  • the hydrophobic material may be a material containing fluorine to exhibit hydrophobicity.
  • the hydrophobic material may be applied to the light emitting elements LD in the form of a self-assembled monolayer (SAM).
  • SAM self-assembled monolayer
  • the hydrophobic material may include octadecyl trichlorosilane, fluoroalkyl trichlorosilane, perfluoroalkyl triethoxysilane, etc., within the spirit and the scope of the disclosure.
  • the hydrophobic material may be a commercially available fluorine containing material such as TeflonTM or CytopTM, or a corresponding material.
  • a light emitting device including the light emitting element LD described above may be used not only in a display device but also in various devices which requires a light source.
  • at least one subminiature light emitting element LD for example, subminiature light emitting elements LD each having a size ranging from the nanometer scale to the micrometer scale, may be disposed in each pixel of the display panel to form a light source (or, a light source unit) of the corresponding pixel using the subminiature light emitting elements LD.
  • the field of application of the light emitting element LD according to the disclosure is not limited to a display device.
  • the light emitting element LD may also be used in other types of devices such as a lighting device, which requires a light source.
  • FIG. 4 is a schematic plan view illustrating a display device in accordance with an embodiment.
  • FIG. 4 illustrates a display device, for example, a display panel PNL provided in the display device, as an example of a device which may use, as a light source, the light emitting element LD described with reference to FIGS. 1A to 3B .
  • each of the pixels PXL of the display panel PNL may have at least one light emitting element LD.
  • FIG. 4 simply illustrates the structure of the display panel PNL in accordance with an embodiment, focused on a display area DA.
  • at least one driving circuit for example, at least one of a scan driver and a data driver
  • lines may be further provided in the display panel PNL.
  • the display panel PNL in accordance with an embodiment may include abase layer BSL, and pixels PXL disposed on the base layer BSL.
  • the display panel PNL and the base layer BSL for forming the display panel PNL may include a display area DA for displaying an image, and a non-display area NDA formed in an area other than the display area DA.
  • the pixels PXL may be disposed in the display area DA on the base layer BSL.
  • the display area DA may be disposed in a central area of the display panel PNL, and the non-display area NDA may be disposed in a peripheral area of the display panel PNL in such away as to enclose the display area DA.
  • the locations of the display area DA and the non-display area NDA are not limited to this, and the locations thereof may be changed.
  • the display area DA may form a screen in which an image is displayed.
  • the base layer BSL may form abase of the display panel PNL.
  • the base layer BSL may be a rigid or flexible substrate or film, and the material or properties thereof are not particularly limited.
  • the base layer BSL may be a rigid substrate made of glass or reinforced glass, a flexible substrate (or a thin film) formed of plastic or metal, or at least one insulating layer, and the material and/or properties thereof are not particularly limited.
  • the base layer BSL may be transparent, but the disclosure is not limited thereto.
  • the base layer BSL may be a transparent, translucent, opaque, or reflective base.
  • An area of the base layer BSL may be defined as the display area DA in which the pixels PXL are disposed, and the other area thereof may be defined as the non-display area NDA.
  • the base layer BSL may include the display area DA including pixel areas in which the respective pixels PXL are formed, and the non-display area NDA disposed around the display area DA.
  • Various lines and/or internal circuits which are connected to the pixels PXL of the display area DA may be disposed in the non-display area NDA.
  • the pixels PXL may be disposed in each pixel area of the display area DA. In an embodiment, the pixels PXL may be arranged or disposed in the display area DA in a stripe or PenTile® arrangement manner, but the disclosure is not limited thereto. For example, the pixels PXL may be arranged or disposed in the display area DA in various arrangement manners.
  • Each pixel PXL may include at least one light source which is driven by a control signal (for example, a scan signal and a data signal) and/or a power supply (for example, a first power supply and a second power supply).
  • each of the pixels PXL may include a light emitting element LD in accordance with any one of embodiments of FIGS. 1A to 3B , for example, at least one subminiature rod-type light emitting element LD having a small size corresponding to the nanometer scale or the micrometer scale.
  • the type of the light emitting element LD which may be used as a light source of the pixel PXL is not limited thereto.
  • each pixel PXL may include a light emitting element that has a core-shell structure and is fabricated by a growth method.
  • the light emitting element having the core-shell structure may be a subminiature core-shell light emitting element having a small size corresponding to the nanometer scale to the micrometer scale, but the size of the light emitting element having the core-shell structure is not limited thereto.
  • each pixel PXL may be formed of an active pixel.
  • the types, structures, and/or driving schemes of the pixels PXL capable of being applied to the display device according to the disclosure are not particularly limited.
  • each pixel PXL may be formed of a pixel for passive or active display devices which have various structures and/or may be operated in various driving schemes.
  • FIGS. 5A to 5G are schematic diagrams of an equivalent circuit each illustrating a pixel PXL in accordance with an embodiment.
  • FIGS. 5A to 5G illustrate different embodiments of the pixel PXL which can be applied to an active display device.
  • the types of pixels PXL and display devices to which embodiments may be applied are not limited thereto.
  • each pixel PXL illustrated in FIGS. 5A to 5G may be any one of the pixels PXL provided in the display panel PNL of FIG. 4 .
  • the pixels PXL may have substantially the same or similar structure.
  • the pixel PXL in accordance with an embodiment may include a light source unit LSU that generates light having a luminance corresponding to a data signal.
  • the pixel PXL may selectively further include a pixel circuit PXC that drives the light source unit LSU.
  • the light source unit LSU may include light emitting elements LD, and a first electrode ET 1 and a second electrode ET 2 which electrically connect the light emitting elements LD between a first power supply VDD (or first power source) and a second power supply VSS (or second power source).
  • the light source unit LSU may include a first electrode ET 1 connected to the first power supply VDD, a second electrode ET 2 connected to the second power supply VSS, and light emitting elements LD connected in parallel to each other in an identical direction between the first and second electrodes ET 1 and ET 2 .
  • the first electrode ET 1 may be an anode electrode
  • the second electrode ET 2 may be a cathode electrode.
  • each of the light emitting elements LD may include a P-type end connected to the first power supply VDD through at least the first electrode ET 1 , and an N-type end connected to the second power supply VSS through at least the second electrode ET 2 .
  • the first and second power supplies VDD and VSS may have different potentials to make it possible for the light emitting elements LD to emit light.
  • the first power supply VDD may be set as a high-potential power supply
  • the second power supply VSS may be set as a low-potential power supply.
  • a difference in potential between voltages of the first and second power supplies VDD and VSS may be set to a threshold voltage of the light emitting elements LD or more during at least an emission period of the pixel PXL.
  • the light emitting elements LD may be connected in parallel between the first and second power supplies VDD and VSS in a forward direction through the first and second electrodes ET 1 and ET 2 .
  • each of the light emitting elements LD connected in a forward direction between the first and second power supplies VDD and VSS may form a valid light source.
  • a group of valid light sources may form the light source unit LSU of the pixel PXL.
  • each pixel PXL may further include a pixel circuit PXC electrically connected between the first or second power supply VDD or VSS and the light source unit LSU.
  • the first ends (for example, the P-type ends) of the light emitting elements LD that form each light source unit LSU may be connected in common to the pixel circuit PXC through the first electrode ET 1 (also referred to as “first pixel electrode”) of the light source unit LSU, and be electrically connected to the first power supply VDD through the pixel circuit PXC and the first power line PL 1 .
  • the second ends (for example, the N-type ends) of the light emitting elements LD may be connected in common to the second electrode ET 2 (also referred to as “second pixel electrode”) of the light source unit LSU and be electrically connected to the second power supply VSS through the second electrode ET 2 of the light source unit LSU and the second power line PL 2 .
  • the light emitting elements LD may emit light having a luminance corresponding to driving current supplied thereto through the corresponding pixel circuit PXC.
  • the pixel circuit PXC may supply, to the light source unit LSU, driving current corresponding to a gray scale value of data of the corresponding frame.
  • the driving current supplied to the light source unit LSU may be divided into parts that flow to the light emitting elements LD connected in the forward direction.
  • each of the light emitting elements LD may emit light having a luminance corresponding to current applied thereto, so that the light source unit LSU may emit light having a luminance corresponding to the driving current.
  • the light source unit LSU may further include at least one invalid light source, as well as including the light emitting elements LD that form each valid light source.
  • at least one reverse light emitting element LDrv may be further connected between the first and second electrodes ET 1 and ET 2 of the light source unit LSU.
  • Each reverse light emitting element LDrv along with the light emitting elements LD that form the valid light sources, may be connected in parallel to each other between the first and second electrodes ET 1 and ET 2 , and may be connected between the first and second electrodes ET 1 and ET 2 in a direction opposite to that of the light emitting elements LD.
  • the N-type end of the reverse light emitting element LDrv may be connected to the first power supply VDD via the first electrode ET 1 .
  • the P-type end of the reverse light emitting element LDrv may be connected to the second power supply VSS via the second electrode ET 2 .
  • the light emitting elements LD supplied to each pixel area may be controlled to be aligned and biased in any one direction (for example, the forward direction) by adjusting alignment signals (or alignment voltages) to be applied to the first and second electrodes ET 1 and ET 2 or forming a magnetic field.
  • the light emitting elements LD may be aligned to be biased such that the number of light emitting elements LD connected in the forward direction between the first and second electrodes ET 1 and ET 2 of each pixel PXL is increased by controlling alignment signals (or alignment voltages) to be applied to the first and second electrodes ET 1 and ET 2 or forming a magnetic field. All of the light emitting elements LD may be connected in the forward direction between the first and second electrodes ET 1 and ET 2 , or the number of light emitting elements LD connected in the forward direction between the first and second electrodes ET 1 and ET 2 may be greater than the number of at least one reverse light emitting elements LDrv.
  • approximately 70% (for example, 80% or more) of the light emitting elements connected between the first and second electrodes ET 1 and ET 2 may be light emitting elements LD connected in the forward direction.
  • the pixel circuit PXC may be connected to a scan line Si and a data line Dj of the corresponding pixel PXL.
  • the pixel circuit PXC of the pixel PXL may be connected to an i-th scan line Si and a j-th data line Dj of the display area DA.
  • the pixel circuit PXC may include first and second transistors T 1 and T 2 , and a storage capacitor Cst.
  • the first transistor T 1 (also referred to as “driving transistor”) may be connected between the first power supply VDD and the light source unit LSU.
  • a gate electrode of the first transistor T 1 may be connected to a first node N 1 .
  • the first transistor T 1 may control driving current to be supplied to the light source unit LSU in response to the voltage of the first node N 1 .
  • the second transistor T 2 (also referred to as “switching transistor”) may be connected between the data line Dj and the first node N 1 .
  • a gate electrode of the second transistor T 2 may be connected to the scan line Si.
  • a scan signal having a gate-on voltage for example, a low-level voltage
  • the second transistor T 2 is turned on to electrically connect the first node N 1 to the data line Dj.
  • a data signal of a corresponding frame is supplied to the data line Dj.
  • the data signal is transmitted to the first node N 1 via the second transistor T 2 . Thereby, a voltage corresponding to the data signal is charged to the storage capacitor Cst.
  • One electrode of the storage capacitor Cst may be connected to the first power supply VDD, and the other electrode thereof may be connected to the first node N 1 .
  • the storage capacitor Cst may charge a voltage corresponding to a data signal to be supplied to the first node N 1 during each frame period.
  • the transistors, for example, the first and second transistors T 1 and T 2 , included in the pixel circuit PXC have been illustrated as being formed of P-type transistors, the disclosure is not limited to this. In other words, at least one of the first and second transistors T 1 and T 2 may be changed to an N-type transistor.
  • both the first and second transistors T 1 and T 2 may be formed of N-type transistors.
  • the gate-on voltage of the scan signal for writing the data signal supplied to the data line Dj in each frame period to the pixel PXL may be a high level voltage.
  • the voltage of the data signal for turning on the first transistor T 1 may be a voltage having a level opposite to that of an embodiment of FIG. 5A .
  • a data signal having a higher voltage may be supplied.
  • the pixel PXL shown in FIG. 5B is substantially similar in configuration and operation to the pixel PXL of FIG. 5A , except that the connection positions of some or a part of circuit elements and the voltage levels of control signals (for example, a scan signal and a data signal) are changed depending on a change in type of the transistor. Therefore, detailed description of the pixel PXL of FIG. 5B will be omitted.
  • the structure of the pixel circuit PXC is not limited to embodiments shown in FIGS. 5A and 5B .
  • the pixel circuit PXC may be formed of a pixel circuit which may have various structures and/or be operated by various driving schemes.
  • the pixel circuit PXC may be formed in the same manner as that of an embodiment illustrated in FIG. 5C .
  • the pixel circuit PXC may be connected not only to a scan line Si of a corresponding horizontal line but also to at least one another scan line (or a control line).
  • the pixel circuit PXC of the pixel PXL disposed at the i-th row of the display area DA may be further connected to an i ⁇ 1-th scan line Si ⁇ 1 and/or an i+i-th scan line Si+1.
  • the pixel circuit PXC may be connected not only to the first and second power supplies VDD and VSS but also to another power supply (or another power source).
  • the pixel circuit PXC may also be connected to an initialization power supply Vint (or initialization power source).
  • the pixel circuit PXC may include first to seventh transistors T 1 to T 7 and a storage capacitor Cst.
  • the first transistor T 1 may be connected between the first power supply VDD and the light source unit LSU.
  • a first electrode (for example, a source electrode) of the first transistor T 1 may be connected to the first power supply VDD through the fifth transistor T 5 and the first power line PL 1
  • a second electrode (for example, a drain electrode) of the first transistor T 1 may be connected via the sixth transistor T 6 to the first electrode of the light source unit LSU (for example, the first pixel electrode and/or the first contact electrode of the corresponding pixel PXL).
  • a gate electrode of the first transistor T 1 may be connected to a first node N 1 .
  • the first transistor T 1 may control driving current to be supplied to the light source unit LSU in response to the voltage of the first node N 1 .
  • the second transistor T 2 may be connected between the data line Dj and the first electrode of the first transistor T 1 .
  • a gate electrode of the second transistor T 2 may be connected to the corresponding scan line Si.
  • the second transistor T 2 may be turned on to electrically connect the data line Dj to the first electrode of the first transistor T 1 .
  • a data signal supplied from the data line Dj may be transmitted to the first transistor T 1 .
  • the third transistor T 3 may be connected between the second electrode of the first transistor T 1 and the first node N 1 .
  • a gate electrode of the third transistor T 3 may be connected to the corresponding scan line Si. In case that a scan signal having a gate-on voltage is supplied from the scan line Si, the third transistor T 3 may be turned on to connect the first transistor T 1 in the form of a diode.
  • the fourth transistor T 4 may be connected between the first node N 1 and the initialization power supply Vint.
  • a gate electrode of the fourth transistor T 4 may be connected to a preceding scan line, for example, an i ⁇ 1-th scan line Si ⁇ 1.
  • the fourth transistor T 4 may be turned on so that the voltage of the initialization power supply Vint may be transmitted to the first node N 1 .
  • the voltage of the initialization power supply Vint for initializing the gate voltage of the first transistor T 1 may be the lowest voltage of the data signal or less.
  • the fifth transistor T 5 may be connected between the first power supply VDD and the first transistor T 1 .
  • a gate electrode of the fifth transistor T 5 may be connected to a corresponding emission control line, for example, an i-th emission control line Ei.
  • the fifth transistor T 5 may be turned off in case that an emission control signal having a gate-off voltage (for example, a high level voltage) is supplied to the emission control line Ei, and may be turned on in other cases.
  • the sixth transistor T 6 may be connected between the first transistor T 1 and the light source unit LSU. Agate electrode of the sixth transistor T 6 may be connected to a corresponding emission control line, for example, the i-th emission control line Ei. The sixth transistor T 6 may be turned off in case that an emission control signal having a gate-off voltage is supplied to the emission control line Ei, and may be turned on in other cases.
  • the seventh transistor T 7 may be connected between a second node N 2 to which the sixth transistor T 6 and the first electrode of the light source unit LSU (for example, the first pixel electrode ET 1 of the corresponding pixel PXL) are connected and the initialization power supply Vint.
  • a gate electrode of the seventh transistor T 7 may be connected to any one of scan lines of a subsequent stage (a subsequent horizontal pixel column), for example, to the i+1-th scan line Si+1. In case that a scan signal of a gate-on voltage is supplied to the i+1-th scan line Si+1, the seventh transistor T 7 may be turned on so that the voltage of the initialization power supply Vint may be supplied to the first electrode of the light source unit LSU.
  • the voltage of the first electrode of the light source unit LSU may be initialized.
  • the control signal for controlling the operation of the seventh transistor T 7 may be changed in various ways.
  • the gate electrode of the seventh transistor T 7 may be connected to a scan line of a corresponding horizontal line, for example, an i-th scan line Si.
  • the seventh transistor T 7 may be turned on so that the voltage of the initialization power supply Vint may be supplied to the first electrode of the light source unit LSU.
  • the storage capacitor Cst may be connected between the first power supply VDD and the first node N 1 .
  • the storage capacitor Cst may store a voltage corresponding both to the data signal applied to the first node N 1 during each frame period and to the threshold voltage of the first transistor T 1 .
  • the transistors, for example, the first to seventh transistors T 1 to T 7 , included in the pixel circuit PXC have been illustrated as being formed of P-type transistors, the disclosure is not limited thereto.
  • at least one of the first to seventh transistors T 1 to T 7 may be changed to an N-type transistor.
  • FIGS. 5A to 5C illustrate embodiments in which all valid light sources, for example, light emitting elements LD, constituting each light source unit LSU are connected in parallel to each other
  • the disclosure is not limited thereto.
  • the light source unit LSU of each pixel PXL may include serial stages which are successively connected to each other.
  • components for example, the pixel circuit PXC
  • the light source unit LSU may include light emitting elements connected in series to each other.
  • the light source unit LSU may include first, second, and third light emitting elements LD 1 , LD 2 , and LD 3 which are connected in series in a forward direction between the first power supply VDD and the second power supply VSS and constitute each valid light source.
  • first, second, and third light emitting elements LD 1 , LD 2 , and LD 3 which are connected in series in a forward direction between the first power supply VDD and the second power supply VSS and constitute each valid light source.
  • the corresponding light emitting element will be referred to as a first light emitting element LD 1 , a second light emitting element LD 2 , or a third light emitting element LD 3 .
  • light emitting element LD or “light emitting elements LD” will be used to arbitrarily designate at least one light emitting element of the first, second, and the third light emitting elements LD 1 , LD 2 , and LD 3 or collectively designate the first, second, and third light emitting elements LD 1 , LD 2 , and LD 3 .
  • a P-type end of the first light emitting element LD 1 may be connected to the first power supply VDD through the first electrode ET 1 of the light source unit LSU, etc., within the spirit and the scope of the disclosure.
  • An N-type end of the first light emitting element LD 1 may be connected to a P-type end of the second light emitting element LD 2 through a 1-2-th intermediate electrode IET 1 - 2 connected between first and second serial stages.
  • the P-type end of the second light emitting element LD 2 may be connected to the N-type end of the first light emitting element LD 1 .
  • An N-type end of the second light emitting element LD 2 may be connected to a P-type end of the third light emitting element LD 3 through a 2-3-th intermediate electrode IET 2 - 3 connected between the second and third serial stages.
  • the P-type end of the third light emitting element LD 3 may be connected to the N-type end of the second light emitting element LD 2 .
  • An N-type end of the third light emitting element LD 3 may be connected to the second power supply VSS through the second electrode ET 2 of the light source unit LSU and the second power line PL 2 .
  • the first, second, and the third light emitting elements LD 1 , LD 2 , and LD 3 may be connected in series between the first and second electrodes ET 1 and ET 2 of the light source unit LSU.
  • FIG. 5D illustrates an embodiment where the light emitting elements LD are connected to have a three-stage serial structure
  • the disclosure is not limited thereto.
  • two light emitting elements LD may be connected to have a two-stage serial structure, or four or more light emitting elements LD may be connected to have a four- or more-stage serial structure.
  • the voltage to be applied between the first and second electrodes ET 1 and ET 2 may be increased, and the amount of driving current flowing to the light source unit LSU may be reduced, compared to a light source unit LSU having a structure in which light emitting elements LD are connected in parallel. Therefore, in the case where the light source unit LSU of each pixel PXL is formed of a serial structure, panel current flowing through the display panel PNL may be reduced as the display device is driven. Hence, power consumption may be reduced.
  • At least one serial stage may include light emitting elements LD connected in parallel to each other.
  • the light source unit LSU may be formed of a serial/parallel combination structure (or series-parallel combination structure).
  • the light source unit LSU may be as illustrated in FIGS. 5E to 5G .
  • FIGS. 5E to 5G there is illustrated only the light emitting elements LD connected between the first and second power supplies VDD and VSS in the forward direction to form valid light sources of the light source unit LSU, the disclosure is not limited thereto.
  • each pixel PXL illustrated in FIG. 5E to 5G may further include one or more reverse light emitting element LDrv described in the foregoing embodiments.
  • the number of reverse light emitting elements LDrv may be less than the number of valid light sources, for example, light emitting elements LD, disposed in the pixel PXL in the forward direction.
  • FIGS. 5E to 5G a structure of the light source unit LSU in accordance with an embodiment of FIGS. 5E to 5G will be described, focused on light emitting elements LD that form the valid light sources of the light source unit LSU.
  • the light source unit LSU may include serial stages successively connected between the first and second power supplies VDD and VSS.
  • Each of the serial stages may include one or more light emitting elements LD which are connected in the forward direction between first and second sub-electrodes that form an electrode pair of the corresponding serial stage.
  • the light source unit LSU may include first to third serial stages successively connected between the first and second power supplies VDD and VSS.
  • Each of the first to third serial stages may include first and second sub-electrodes SET 1 [ 1 ] and SET 2 [ 1 ], SET 1 [ 2 ] and SET 2 [ 2 ], or SET 1 [ 3 ] and SET 2 [ 3 ], and one or more light emitting elements LD connected in the forward between the first and second sub-electrodes SET 1 [ 1 ] and SET 2 [ 1 ], SET 1 [ 2 ] and SET 2 [ 2 ], or SET 1 [ 3 ] and SET 2 [ 3 ].
  • a first sub-electrode of a first electrode pair (for example, the first sub-electrode SET 1 [ 1 ] of the first serial stage) may be an anode electrode of the light source unit LSU.
  • a second sub-electrode of a last electrode pair (for example, the second sub-electrode SET 2 [ 3 ] of the third serial stage) may be a cathode electrode of the light source unit LSU.
  • the first serial stage (also referred to as “first stage”) may include a pair of first and second sub-electrodes SET 1 [ 1 ] and SET 2 [ 1 ], and one or more first light emitting elements LD 1 electrically connected between the pair of first and second sub-electrodes SET 1 [ 1 ] and SET 2 [ 1 ].
  • the first serial stage may include a first sub-electrode SET 1 [ 1 ] connected to the first power supply VDD via the pixel circuit PXC, a second sub-electrode SET 2 [ 1 ] which forms, along with the first sub-electrode SET 1 [ 1 ], an electrode pair of the first serial stage and may be connected to the second power supply VSS, and first light emitting elements LD 1 which are electrically connected between the first and second sub-electrodes SET 1 [ 1 ] and SET 2 [ 1 ].
  • a P-type end of each of the first light emitting elements LD 1 may be electrically connected to the first sub-electrode SET 1 [ 1 ] of the first serial stage, and an N-type end of each of the first light emitting elements LD 1 may be electrically connected to the second sub-electrode SET 2 [ 1 ] of the first serial stage.
  • the first light emitting elements LD 1 may be connected in parallel between the first and second sub-electrodes SET 1 [ 1 ] and SET 2 [ 1 ] of the first serial stage, and be connected in the forward direction between the first and second power supplies VDD and VSS through the first and second sub-electrodes SET 1 [ 1 ] and SET 2 [ 1 ].
  • the second serial stage (also referred to as “second stage”) may include a pair of first and second sub-electrodes SET 1 [ 2 ] and SET 2 [ 2 ], and one or more second light emitting elements LD 2 electrically connected between the pair of first and second sub-electrodes SET 1 [ 2 ] and SET 2 [ 2 ].
  • the second serial stage may include a first sub-electrode SET 1 [ 2 ] connected to the first power supply VDD via the first serial stage and the pixel circuit PXC, a second sub-electrode SET 2 [ 2 ] which forms, along with the first sub-electrode SET 1 [ 2 ], an electrode pair of the second serial stage and may be connected to the second power supply VSS, and second light emitting elements LD 2 which are electrically connected between the first and second sub-electrodes SET 1 [ 2 ] and SET 2 [ 2 ].
  • a P-type end of each of the second light emitting elements LD 2 may be electrically connected to the first sub-electrode SET 1 [ 2 ] of the second serial stage, and an N-type end of each of the second light emitting elements LD 2 may be electrically connected to the second sub-electrode SET 2 [ 2 ] of the second serial stage.
  • the second light emitting elements LD 2 may be connected in parallel between the first and second sub-electrodes SET 1 [ 2 ] and SET 2 [ 2 ] of the second serial stage, and be connected in the forward direction between the first and second power supplies VDD and VSS through the first and second sub-electrodes SET 1 [ 2 ] and SET 2 [ 2 ].
  • the second sub-electrode SET 2 [ 1 ] of the first serial stage and the first sub-electrode SET 1 [ 2 ] of the second serial stage may be integrally or non-integrally connected to each other.
  • the second sub-electrode SET 2 [ 1 ] of the first serial stage and the first sub-electrode SET 1 [ 2 ] of the second serial stage may form an intermediate electrode that connects the first and second serial stages to each other.
  • the second sub-electrode SET 2 [ 1 ] of the first serial stage and the first sub-electrode SET 1 [ 2 ] of the second serial stage are integrally connected to each other, they may be regarded as being different areas of one intermediate electrode rather than being separate sub-electrodes.
  • the third serial stage (also referred to as “third stage”) may include a pair of first and second sub-electrodes SET 1 [ 3 ] and SET 2 [ 3 ], and one or more third light emitting elements LD 3 electrically connected between the pair of first and second sub-electrodes SET 1 [ 3 ] and SET 2 [ 3 ].
  • the third serial stage may include a first sub-electrode SET 1 [ 3 ] connected to the first power supply VDD via the preceding serial stages (for example, the first and second serial stages) and the pixel circuit PXC, a second sub-electrode SET 2 [ 3 ] which forms, along with the first sub-electrode SET 1 [ 3 ], an electrode pair of the third serial stage and may be connected to the second power supply VSS, and third light emitting elements LD 3 which are electrically connected between the first and second sub-electrodes SET 1 [ 3 ] and SET 2 [ 3 ].
  • a P-type end of each of the third light emitting elements LD 3 may be electrically connected to the first sub-electrode SET 1 [ 3 ] of the third serial stage, and an N-type end of each of the third light emitting elements LD 3 may be electrically connected to the second sub-electrode SET 2 [ 3 ] of the third serial stage.
  • the third light emitting elements LD 3 may be connected in parallel between the first and second sub-electrodes SET 1 [ 3 ] and SET 2 [ 3 ] of the third serial stage, and be connected in the forward direction between the first and second power supplies VDD and VSS through the first and second sub-electrodes SET 1 [ 3 ] and SET 2 [ 3 ].
  • first, second, and third light emitting elements LD 1 , LD 2 , and LD 3 disposed in the first, second, and third serial stages may be identical with or different from each other.
  • the numbers of first, second, and third light emitting elements LD 1 , LD 2 , and LD 3 are not limited thereto.
  • the second sub-electrode SET 2 [ 2 ] of the second serial stage and the first sub-electrode SET 1 [ 3 ] of the third serial stage may be integrally or non-integrally connected to each other.
  • the second sub-electrode SET 2 [ 2 ] of the second serial stage and the first sub-electrode SET 1 [ 3 ] of the third serial stage may form an intermediate electrode that connects the second and third serial stages to each other.
  • the second sub-electrode SET 2 [ 2 ] of the second serial stage and the first sub-electrode SET 1 [ 3 ] of the third serial stage are integrally connected to each other, they may be regarded as being different areas of one intermediate electrode rather than being separate sub-electrodes.
  • the first and second sub-electrodes SET 1 [ 1 ] to SET 1 [ 3 ] and SET 2 [ 1 ] to SET 2 [ 3 ] disposed in each serial stage may form electrode pairs dispersed in each light source unit LSU.
  • first sub-electrode SET 1 also referred to as “first electrode”
  • first sub-electrodes SET 1 will be used to arbitrarily designate at least one first sub-electrode among the first sub-electrodes SET 1 [ 1 ] to SET 1 [ 3 ] (also referred to as “first electrodes”) disposed in each serial stage, or collectively designate the first sub-electrodes SET 1 [ 1 ] to SET 1 [ 3 ] disposed in each serial stage.
  • second sub-electrode SET 2 (also referred to as “second electrode”) or “second sub-electrodes SET 2 ” will be used to arbitrarily designate at least one second sub-electrode among the second sub-electrodes SET 2 [ 1 ] to SET 2 [ 3 ] (also referred to as “second electrodes”) disposed in each serial stage, or collectively designate the second sub-electrodes SET 2 [ 1 ] to SET 2 [ 3 ] disposed in each serial stage.
  • driving current/voltage conditions may be readily controlled to correspond to specifications of a desired product.
  • the light source unit LSU in which the light emitting elements LD are connected in the serial/parallel combination structure makes it possible to reduce driving current compared to that of the light source unit LSU having a structure in which all of the light emitting elements LD are connected in parallel to each other as shown in embodiments of FIGS.
  • the driving current is allowed to flow through the other light emitting elements LD of the corresponding serial stage. Therefore, defects of the pixel PXL may be prevented or reduced.
  • the pixel PXL including the light source unit LSU having a three-stage serial/parallel combination structure has been described for illustrative purposes, but the disclosure is not limited thereto.
  • the pixel PXL in accordance with an embodiment may include a light source unit LSU having only a two-stage serial/parallel combination structure, as illustrated in FIG. 5F .
  • a pixel PXL in accordance with an embodiment may include a light source unit LSU having a four- or more-stage serial/parallel combination structure.
  • the pixel PXL in accordance with an embodiment may include a light source unit LSU having a series-parallel structure including at least two serial stages, and the number of serial stages may be changed depending on embodiments.
  • the pixel PXL may include a light source unit LSU having a six-stage serial/parallel combination structure, as illustrated in FIG. 5G .
  • the light source unit LSU may include first to sixth serial stages successively connected between the first and second power supplies VDD and VSS.
  • Each of the first to sixth serial stages may include a first sub-electrode SET 1 and a second sub-electrode SET 2 which form an electrode pair of the corresponding serial stage, and one or more light emitting elements LD connected in the forward direction between the first and second sub-electrodes SET 1 and SET 2 .
  • the first serial stage may include a pair of first and second sub-electrodes SET 1 [ 1 ] and SET 2 [ 1 ], and one or more first light emitting elements LD 1 (for example, first light emitting elements LD 1 ) electrically connected between the first and second sub-electrodes SET 1 [ 1 ] and SET 2 [ 1 ].
  • first light emitting elements LD 1 for example, first light emitting elements LD 1
  • the other serial stages may have a structure similar to that of the first serial stage.
  • the second serial stage may include first and second sub-electrodes SET 1 [ 2 ] and SET 2 [ 2 ], and one or more second light emitting elements LD 2 (for example, second light emitting elements LD 2 ) electrically connected between the first and second sub-electrodes SET 1 [ 2 ] and SET 2 [ 2 ].
  • the third serial stage may include a pair of first and second sub-electrodes SET 1 [ 3 ] and SET 2 [ 3 ], and one or more third light emitting elements LD 3 (for example, third light emitting elements LD 3 ) electrically connected between the first and second sub-electrodes SET 1 [ 3 ] and SET 2 [ 3 ].
  • the fourth serial stage may include a pair of first and second sub-electrodes SET 1 [ 4 ] and SET 2 [ 4 ], and one or more fourth light emitting elements LD 4 (for example, fourth light emitting elements LD 4 ) electrically connected between the first and second sub-electrodes SET 1 [ 4 ] and SET 2 [ 4 ].
  • the fifth serial stage may include a pair of first and second sub-electrodes SET 1 [ 5 ] and SET 2 [ 5 ], and one or more fifth light emitting elements LD 5 (for example, fifth light emitting elements LD 5 ) electrically connected between the first and second sub-electrodes SET 1 [ 5 ] and SET 2 [ 5 ].
  • the sixth serial stage may include a pair of first and second sub-electrodes SET 1 [ 6 ] and SET 2 [ 6 ], and one or more sixth light emitting elements LD 6 (for example, sixth light emitting elements LD 6 ) electrically connected between the first and second sub-electrodes SET 1 [ 6 ] and SET 2 [ 6 ].
  • a K-th (K is a natural number) serial stage of the light source unit LSU may include first and second sub-electrodes SET 1 [K] and SET 2 [K], and one or more K-th light emitting element LDK electrically connected between the first and second sub-electrodes SET 1 [K] and SET 2 [K].
  • Two sub-electrodes connected between respective serial stages may be integrally or non-integrally connected to each other to form each intermediate electrode.
  • the second sub-electrode SET 2 [ 1 ] of the first serial stage and the first sub-electrode SET 1 [ 2 ] of the second serial stage may form an intermediate electrode that connects the first and second serial stages to each other.
  • the second sub-electrode SET 2 [ 2 ] of the second serial stage and the first sub-electrode SET 1 [ 3 ] of the third serial stage may form an intermediate electrode that connects the second and third serial stages to each other.
  • the second sub-electrode SET 2 [ 3 ] of the third serial stage and the first sub-electrode SET 1 [ 4 ] of the fourth serial stage may form an intermediate electrode that connects the third and fourth serial stages to each other.
  • the second sub-electrode SET 2 [ 4 ] of the fourth serial stage and the first sub-electrode SET 1 [ 5 ] of the fifth serial stage may form an intermediate electrode that connects the fourth and fifth serial stages to each other.
  • the second sub-electrode SET 2 [ 5 ] of the fifth serial stage and the first sub-electrode SET 1 [ 6 ] of the sixth serial stage may form an intermediate electrode that connects the fifth and sixth serial stages to each other.
  • the light source unit LSU of each pixel PXL may be formed of a series-parallel structure including serial stages. Hence, the emission rate of the light emitting elements LD and the luminance of the pixel PXL may be enhanced.
  • the pixel PXL may include a pixel circuit PXC and/or a light source unit LSU which may have various structures.
  • the structure of the pixel PXL which may be applied to the disclosure is not limited to embodiments illustrated in FIGS. 5A to 5 G, and each pixel PXL may have various structures.
  • the pixel circuit PXC included in each pixel PXL may be formed of a pixel circuit which may have various structures and/or be operated by various driving schemes.
  • each pixel PXL may be formed in a passive display device, or the like within the spirit and the scope of the disclosure.
  • the pixel circuit PXC may be omitted, and each of the first and second electrodes ET 1 and ET 2 (or the first sub-electrode SET 1 of the first serial stage and the second sub-electrode SET 2 of the last serial stage) of the light source unit LSU may be connected to or directly connected to a scan line Si, a data line Dj, a power line, and/or a control line.
  • FIGS. 6A and 6B are schematic diagrams of an equivalent circuit each illustrating a pixel PXL in accordance with an embodiment, and for example illustrate different embodiments of a pixel PXL in which open failures have occurred due to different reasons.
  • FIGS. 6A and 6B illustrate an example of an open failure which may occur in the pixel PXL according to an embodiment of FIG. 5E , and detailed descriptions similar or equal to those of embodiments described above will be omitted.
  • first and second sub-electrodes SET 1 [ 2 ] and SET 2 [ 2 ] of the second serial stage there is no light emitting element LD connected in the forward direction between first and second sub-electrodes SET 1 [ 2 ] and SET 2 [ 2 ] of the second serial stage, as illustrated in FIG. 6A , and only a reverse light emitting element LDrv may be connected therebetween.
  • the first and second sub-electrodes SET 1 [ 2 ] and SET 2 [ 2 ] may not be electrically connected to each other and may remain as floating electrodes. Hence, since an open failure occurs in the second serial stage, a current path along which driving current I can flow may be blocked.
  • any light emitting element LD may not be reliably connected between the first and second sub-electrodes SET 1 [ 2 ] and SET 2 [ 2 ] of the second serial stage.
  • the first and second sub-electrodes SET 1 [ 2 ] and SET 2 [ 2 ] may not be electrically connected to each other and may remain as floating electrodes.
  • a current path along which driving current I can flow may be blocked.
  • FIGS. 6A and 6B illustrate an example of the pixel PXL in which an open failure has occurred in the second serial stage
  • the current path along which the driving current I can flow may be block even in case that an open failure occurs in other serial stages.
  • the pixel PXL including a light source unit LSU having a serial structure for example, a light source unit LSU having a serial/parallel combination structure
  • a light source unit LSU having a serial/parallel combination structure if one or more light emitting elements LD are not reliably connected in the forward direction between a pair of first and second sub-electrodes SET 1 and SET 2 that form each serial stage, an open failure may occur, so that the pixel may be revealed as a dark spot.
  • the disclosure discloses, through embodiments to be described below, a pixel PXL having a structure that can be optimized to a biased alignment scheme and in which a light source unit LSU can be efficiently formed or structured using light emitting elements LD supplied to the emission area of each pixel PXL, and discloses a display device and a method of fabricating the display device.
  • FIG. 7 is a schematic plan view illustrating a pixel PXL in accordance with an embodiment.
  • the pixel PXL illustrated in FIG. 7 may be any one of the pixels PXL illustrated in FIGS. 4 to 5G .
  • the pixel PXL illustrated in FIG. 7 may be a pixel PXL corresponding to an embodiment of FIG. 5G .
  • the pixels PXL disposed in the display area (DA of FIG. 4 ) may have substantially identical or similar structures.
  • FIG. 7 illustrates the structure of the pixel PXL, focused on each light source unit LSU.
  • the pixel PXL may selectively further include a circuit element (for example, at least one circuit element that forms the pixel circuit PXC of FIGS. 5A to 5G ) for controlling the light source unit LSU.
  • the circuit element may be disposed on a layer different from that of the light source unit LSU.
  • the circuit element may be disposed in a pixel circuit layer located or disposed on one surface or a surface of the base layer BSL, and the light source unit LSU may be disposed in a display element layer disposed on the pixel circuit layer.
  • FIG. 7 illustrates an embodiment in which each light source unit LSU may be connected, through first and second contact holes CH 1 and CH 2 , to a power line (for example, first and/or second power lines PL 1 and/or PL 2 ), a circuit element (for example, at least one circuit element that forms the pixel circuit PXC), and/or a signal line (for example, a scan line Si and/or a data line Dj), but the disclosure is not limited thereto.
  • a power line for example, first and/or second power lines PL 1 and/or PL 2
  • a circuit element for example, at least one circuit element that forms the pixel circuit PXC
  • a signal line for example, a scan line Si and/or a data line Dj
  • At least one sub-electrode (or a first connection electrode CNE 1 and/or a second connection electrode CNE 2 connected to the at least one sub-electrode) of the first and second sub-electrodes SET 1 and SET 2 of each pixel PXL may be connected to or directly connected to a power line and/or signal line without passing through a contact hole, an intermediate line, and/or the like within the spirit and the scope of the disclosure.
  • the pixel PXL in accordance with an embodiment may include electrode pairs each including a pair of first sub-electrode SET 1 and second sub-electrode SET 2 , light emitting elements LD each of which is electrically connected between any one pair of first and second sub-electrodes SET 1 and SET 2 , a first connection electrode CNE 1 connected to any one of the first sub-electrodes SET 1 (for example, a first sub-electrode SET 1 [ 1 ] of the first electrode pair), and a second connection electrode CNE 2 connected to any one of the second sub-electrodes SET 2 (for example, a second sub-electrode SET 2 [ 6 ] of the last electrode pair).
  • the first sub-electrode SET 1 of the first electrode pair may be the first sub-electrode SET 1 [ 1 ] of the first serial stage.
  • the second sub-electrode SET 2 of the last electrode pair may be the second sub-electrode SET 2 [ 6 ] of the last serial stage (for example, the sixth serial stage).
  • the pixel PXL may further include an opaque bank BNK that encloses each emission area EMA in which the electrode pairs and the light emitting elements LD are disposed, first contact electrodes CET 1 which are individually disposed on the respective first sub-electrodes SET 1 of the electrode pairs disposed in each emission area EMA, second contact electrodes CET 2 which are individually disposed on the respective second sub-electrodes SET 2 of the electrode pairs, and at least one intermediate connection electrode CNEi connected between two successive serial stages.
  • an opaque bank BNK that encloses each emission area EMA in which the electrode pairs and the light emitting elements LD are disposed
  • first contact electrodes CET 1 which are individually disposed on the respective first sub-electrodes SET 1 of the electrode pairs disposed in each emission area EMA
  • second contact electrodes CET 2 which are individually disposed on the respective second sub-electrodes SET 2 of the electrode pairs
  • at least one intermediate connection electrode CNEi connected between two successive serial stages
  • the emission areaEMA of each pixel PXL may be an area defined and/or sectioned by the bank BNK. Furthermore, the emission area EMA may be an area in which the light emitting elements LD and the respective first and second sub-electrodes SET 1 and SET 2 corresponding to serial stages of the corresponding pixel PXL are disposed.
  • the bank BNK may be disposed in a peripheral area of the pixels PXL and/or between the pixels PXL to enclose the emission area EMA of each of the pixels PXL disposed in the display area DA.
  • the bank BNK may include openings corresponding to the respective emission areas EMA of the pixels PXL and be formed in the display area DA in a mesh shape or substantially mesh shape.
  • the bank BNK may include light shielding and/or reflective opaque material, so that light leakage may be prevented from occurring between adjacent pixels PXL.
  • the bank BNK may also function as a dam structure for defining each emission area EMA to which the light emitting elements LD are to be supplied, in case that the light emitting elements LD are supplied to each pixel PXL.
  • electrode pairs that form each of serial stages may be successively disposed in any one direction.
  • a pair of first and second sub-electrodes SET 1 and SET 2 that form each serial stage may be sequentially disposed in the any one direction.
  • each pixel PXL may include electrode pairs which are successively arranged or disposed in a first direction DR 1 in each emission area EMA.
  • Each of the electrode pairs may include a first sub-electrode SET 1 and a second sub-electrode SET 2 which are sequentially disposed in the first direction DR 1 .
  • the first direction DR 1 may be a longitudinal direction (also referred to as “vertical direction” or “lengthwise direction”) of the emission area EMA, and have a length greater than that of a transverse direction of the emission area EMA.
  • the number of electrode pairs disposed in each pixel PXL may be increased.
  • the number of serial stages included in the light source unit LSU may be increased.
  • each light source unit LSU may be formed of three or more electrode pairs, and the light emitting elements LD that form valid light sources of the light source unit LSU may be dispersed in three or more serial stages each including an electrode pair, and be connected to each other in a serial/parallel combination structure.
  • each pixel PXL may include six electrode pairs which are sequentially arranged or disposed in the first direction DR 1 and respectively form first to sixth serial stages.
  • each light source unit LSU may be changed in various ways depending on embodiments. As such, if the light source unit LSU of each pixel PXL is formed of a series-parallel structure including serial stages, the emission rate of the light emitting elements LD may be improved, and the luminance of the pixel PXL may be enhanced.
  • each of the first and second sub-electrodes SET 1 and SET 2 may have a shape extending in a second direction DR 2 intersecting the first direction DR 1 .
  • the second direction DR 2 may be a transverse direction of the emission area EMA, but the disclosure is not limited thereto.
  • the second direction DR 2 may be an oblique direction including a diagonal direction of the emission area EMA.
  • each of the first and second sub-electrodes SET 1 and SET 2 may be an electrode having a substantially bar shape extending in the second direction DR 2 .
  • the shape of each of the first and second sub-electrodes SET 1 and SET 2 may be changed in various ways.
  • at least one of the first and second sub-electrodes SET 1 and SET 2 may have a substantially bar shape extending in an oblique direction inclined with respect to the longitudinal direction and the transverse direction of the emission area EMA, or at least one area may have a substantially curved or substantially bent shape.
  • the number of electrode pairs (for example, the number of serial stages) disposed in each emission area EMA may be changed in various ways.
  • the number of electrode pairs each including the first and second sub-electrodes SET 1 and SET 2 may be designed in various ways depending on the shape and/or size (a surface area, a length, a width, etc.) of the emission area EMA, and the shape and/or size of each of the first and second sub-electrodes SET 1 and SET 2 .
  • the first and second sub-electrodes SET 1 and SET 2 for forming the respective electrode pairs may be arranged or disposed in the opposite directions such that the respective first sub-electrodes SET 1 or the respective second sub-electrodes SET 2 are adjacent to each other.
  • the first and second sub-electrodes SET 1 and SET 2 of each of odd numbered electrode pairs may be sequentially disposed in the first direction DR 1 while the first and second sub-electrodes SET 1 and SET 2 of each of even numbered electrode pairs (for example, the first and second sub-electrodes SET 1 [ 2 ], SET 2 [ 2 ], SET 1 [ 4 ], SET 2 [ 4 ], SET 1 [ 6 ], and SET 2 [ 6 ] of the second, fourth, and sixth serial stages) may be disposed in reverse order in the first direction DR 1 .
  • first sub-electrodes SET 1 or second sub-electrodes SET 2 of two successive electrode pairs may be first integrally or non-integrally connected to each other, and supplied with an identical alignment signal at the step of aligning the light emitting elements LD.
  • the first sub-electrodes SET 1 or the second sub-electrodes SET 2 of the two successive electrode pairs may be separated from each other after the alignment of the light emitting elements LD has been completed. This will be described in detail later herein.
  • a pair of first and second sub-electrodes SET 1 and SET 2 that form each serial stage may be disposed in each emission area EMA at positions spaced apart from each other at regular intervals.
  • the light emitting elements LD may be more regularly dispersed and/or aligned in each emission area EMA.
  • the disclosure is not limited thereto, and the disposition intervals of the first and second sub-electrodes SET 1 and SET 2 may be changed in various ways.
  • each of the second sub-electrodes of remaining electrode pairs other than the last electrode pair may be disposed to be spaced apart from the first sub-electrode SET 1 of a subsequent electrode pair with at least one first or second sub-electrode SET 1 or SET 2 interposed therebetween, and be thus electrically connected to the first sub-electrode SET 1 of the subsequent electrode pair.
  • the second sub-electrodes SET 2 [ 1 ] to SET 2 [ 5 ] of the first to fifth serial stages may be electrically connected to the first sub-electrodes SET 1 [ 2 ] to SET 1 [ 6 ] of the second to sixth serial stages with the first or second sub-electrode SET 1 or SET 2 of a subsequent serial stage interposed therebetween.
  • each of the second sub-electrodes SET 2 of the remaining electrode pairs other than the last electrode pair may be integrally or non-integrally connected to the first sub-electrode SET 1 of a subsequent electrode pair.
  • At least one light emitting element LD may be connected between the first and second sub-electrodes SET 1 and SET 2 of each serial stage.
  • first light emitting elements LD 1 may be connected in parallel between the first and second sub-electrodes SET 1 [ 1 ] and SET 2 [ 1 ] of the first serial stage.
  • second light emitting elements LD 2 , third light emitting elements LD 3 , fourth light emitting elements LD 4 , fifth light emitting elements LD 5 , and sixth light emitting elements LD 6 may be respectively connected in parallel between the first and second sub-electrodes SET 1 [ 2 ] and SET 2 [ 2 ] of the second serial stage, between the first and second sub-electrodes SET 1 [ 3 ] and SET 2 [ 3 ] of the third serial stage, between the first and second sub-electrodes SET 1 [ 4 ] and SET 2 [ 4 ] of the fourth serial stage, between the first and second sub-electrodes SET 1 [ 5 ] and SET 2 [ 5 ] of the fifth serial stage, and between the first and second sub-electrodes SET 1 [ 6 ] and SET 2 [ 6 ] of the sixth serial stage.
  • only a single light emitting element LD may be connected between the first and second sub-electrodes SET 1 [ 2
  • each of the light emitting elements LD may be a light emitting element which is made of material having an inorganic crystal structure and has a subminiature size, for example, ranging from the nanometer scale to the micrometer scale.
  • each light emitting element LD may be a subminiature rod-type light emitting element having a size ranging from the nanometer scale to the micrometer scale, as illustrated in FIGS. 1A to 3B .
  • the size, the type, the shape, etc. of the light emitting elements LD may be changed in various ways.
  • FIG. 7 illustrates that, in the area where a pair of first and second sub-electrodes SET 1 and SET 2 are disposed to face each other, each light emitting element LD is uniformly vertically arranged or disposed in the first direction DR 1 between the first and second sub-electrodes SET 1 and SET 2 , the disclosure is not limited thereto.
  • at least one of the light emitting elements LD may be arranged or disposed and/or connected in a diagonal direction between the first and second sub-electrodes SET 1 and SET 2 .
  • At least one reverse light emitting element LDrv connected in a reverse direction between a pair of first and second sub-electrodes SET 1 and SET 2 may be further disposed in each emission area EMA, or at least one light emitting element (for example, another invalid light source other than the reverse light emitting element LDrv) that is not reliably connected between a pair of first and second sub-electrodes SET 1 and SET 2 may be further disposed in each emission area EMA.
  • at least one light emitting element for example, another invalid light source other than the reverse light emitting element LDrv
  • the light emitting elements LD may be prepared in a diffused form in a solution, and supplied to each pixel area (for example, each emission area enclosed by a bank BNK (also referred to as “pixel defining layer”) disposed between adjacent pixels PXL).
  • the light emitting elements LD may be supplied to each pixel area by an inkjet scheme, a slit coating scheme, or other various schemes.
  • the light emitting elements LD may be mixed with a volatile solvent and supplied to the emission area EMA of each pixel PXL by an inkjet printing method or a slit coating method.
  • the light emitting elements LD may be aligned between the first and second sub-electrodes SET 1 and SET 2 .
  • the solvent may be removed by a volatilization scheme or other schemes. In this way, the light emitting elements LD may be reliably disposed between the first and second sub-electrodes SET 1 and SET 2 .
  • Each of the light emitting elements LD may include a first end EP 1 electrically connected to a first sub-electrode SET 1 of any one electrode pair, and a second end EP 2 connected to a second sub-electrode SET 2 of the any one electrode pair.
  • the first end EP 1 of each of the light emitting elements LD may be a P-type end
  • the second end EP 2 may be an N-type end.
  • each of the light emitting elements LD may be connected in the forward direction between the first and second sub-electrodes SET 1 and SET 2 of any one electrode pair.
  • the first end EP 1 of each of the light emitting elements LD may be connected to or directly connected to a first sub-electrode SET 1 of any one electrode pair, or be connected to the first sub-electrode SET 1 of the any one electrode pair through each first contact electrode CET 1 .
  • the second end EP 2 of each of the light emitting elements LD may be connected to or directly connected to a second sub-electrode SET 2 of any one electrode pair, or be connected to the second sub-electrode SET 2 of the any one electrode pair through each second contact electrode CET 2 .
  • the light emitting elements LD connected in the forward direction between the first and second sub-electrodes SET 1 and SET 2 of each electrode pair may form valid light sources of each serial stage.
  • the first connection electrode CNE 1 may be electrically connected between the first sub-electrode SET 1 of the first electrode pair (for example, the first sub-electrode SET 1 [ 1 ] of the first serial stage) and the first power supply VDD.
  • the first connection electrode CNE 1 may be connected to the first sub-electrode SET 1 [ 1 ] of the first electrode pair, and the other end or another end of the first connection electrode CNE 1 may be connected to the first power supply VDD via the first contact hole CH 1 , etc., within the spirit and the scope of the disclosure.
  • the first connection electrode CNE 1 may be integrally or non-integrally connected with the first sub-electrode SET 1 [ 1 ] of the first electrode pair.
  • the first connection electrode CNE 1 and the first sub-electrode SET 1 [ 1 ] of the first electrode pair may be regarded as being different areas of one electrode, line, or pattern.
  • the first connection electrode CNE 1 may be electrically connected to a circuit element disposed thereunder through the first contact hole CH 1 , and be connected to the first power line PL 1 through the circuit element.
  • each pixel PXL may further include a pixel circuit PXC connected between the first connection electrode CNE 1 and the first power supply VDD.
  • the pixel circuit PXC may be disposed under or below each light source unit LSU and be connected to the first connection electrode CNE 1 of the light source unit LSU through the first contact hole CH 1 .
  • the first connection electrode CNE 1 may be connected, via the first contact hole CH 1 , etc., to a signal line to which a first driving signal is supplied. In an embodiment, the first connection electrode CNE 1 may be connected to or directly connected to the first power line PL 1 or a signal line without using the first contact hole CH 1 , and/or the circuit element. The first connection electrode CNE 1 may be integrally or non-integrally connected to the first power line PL 1 or the signal line.
  • the first connection electrode CNE 1 may be supplied with a voltage of the first power supply VDD or a first driving signal (for example, a scan signal, a data signal, or a other control signal) during a period in which the display device is operated.
  • a first driving signal for example, a scan signal, a data signal, or a other control signal
  • the second connection electrode CNE 2 may be electrically connected between the second sub-electrode SET 2 of the last electrode pair (for example, the second sub-electrode SET 2 of the last serial stage) and the second power supply VSS.
  • the second connection electrode CNE 2 may be connected to the second sub-electrode SET 2 of the last electrode pair (for example, the second sub-electrode SET 2 [ 6 ] of the sixth serial stage), and the other end or another end of the second connection electrode CNE 2 may be connected to the second power supply VSS via the second contact hole CH 2 , etc., within the spirit and the scope of the disclosure.
  • the second connection electrode CNE 2 may be integrally or non-integrally connected with the second sub-electrode SET 2 of the last electrode pair (for example, the second sub-electrode SET 2 [ 6 ] of the sixth serial stage).
  • the second connection electrode CNE 2 is integrally connected with the second sub-electrode SET 1 of the last electrode pair
  • the second connection electrode CNE 2 and the second sub-electrode SET 2 of the last electrode pair may be regarded as being different areas of one electrode, line, or pattern.
  • the second connection electrode CNE 2 may be electrically connected to a second contact hole CH 2 , a circuit element (for example, at least one transistor that forms the pixel circuit PXC), a power line (for example, the second power line PL 2 ), and/or a signal line (for example, a scan line Si, a data line Dj, or a control line).
  • a circuit element for example, at least one transistor that forms the pixel circuit PXC
  • a power line for example, the second power line PL 2
  • a signal line for example, a scan line Si, a data line Dj, or a control line.
  • the second connection electrode CNE 2 may be connected to or directly connected to the second power line PL 2 or a signal line (for example, a signal line to which a second driving signal is supplied) without passing through the second contact hole CH 2 and/or the circuit element, etc., within the spirit and the scope of the disclosure.
  • the second connection electrode CNE 2 may be integrally or non-integrally connected to the second power line PL 2 or the signal line.
  • the second connection electrode CNE 2 may be supplied with a voltage of the second power supply VSS or a second driving signal (for example, a scan signal, a data signal, or a other control signal) during a period in which the display device is operated.
  • a second driving signal for example, a scan signal, a data signal, or a other control signal
  • the first contact electrodes CET 1 are individually disposed on the respective first sub-electrodes SET 1 of the electrode pairs, so that each first sub-electrode SET 1 can be electrically connected to the first end EP 1 of an adjacent light emitting element LD.
  • first contact electrodes CET 1 [ 1 ] to CET 1 [ 6 ] of the first to sixth serial stages may be respectively disposed on the first sub-electrodes SET 1 [ 1 ] to SET 1 [ 6 ] of the first to sixth serial stages.
  • the first contact electrodes CET 1 [ 1 ] to CET 1 [ 6 ] of the first to sixth serial stages may electrically connect the first sub-electrodes SET 1 [ 1 ] to SET 1 [ 6 ] of the first to sixth serial stages to the first ends EP 1 of the first to sixth light emitting elements LD 1 to LD 6 , respectively.
  • the first contact electrodes CET 1 may be selectively formed depending on embodiments. In an embodiment, in the case where the pixel PXL does not include the first contact electrodes CET 1 , the first sub-electrodes SET 1 may be connected with or directly connected with the respective light emitting elements LD.
  • the second contact electrodes CET 2 are individually disposed on the respective second sub-electrodes SET 2 of the electrode pairs, so that each second sub-electrode SET 2 can be electrically connected to the second end EP 2 of an adjacent light emitting element LD.
  • second contact electrodes CET 2 [ 1 ] to CET 2 [ 6 ] of the first to sixth serial stages may be respectively disposed on the second sub-electrodes SET 2 [ 1 ] to SET 2 [ 6 ] of the first to sixth serial stages.
  • the second contact electrodes CET 2 [ 1 ] to CET 2 [ 6 ] of the first to sixth serial stages may electrically connect the second sub-electrodes SET 2 [ 1 ] to SET 2 [ 6 ] of the first to sixth serial stages to the second ends EP 2 of the first to sixth light emitting elements LD 1 to LD 6 , respectively.
  • the second contact electrodes CET 2 may be selectively formed depending on embodiments.
  • the second sub-electrodes SET 2 may be connected with or directly connected with the respective light emitting elements LD.
  • the light emitting elements LD may be more reliably connected between the first and second sub-electrodes SET 1 and SET 2 .
  • each of the second sub-electrodes SET 2 of the remaining electrode pairs other than the last electrode pair may be connected to the first sub-electrode SET 1 of a subsequent electrode pair through each corresponding intermediate connection electrode CNEi.
  • each intermediate connection electrode CNEi may integrally extend from any one sub-electrode of the second sub-electrode SET 2 of each of the remaining electrode pairs and the first sub-electrode SET 1 of the subsequent electrode pair.
  • the first or second contact electrode CET 1 or CET 2 disposed on the other sub-electrode of the second sub-electrode SET 2 of each of the remaining electrode pairs and the first sub-electrode SET 1 of the subsequent electrode pair may include a protrusion PRT which protrudes from any one end or an end in the second direction DR 2 and is electrically connected to each corresponding intermediate connection electrode CNEi.
  • the second sub-electrode SET 2 [ 1 ] of the first serial stage and the first sub-electrode SET 1 [ 2 ] of the second serial stage may be electrically connected to each other both through a protrusion PRT that integrally extends from the second contact electrode CET 2 [ 1 ] of the first serial stage that is disposed on the second sub-electrode SET 2 [ 1 ] of the first serial stage and through the first intermediate connection electrode CNEi 1 that integrally extends from the first sub-electrode SET 1 [ 2 ] of the second serial stage.
  • the protrusion PRT and the first intermediate connection electrode CNEi 1 may be electrically connected to each other through a first contact part CNT 1 .
  • each contact part CNT including the first contact part CNT 1 may be implemented by a contact hole or the like, but the disclosure is not limited thereto.
  • the second sub-electrode SET 2 [ 2 ] of the second serial stage and the first sub-electrode SET 1 [ 3 ] of the third serial stage may be electrically connected to each other both through the second intermediate connection electrode CNEi 2 that integrally extends from the second sub-electrode SET 2 [ 2 ] of the second serial stage and through a protrusion PRT that integrally extends from the first contact electrode CET 1 [ 3 ] of the third serial stage that is disposed on the first sub-electrode SET 1 [ 3 ] of the third serial stage.
  • the protrusion PRT and the second intermediate connection electrode CNEi 2 may be electrically connected to each other through a second contact part CNT 2 .
  • the second sub-electrode SET 2 [ 3 ] of the third serial stage and the first sub-electrode SET 1 [ 4 ] of the fourth serial stage may be electrically connected to each other both through a protrusion PRT that integrally extends from the second contact electrode CET 2 [ 3 ] of the third serial stage that is disposed on the second sub-electrode SET 2 [ 3 ] of the third serial stage and through a third intermediate connection electrode CNEi 3 that integrally extends from the first sub-electrode SET 1 [ 4 ] of the fourth serial stage.
  • the protrusion PRT and the third intermediate connection electrode CNEi 3 may be electrically connected to each other through a third contact part CNT 3 .
  • the second sub-electrode SET 2 [ 4 ] of the fourth serial stage and the first sub-electrode SET 1 [ 5 ] of the fifth serial stage may be electrically connected to each other both through a fourth intermediate connection electrode CNEi 4 that integrally extends from the second sub-electrode SET 2 [ 4 ] of the fourth serial stage and through a protrusion PRT that integrally extends from the first contact electrode CET 1 [ 5 ] of the fifth serial stage that is disposed on the first sub-electrode SET 1 [ 5 ] of the fifth serial stage.
  • the protrusion PRT and the fourth intermediate connection electrode CNEi 4 may be electrically connected to each other through a fourth contact part CNT 4 .
  • the second sub-electrode SET 2 [ 5 ] of the fifth serial stage and the first sub-electrode SET 1 [ 6 ] of the sixth serial stage may be electrically connected to each other both through a protrusion PRT that integrally extends from the second contact electrode CET 2 [ 5 ] of the fifth serial stage that is disposed on the second sub-electrode SET 2 [ 5 ] of the fifth serial stage and through a fifth intermediate connection electrode CNEi 5 that integrally extends from the first sub-electrode SET 1 [ 6 ] of the sixth serial stage.
  • the protrusion PRT and the fifth intermediate connection electrode CNEi 5 may be electrically connected to each other through a fifth contact part CNT 5 .
  • the first to fifth intermediate connection electrodes CNEi 1 to CNEi 5 may be alternately disposed on different sides (for example, a left side and a right side) of the emission area EMA. Hence, even in case that all of the first to fifth intermediate connection electrodes CNEi 1 to CNEi 5 are formed on an identical layer, they may be prevented from short-circuiting with each other.
  • the pixel PXL in accordance with an embodiment may include electrode pairs which are successively disposed in the first direction DR 1 and form each serial stage.
  • Each electrode pair may include a pair of first and second sub-electrodes SET 1 and SET 2 that are successively disposed in the first direction DR 1 .
  • the second sub-electrode SET 2 of each of the remaining electrode pairs other than the last electrode pair may be disposed to be spaced apart from the first sub-electrode SET 1 of a subsequent electrode pair with at least one first or second sub-electrode SET 1 or SET 2 interposed therebetween.
  • the first and second sub-electrodes SET 1 and SET 2 of the respective electrode pairs may be disposed in the opposite direction based on the first direction DR 1 such that the first sub-electrodes SET 1 or the second sub-electrodes SET 2 of two successive electrode pairs are adjacent to each other.
  • the second sub-electrode SET 2 of each of the remaining electrode pairs may be electrically connected to the first sub-electrode SET 1 of a subsequent electrode pair through each intermediate connection electrode CNEi, etc., within the spirit and the scope of the disclosure.
  • the light source unit LSU including serial stages may be formed efficiently using light emitting elements LD supplied to the emission area EMA of each pixel PXL, and the light emitting elements LD may be more uniformly arranged or disposed between electrode pairs corresponding to respective serial stages.
  • light emitting elements LD may be connected in an identical direction between a pair of first and second sub-electrodes SET 1 and SET 2 by using the biased alignment scheme.
  • the light emitting elements LD may be biased-aligned such that the respective first ends EP 1 of the light emitting elements LD are disposed to face any one first sub-electrode SET 1 , and the respective second ends EP 2 of the light emitting elements LD are disposed to face any one second sub-electrode SET 2 adjacent to the any one first sub-electrode SET 1 .
  • the rates at which the light emitting elements LD are respectively aligned in the forward direction and the reverse direction between a pair of first and second sub-electrodes SET 1 and SET 2 may be substantially identical or similar to each other.
  • approximately 80% or more (ideally 100%) of the light emitting elements LD supplied to the emission area EMA of each pixel PXL may be aligned in the forward direction between the first and second sub-electrodes SET 1 and SET 2 .
  • the first sub-electrodes SET 1 and the second sub-electrodes SET 2 are separated from each other, and the sub-electrodes may be re-connected to each other such that electrode pairs are connected in series to each other, for example, as shown in FIG. 7 .
  • the light emitting elements LD supplied to the emission area EMA of each pixel PXL are maximally connected in the forward direction between the first and second sub-electrodes SET 1 and SET 2 , so that an application efficiency of the light emitting elements LD may be enhanced.
  • a reverse light emitting element LDrv is prevented or mitigated from occurring, leakage current due to the reverse light emitting element LDrv may be blocked or reduced.
  • the number of serial stages included in the light source unit LSU having a serial/parallel combination structure may be increased.
  • an apparatus for example, an inkjet nozzle, for supplying light emitting elements LD to each emission area EMA moves in the longitudinal direction of the emission area EMA (for example, in the longitudinal direction of the pixel PXL)
  • a liquid drop of a light-emitting-element mixed solution for example, light-emitting-element ink
  • the light emitting elements LD may be relatively regularly distributed in the longitudinal direction of the emission area EMA even if they are irregularly distributed in the transverse direction of the emission area EMA.
  • a distribution deviation (for example, a deviation in number) of the light emitting elements LD between the serial stages may be reduced, and the light emitting elements LD may be relatively regularly distributed in the respective serial stages.
  • an open failure of the pixel PXL which may occur because no light emitting element LD may be connected in the forward direction in a specific or given serial stage can be prevented or minimized.
  • the numbers of light emitting elements LD connected in the forward direction in the respective serial stages are relatively uniform, alignment/driving current may be prevented from being focused on a small number of light emitting elements LD aligned in the forward direction in any one serial stage. Therefore, each pixel PXL may be more reliably driven.
  • the emission efficiency and the luminance of each pixel PXL may be enhanced, and a failure rate may be mitigated.
  • FIGS. 8 to 11 are schematic plan views each illustrating a pixel PXL in accordance with an embodiment, and for example illustrate different embodiments pertaining to the pixel PXL of FIG. 7 .
  • like reference numerals are used to designate identical or similar components as those of at least one above-mentioned embodiment including an embodiment of FIG. 7 , and detailed descriptions thereof will be omitted.
  • each protrusion PRT may have a width less than that of the first or second contact electrode CET 1 or CET 2 connected thereto, as shown in FIG. 7 , or may have a width substantially identical with that of the first or second contact electrode CET 1 or CET 2 connected thereto, as shown in an embodiment of FIG. 8 .
  • FIGS. 7 and 8 there are illustrated the pixels PXL capable of simplifying a fabricating process by integrally forming each protrusion PRT with any one first or second contact electrode CET 1 or CET 2 , and integrally forming each intermediate connection electrode CNEi with any one first or second sub-electrode SET 1 or SET 2 .
  • the disclosure is not limited thereto.
  • at least one protrusion PRT and/or an intermediate connection electrode CNEi may be formed through a process different from that of the first and second sub-electrodes SET 1 and SET 2 and the first and second contact electrodes CET 1 and CET 2 and formed on a layer different from that thereof.
  • a connection structure between serial stages may be changed in various ways.
  • the pixel PXL may further include at least one of a first dummy electrode DET 1 disposed adjacent to the first electrode pair (for example, the first and second sub-electrodes SET 1 [ 1 ] and SET 2 [ 1 ] of the first serial stage) and a second dummy electrode DET 2 disposed adjacent to the last electrode pair (for example, the first and second sub-electrodes SET 1 [ 6 ] and SET 2 [ 6 ] of the sixth serial stage).
  • the first and second dummy electrodes DET 1 and DET 2 each may be a floating electrode which is electrically isolated.
  • the first dummy electrode DET 1 may be disposed adjacent to the first or second sub-electrode SET 1 [ 1 ] or SET 2 [ 1 ] of the first electrode pair.
  • the first dummy electrode DET 1 may be disposed in an outer area (for example, an upper outer area) of the emission area EIA such that the first dummy electrode DET 1 is adjacent to the first sub-electrode SET 1 [ 1 ] of the first electrode pair.
  • the first dummy electrode DET 1 may be first fabricated to be connected with the first sub-electrode SET 1 [ 1 ] of the first electrode pair, and thereafter separated and electrically isolated from the first sub-electrode SET 1 [ 1 ] of the first electrode pair after the alignment of the light emitting elements LD is completed.
  • the second dummy electrode DET 2 may be disposed adjacent to the first or second sub-electrode SET 1 [ 6 ] or SET 2 [ 6 ] of the last electrode pair, for example, the first or second sub-electrode SET 1 [ 6 ] or SET 2 [ 6 ] of the sixth serial stage.
  • the second dummy electrode DET 2 may be disposed in another outer area (for example, a lower outer area) of the emission area EIA such that the second dummy electrode DET 2 is adjacent to the first sub-electrode SET 1 [ 6 ] of the sixth serial stage.
  • the pixel PXL may selectively further include a first dummy contact electrode DCET 1 disposed on the first dummy electrode DET 1 , and a second dummy contact electrode DCET 2 disposed on the second dummy electrode DET 2 .
  • the first dummy contact electrode DCET 1 may be electrically connected with the first dummy electrode DET 1 to form a floating electrode having a multilayer structure.
  • the second dummy contact electrode DCET 2 may be electrically connected with the second dummy electrode DET 2 to form a floating electrode having a multilayer structure.
  • the first and second dummy contact electrodes DCET 1 and DCET 2 may be formed along with the first and second contact electrodes CET 1 and CET 2 , and have individual patterns separated therefrom.
  • the pixel PXL may further include partition walls or banks PW (also referred to as “walls” or “bank patterns”) disposed in each emission area EMA.
  • Each partition wall PW may be disposed under or below at least one first sub-electrode SET 1 or at least one second sub-electrode SET 2 .
  • partition walls PW each having an individual pattern may be disposed under or below sub-electrodes arranged or disposed at the first and last positions with respect to the first direction DR 1 , for example, under or below the first sub-electrode SET 1 [ 1 ] of the first serial stage and the first sub-electrode SET 1 [ 6 ] of the sixth serial stage.
  • Partition walls PW may be disposed under or below the other sub-electrodes, for example, first and second sub-electrodes SET 1 and SET 2 arranged or disposed at intermediate positions such that each partition wall PW overlap first or second sub-electrodes SET 1 or SET 2 .
  • each of the partition walls PW arranged or disposed at the intermediate positions of the emission area EMA may be disposed under or below two first or second sub-electrodes SET 1 or SET 2 that are successively disposed in the first direction DR 1 (for example, first or second sub-electrodes SET 1 or SET 2 of two successive serial stages disposed adjacent to each other) such that the partition wall PW overlaps the two first or second sub-electrodes SET 1 or SET 2 in common.
  • the partition walls PW may be individually separately disposed under or below the first and second sub-electrodes SET 1 and SET 2 , respectively.
  • the shape, size, and/or arrangement structure of the partition walls PW may be changed in various ways depending on embodiments.
  • the first and second sub-electrodes SET 1 and SET 2 may protrude upward in an area in which the partition walls PW are disposed.
  • light emitted from the opposite ends of the light emitting elements LD that face the first and second sub-electrodes SET 1 and SET 2 may be more effectively controlled to travel in a frontal direction of the display device.
  • Each pixel PXL in accordance with the above-mentioned embodiments may have a structure optimized to the biased alignment scheme in the same manner as that of the pixel PXL in accordance with an embodiment of FIG. 7 , and obtain effects corresponding to that of an embodiment of FIG. 7 .
  • the light source unit LSU including serial stages are formed efficiently using light emitting elements LD supplied to the emission area EMA of each pixel PXL, and the light emitting elements LD may be uniformly arranged or disposed in each serial stage. Consequently, the emission efficiency and the luminance of each pixel PXL may be enhanced, and a failure rate may be reduced.
  • FIGS. 12A to 12D each are a schematic cross-sectional view illustrating a pixel PXL in accordance with an embodiment, and for example illustrate different embodiments of a cross-section of the pixel PXL corresponding to line I-I′ of FIG. 11 .
  • FIGS. 12A to 12D each illustrate a cross-sectional structure of each pixel PXL focused on any one first light emitting element LD 1 and a peripheral area thereof, and the pixels PXL may have a substantially identical or similar cross-sectional structure in the respective serial stages.
  • the pixel PXL in accordance with an embodiment and the display device including the pixel PXL may include a display element layer DPL including light emitting elements LD disposed in the emission area EMA of each pixel PXL. Furthermore, the pixel PXL or the display device including the pixel PXL may selectively further include a pixel circuit layer PCL. For example, the pixel PXL or the display device including the pixel PXL may further include a pixel circuit layer PCL disposed between the base layer BSL and the display element layer DPL.
  • the pixel circuit layer PCL may include at least one circuit element electrically connected to the light emitting elements LD of the corresponding pixel PXL.
  • the pixel circuit layer PCL may include at least one circuit element which forms the pixel circuit PXC of each pixel PXL.
  • the pixel circuit layer PCL may include transistors T and a storage capacitor Cst that are disposed in each pixel area and form the corresponding pixel circuit PXC, and further include at least one power line and/or at least one signal line that may be connected to the pixel circuit PXC and/or the light source unit LSU.
  • the pixel circuit layer PCL may be omitted.
  • FIGS. 12A to 12D representatively illustrate only any one transistor T among the circuit elements and the lines that are disposed in the pixel circuit layer PCL.
  • the plane/section structure of the pixel circuit layer PCL may be changed in various ways.
  • the positions and cross-sectional structures of each transistor T may be changed in various ways depending on embodiments.
  • the pixel circuit layer PCL may include insulating layers disposed between respective electrodes and/or lines.
  • the pixel circuit layer PCL may include a buffer layer BFL, a gate insulating layer GI, an interlayer insulating layer ILD, and a passivation layer PSV which may be successively stacked each other on one surface or a surface of the base layer BSL.
  • the pixel circuit layer PCL may further include at least one light shielding pattern (not shown) disposed under or below at least some or a part of transistors T.
  • the buffer layer BFL may prevent impurities from diffusing into each circuit element.
  • the buffer layer BFL may be formed of a single layer, or may be formed of multiple layers having at least two layers. In the case where the buffer layer BFL has a multilayer structure, the respective layers may be formed of the same material or different materials. In an embodiment, the buffer layer BFL may be omitted.
  • each transistor T may include a semiconductor layer SCL, a gate electrode GE, and first and second transistor electrodes TE 1 and TE 2 .
  • FIGS. 12A to 12D illustrate an embodiment in which each transistor T may include the first and second transistor electrodes TE 1 and TE 2 that are formed separately from the semiconductor layer SCL, the disclosure is not limited thereto.
  • the first and/or second transistor electrode TE 1 and/or TE 2 provided in at least one transistor T disposed in each pixel area may be integrally formed with the corresponding semiconductor layer SCL.
  • the semiconductor layer SCL may be disposed on the buffer layer BFL.
  • the semiconductor layer SCL may be disposed between the gate insulating layer GI and the base layer BSL on which the buffer layer BFL is formed.
  • the semiconductor layer SCL may include a first area which comes into contact with each first transistor electrode TE 1 , a second area which comes into contact with each second transistor electrode TE 2 , and a channel area disposed between the first and second areas.
  • one of the first and second areas may be a source area, and the other may be a drain area.
  • the semiconductor layer SCL may be a semiconductor pattern formed of polysilicon, amorphous silicon, an oxide semiconductor, etc., within the spirit and the scope of the disclosure.
  • the channel area of the semiconductor layer SCL may be an intrinsic semiconductor, which is an undoped semiconductor pattern.
  • Each of the first and second areas of the semiconductor layer SCL may be a semiconductor pattern doped with an impurity.
  • the gate electrode GE may be disposed on the semiconductor layer SCL with the gate insulating layer GI interposed therebetween.
  • the gate electrode GE may be disposed between the gate insulating layer GI and the interlayer insulating layer ILD and overlap at least one area of the semiconductor layer SCL.
  • the first and second transistor electrodes TE 1 and TE 2 may be disposed on each semiconductor layer SCL with at least one interlayer insulating layer ILD interposed therebetween.
  • the first and second transistor electrodes TE 1 and TE 2 may be disposed on respective different ends of the semiconductor layer SCL with the gate insulating layer GI and the interlayer insulating layer ILD interposed therebetween.
  • the first and second transistor electrodes TE 1 and TE 2 may be electrically connected to each semiconductor layer SCL.
  • the first and second transistor electrodes TE 1 and TE 2 may be connected to the first and second areas of the semiconductor layer SCL through corresponding contact holes which pass through the gate insulating layer GI and the interlayer insulating layer ILD.
  • any one of the first and second transistor electrodes TE 1 and TE 2 may be a source electrode, and the other may be a drain electrode.
  • At least one transistor T provided in the pixel circuit PXC may be connected to at least one pixel electrode.
  • any one (for example, the drain electrode) of the first and second transistor electrodes TE 1 and TE 2 of the first transistor T 1 illustrated in FIG. 5G may be electrically connected to a first first-sub-electrode SET 1 (for example, the first sub-electrode SET 1 [ 1 ] of the first serial stage) of the corresponding pixel PXL both through a contact hole (for example, the first contact hole CH 1 ) passing through the passivation layer PSV and through the first connection electrode CNE 1 provided or disposed over the passivation layer PSV.
  • At least one signal line and/or power line that may be connected to each pixel PXL may be disposed on a layer identical with that of one electrode of each of the circuit elements that form the pixel circuit PXC.
  • the scan line Si of each pixel PXL may be disposed on the same layer or a same layer as that of the gate electrodes GE.
  • the data line Dj of each pixel PXL may be disposed on the same layer or a same layer as that of the first and second transistor electrodes TE 1 and TE 2 of the transistors T.
  • the first and/or second power lines PL 1 and PL 2 may be disposed on the same layer or a same layer as that of the gate electrodes GE or the first and second transistor electrodes TE 1 and TE 2 of the transistors T.
  • the display element layer DPL may include a light source unit LSU of each of the pixels PXL.
  • the display element layer DPL may include first and second sub-electrodes SET 1 and SET 2 of each of electrode pairs disposed in the emission area EMA of each pixel PXL, and light emitting elements LD arranged or disposed between the first and second sub-electrodes SET 1 and SET 2 .
  • the display element layer DPL may selectively further include partition walls PW that protrude areas of the first and second sub-electrodes SET 1 and SET 2 upward, and first and second contact electrodes CET 1 and CET 2 to more reliably connect the light emitting elements LD between the first and second sub-electrodes SET 1 and SET 2 .
  • the display element layer DPL may further include, for example, at least one conductive layer and/or insulating layer.
  • the display element layer DPL may include partition walls PW, first and second sub-electrodes SET 1 and SET 2 , a first insulating layer INS 1 , light emitting elements LD, an insulating pattern INP, first and second contact electrodes CET 1 and CET 2 , and a second insulating layer INS 2 , which are successively disposed and/or formed over the base layer BSL and/or the pixel circuit layer PCL.
  • the partition walls PW may be disposed at positions spaced apart from each other in the emission area EMA of each pixel PXL.
  • the partition walls PW may protrude from the base layer BSL and/or the pixel circuit layer PCL in a height direction of the base layer BSL.
  • the partition walls PW may have substantially the same height, but the disclosure is not limited thereto.
  • the partition walls PW may be disposed between the base layer BSL and/or the pixel circuit layer PCL and each first or second sub-electrode SET 1 or SET 2 .
  • the partition walls PW may be disposed adjacent to the first and second ends EP 1 and EP 2 of the light emitting elements LD.
  • the partition walls PW may be disposed to face the first and/or second ends EP 1 and/or EP 2 of the light emitting elements LD adjacent thereto.
  • the partition walls PW may have various shapes.
  • the partition walls PW each may have a substantially trapezoidal cross-section which may be reduced in width upward, as illustrated in FIGS. 12A and 12C .
  • Each of the partition walls PW may have an inclined surface on at least one side surface or a side surface.
  • the partition walls PW each may have a substantially semi-circular or substantially semi-elliptical cross-section, the width of which may be gradually reduced upward.
  • Each of the partition walls PW may have a substantially curved surface on at least one side surface or a side surface, and at least electrode (or a sub-electrode) and/or an insulating layer that may be disposed over the partition walls PW may have a substantially curved surface in areas corresponding to the partition walls PW.
  • the shape of the partition walls PW is not particularly limited, and it may be changed in various ways. Furthermore, in an embodiment, at least one of the partition walls PW may be omitted, or the position thereof may be changed.
  • the partition walls PW may include insulating material including at least one inorganic material and/or organic material.
  • the partition walls PW may include at least one inorganic layer including various inorganic insulating materials such as silicon nitride (SiNx) or silicon oxide (SiOx).
  • the partition walls PW each may include at least one organic layer and/or photoresist layer containing various kinds of organic insulating materials, or may form a single- or multi-layer insulator containing organic/inorganic materials in combination.
  • the constituent material of the partition walls PW may be changed in various ways.
  • the partition walls PW each may function as a reflector.
  • the partition walls PW, along with the first and second sub-electrodes SET 1 and SET 2 provided or disposed thereover, may function as reflectors that guide light emitted from each light emitting element LD in a desired direction, thus enhancing the light efficiency of the pixel PXL.
  • the first and second sub-electrodes SET 1 and SET 2 may be disposed over the respective partition walls PW.
  • the first and second sub-electrodes SET 1 and SET 2 may be disposed at positions spaced apart from each other in each pixel area (by way of example, each emission area EMA).
  • the first and second sub-electrodes SET 1 and SET 2 , etc. that are disposed over the respective partition walls PW may have shapes corresponding to respective shapes of the partition walls PW.
  • the first and second sub-electrodes SET 1 and SE 2 each may have a substantially inclined surface or a substantially curved surface corresponding to that of each corresponding partition wall PW and protrude in a height direction of the base layer BSL.
  • the partition walls PW may not be formed.
  • Each of the first and second sub-electrodes SET 1 and SET 2 may be formed in a substantially planar shape on the passivation layer PSV.
  • Each of the first and second sub-electrodes SET 1 and SET 2 may include at least one conductive material.
  • each of the first and second sub-electrodes SET 1 and SET 2 may include at least one conductive material among at least one metal of various metal materials including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chrome (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), etc., or an alloy thereof, conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), antimony zinc oxide (AZO), indium tin zinc oxide (ITZO), tin oxide (SnO 2 ), and a conductive polymer such as PEDOT, but the disclosure is not limited thereto.
  • each of the first and second sub-electrodes SET 1 and SET 2 may include other conductive materials such as a carbon nano tube and a graphene.
  • each of the first and second sub-electrodes SET 1 and SET 2 may include at least one of various conductive materials to have conductivity, and the constituent material thereof is not particularly limited.
  • each of the first and second sub-electrodes SET 1 and SET 2 may have the same conductive material, or at least one different conductive material.
  • Each of the first and second sub-electrodes SET 1 and SET 2 may have a single-layer or multilayer structure.
  • each of the first and second sub-electrodes SET 1 and SET 2 may include a reflective electrode layer including reflective conductive material.
  • Each of the first and second sub-electrodes SET 1 and SET 2 may selectively further include at least one of at least one transparent electrode layer disposed over and/or under or below the reflective electrode layer, and at least one conductive capping layer covering or overlapping an upper portion of the reflective electrode layer and/or the transparent electrode layer.
  • the reflective electrode layer of each of the first and second sub-electrodes SET 1 and SET 2 may be formed of conductive material having a uniform reflectivity.
  • the reflective electrode layer may include at least one of various metal materials including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chrome (Cr), titanium (Ti), molybdenum (Mo), copper (Cu), etc., or an alloy thereof, but the disclosure is not limited thereto.
  • reflective electrode layer may be formed of various reflective conductive materials.
  • Each of the first and second sub-electrodes SET 1 and SET 2 that may include the reflective electrode layer may enable light emitted from the opposite ends of each of the light emitting elements LD, for example, the first and second ends EP 1 and EP 2 , to travel in a direction (for example, in a frontal direction) in which an image is displayed.
  • first and second sub-electrodes SET 1 and SET 2 have substantially inclined or substantially curved surfaces corresponding to the shapes of the respective partition walls PW and are disposed to face the first and second ends EP 1 and EP 2 of the light emitting elements LD, light emitted from the first and second ends EP 1 and EP 2 of each of the light emitting elements LD may be reflected by the first and second sub-electrodes SET 1 and SET 2 and thus further reliably travel in the frontal direction of the display panel PNL (for example, in an upward direction of the base layer BSL). Thereby, the efficiency of light emitted from the light emitting elements LD may be enhanced.
  • each of the first and second sub-electrodes SET 1 and SET 2 may be formed of various transparent conductive materials.
  • the transparent electrode layer may include ITO, IZO or ITZO, but the disclosure is not limited thereto.
  • each of the first and second sub-electrodes SET 1 and SET 2 may have a three-layer structure having a stacked structure of ITO/Ag/ITO. As such, if the first and second sub-electrodes SET 1 and SET 2 each are formed of a multilayer structure having at least two layers, a voltage drop due to signal delay (RC delay) may be minimized. Thus, a desired voltage can be effectively transmitted to the light emitting elements LD.
  • RC delay signal delay
  • each of the first and second sub-electrodes SET 1 and SET 2 may include the conductive capping layer that covers or overlaps the reflective electrode layer and/or the transparent electrode layer, it is possible to prevent the reflective electrode layer of the first and second sub-electrodes SET 1 and SET 2 from being damaged due to defects caused during the fabricating process of the pixel PXL.
  • the conductive capping layer may be selectively included in the first and second sub-electrodes SET 1 and SET 2 , and may be omitted depending on embodiments.
  • the conductive capping layer may be considered as a component of each of the first and second sub-electrodes SET 1 and SET 2 , or considered as a separate component disposed on the first and second sub-electrodes SET 1 and SET 2 .
  • the first insulating layer INS 1 may be disposed on an area of each of the first and second sub-electrodes SET 1 and SET 2 .
  • the first insulating layer INS 1 may be formed to cover or overlap areas of the first and second sub-electrodes SET 1 and SET 2 , and may include an opening to expose other areas of the first and second sub-electrodes SET 1 and SET 2 .
  • the first insulating layer INS 1 may expose the first and second sub-electrodes SET 1 and SET 2 in first and second contact areas CNP 1 and CNP 2 .
  • the first insulating layer INS 1 may not be formed.
  • the light emitting elements LD may be disposed on or directly disposed on the passivation layer PSV and/or one end or an end of each of the first and second sub-electrodes SET 1 and SET 2 .
  • the first insulating layer INS 1 may be primarily formed to cover or overlap the overall surfaces of the first and second sub-electrodes SET 1 and SET 2 . After the light emitting elements LD are supplied and aligned on the first insulating layer INS 1 , the first insulating layer INS 1 may be partially open to expose the first and second sub-electrodes SET 1 and SET 2 in respective areas (for example, the respective first and second contact areas CNP 1 and CNP 2 ) on the partition walls PW. In an embodiment, the first insulating layer INS 1 may be patterned in the form of an individual pattern which is sectionally disposed under or below the light emitting elements LD after the supply and alignment of the light emitting elements LD have been completed.
  • the first insulating layer INS 1 may be interposed between the first and second sub-electrodes SET 1 and SET 2 and the light emitting elements LD, and may expose at least one area of each of the first and second sub-electrodes SET 1 and SET 2 .
  • the first insulating layer INS 1 may be formed to cover or overlap the first and second sub-electrodes SET 1 and SET 2 , so that it is possible to prevent the first and second sub-electrodes SET 1 and SET 2 from being damaged or to prevent metal from being precipitated in a subsequent process.
  • the first insulating layer INS 1 may stably support each light emitting element LD.
  • the first insulating layer INS 1 may be formed of a single layer or multiple layers, and include at least one inorganic insulating material and/or organic insulating material.
  • the first insulating layer INS 1 may include various kinds of organic/inorganic insulating materials including silicon nitride (SiNx), silicon oxide (SiOx), aluminum oxide (Al 2 O 3 ), etc., within the spirit and the scope of the disclosure.
  • the constituent material of the first insulating layer INS 1 is not particularly limited.
  • Light emitting elements LD may be supplied to and aligned in each pixel area, by way of example, the emission area EMA of each pixel PXL, in which the first insulating layer INS 1 is formed.
  • light emitting elements LD may be supplied to each emission area EMA through an inkjet scheme or a slit-coating scheme, and the light emitting elements LD may be aligned with the directionality between the first and second sub-electrodes SET 1 and SET 2 by alignment signals (or alignment voltages) applied to the first and second sub-electrodes SET 1 and SET 2 .
  • At least some or a part of the light emitting elements LD may be disposed in the horizontal direction between a pair of first and second sub-electrodes SET 1 and SET 2 such that the opposite ends (for example, the first and second ends EP 1 and EP 2 ) of each light emitting element LD with respect to the longitudinal direction thereof overlap the pair of first and second sub-electrodes SET 1 and SET 2 .
  • other some or a part of the light emitting elements LD may be disposed in a diagonal direction between the pair of first and second sub-electrodes SET 1 and SET 2 .
  • At least some or a part of the light emitting elements LD may be disposed between a pair of first and second sub-electrodes SET 1 and SET 2 such that the at least some or a part of light emitting elements LD do not overlap the first and second sub-electrodes SET 1 and SET 2 , and may be connected to the first and second sub-electrodes SET 1 and SET 2 respectively through the first contact electrode CET 1 and the second contact electrode CET 2 .
  • the insulating pattern INP may be disposed on areas of the light emitting elements LD.
  • the insulating pattern INP may expose the first and second ends EP 1 and EP 2 of the light emitting elements LD and be partially disposed over only the areas of the light emitting elements LD including respective central areas of the light emitting elements LD.
  • the insulating pattern INP may be formed in an independent pattern in each emission area EMA, but the disclosure is not limited thereto.
  • the insulating pattern INP may be omitted depending on embodiments.
  • the opposite ends of the first and second contact electrodes CET 1 and CET 2 may be disposed on or directly disposed on the light emitting elements LD.
  • the insulating pattern INP may be formed of a single layer or multiple layers, and include at least one inorganic insulating material and/or organic insulating material.
  • the insulating pattern INP may include various kinds of organic/inorganic insulating materials including silicon nitride (SiNx), silicon oxide (SiOx), aluminum oxide (Al 2 O 3 ), photoresist (PR) material, etc., within the spirit and the scope of the disclosure.
  • the constituent material of the insulating pattern INP is not particularly limited.
  • the insulating pattern INP is formed on the light emitting elements LD so that the light emitting elements LD may be prevented from being removed from the aligned position. Furthermore, in the case where space may be present between the first insulating layer INS 1 and the light emitting elements LD, the space may be filled with the insulating material drawn thereinto during a process of forming the insulating pattern INP. Consequently, the light emitting elements LD may be more stably supported.
  • the insulating pattern INP may be formed only over the light emitting elements LD, or may be formed both over and under or below the light emitting elements LD.
  • the opposite ends of the light emitting elements LD for example, the first and second ends EP 1 and EP 2 , which are not covered with or overlapped by the insulating pattern INP, may be respectively covered with or overlapped by the first and second contact electrodes CET 1 and CET 2 .
  • respective ends of the first and second contact electrodes CET 1 and CET 2 may be disposed, at positions spaced apart from each other, on the first and second ends EP 1 and EP 2 of the light emitting elements LD, with the insulating pattern INP interposed therebetween.
  • the first and second contact electrodes CET 1 and CET 2 may be simultaneously formed on the same layer or a same layer on one surface or a surface of the base layer BSL, as illustrated in FIGS. 12A and 12B .
  • a process of fabricating the pixel PXL and the display device including the pixel PXL may be simplified. For example, compared to the case where the first and second contact electrodes CET 1 and CET 2 are formed through respective mask processes, the number of mask processes needed to form the pixel PXL may be reduced, and the first and second contact electrodes CET 1 and CET 2 may be more readily formed.
  • the first and second contact electrodes CET 1 and CET 2 may be successively formed on different layers on one surface or a surface of the base layer BSL, as illustrated in FIGS. 12C and 12D .
  • An additional third insulating layer INS 3 may be disposed between the first and second contact electrodes CET 1 and CET 2 .
  • the positions and the relative disposition relationship of the first and second contact electrodes CET 1 and CET 2 may be changed in various ways.
  • first and second contact electrodes CET 1 and CET 2 may be disposed over the first and second sub-electrodes SET 1 and SET 2 to cover or overlap exposed areas (for example, the first and second contact areas CNP 1 and CNP 2 ) of the first and second sub-electrodes SET 1 and SET 2 .
  • the first and second contact electrodes CET 1 and CET 2 may be disposed on at least areas of the first and second sub-electrodes SET 1 and SET 2 to come into contact with the first and second sub-electrodes SET 1 and SET 2 in the first and second contact areas CNP 1 and CNP 2 .
  • first and second contact electrodes CET 1 and CET 2 may be respectively electrically connected to the first and second sub-electrodes SET 1 and SET 2 .
  • the first and second sub-electrodes SET 1 and SET 2 may be respectively electrically connected to the first and second ends EP 1 and EP 2 of the light emitting elements LD through the first and second contact electrodes CET 1 and CET 2 .
  • the first and second contact electrodes CET 1 and CET 2 may be formed of various transparent conductive materials.
  • the first and second contact electrodes CET 1 and CET 2 may include a transparent electrode layer including at least one of various transparent conductive materials including ITO, IZO, and ITZO. Since the first and second contact electrodes CET 1 and CET 2 are formed to be substantially transparent or translucent to satisfy a transmittance, light emitted from the light emitting elements LD through the respective first and second ends EP 1 and EP 2 may be emitted outside the display device after passing through the first and second contact electrodes CET 1 and CET 2 .
  • the second insulating layer INS 2 may be disposed on the first and second contact electrodes CET 1 and CET 2 .
  • the second insulating layer INS 2 may be formed and/or disposed on the overall surface of the display area DA of the base layer BSL on which the partition walls PW, the first and second sub-electrodes SET 1 and SET 2 , the light emitting elements LD, the insulating pattern INP, and the first and second contact electrodes CET 1 and CET 2 are formed.
  • the second insulating layer INS 2 may be formed on the overall surface of the display area DA to cover or overlap the bank BNK that encloses each emission area EMVA, but the disclosure is not limited thereto.
  • the second insulating layer INS 2 may include at least one inorganic layer and/or organic layer.
  • the second insulating layer INS 2 may be formed of a single layer or multiple layers, and include at least one inorganic insulating material and/or organic insulating material.
  • the second insulating layer INS 2 may include various kinds of organic/inorganic insulating materials including silicon nitride (SiNx), silicon oxide (SiOx), etc., within the spirit and the scope of the disclosure.
  • the constituent material of the second insulating layer INS 2 is not particularly limited.
  • the second insulating layer INS 2 may include a thin-film encapsulation layer having a multi-layered structure.
  • the second insulating layer INS 2 may be formed of a thin-film encapsulation layer having a multilayer structure including at least two inorganic insulating layers, and at least one organic insulating layer interposed between the at least two inorganic insulating layers.
  • the constituent material and/or structure of the second insulating layer INS 2 may be changed in various ways.
  • at least one overcoat layer, and/or an encapsulation substrate, etc. may be further disposed over the second insulating layer INS 2 .
  • FIG. 13 is a schematic cross-sectional view illustrating a pixel PXL in accordance with an embodiment and for example illustrates an embodiment of a cross-section of the pixel PXL corresponding to line II-II′ of FIG. 11 .
  • FIG. 13 schematically illustrates a structure of the pixel PXL, focused on the above-described display element layer DPL.
  • like reference numerals will be used to designate components similar or equal to those of the previous embodiments, and detailed explanation thereof will be omitted.
  • light emitting elements LD disposed in different serial stages may be spaced apart from each other with at least two sub-electrodes interposed therebetween.
  • a first light emitting element LD 1 disposed between the first and second sub-electrodes SET 1 [ 1 ] and SET 2 [ 1 ] of the first serial stage may be spaced apart from a second light emitting element LD 2 disposed between the first and second sub-electrodes SET 1 [ 2 ] and SET 2 [ 2 ] of the second serial stage with the second sub-electrodes SET 2 [ 1 ] and SET 2 [ 2 ] of the first and second serial stages that are adjacent to each other interposed therebetween.
  • the first and second ends EP 1 and EP 2 of the first light emitting element LD 1 may be successively disposed with respect to the first direction DR 1 .
  • the first and second ends EP 1 and EP 2 of the second light emitting element LD 2 may be disposed in reverse order with respect to the first direction DR 1 .
  • the first to sixth light emitting elements LD 1 to LD 6 may be arranged or disposed in the first direction DR 1 at intervals corresponding to two sub-electrodes.
  • the light emitting element LD may not be disposed between the first sub-electrodes SET 1 or the second sub-electrodes SET 2 that are adjacent to each other.
  • any light emitting element LD may not be connected between the second sub-electrode SET 2 [ 1 ] of the first serial stage and the second sub-electrode SET 2 [ 2 ] of the second serial stage that are successively disposed in the first direction DR 1 .
  • the first or second sub-electrodes SET 1 or SET 2 that are adjacent to each other may be integrally or non-integrally connected to each other at the step of aligning the light emitting elements LD, and thus be supplied with an identical alignment signal (or alignment voltage).
  • FIGS. 14 and 15 are schematic plan views each illustrating a pixel PXL in accordance with an embodiment, and for example illustrate different embodiments pertaining to the pixel PXL of FIG. 7 .
  • like reference numerals are used to designate components similar or equal to those of at least one above-described embodiment, for example, an embodiment of FIG. 7 , and detailed explanation thereof will be omitted.
  • electrode pairs each including a pair of first and second sub-electrodes SET 1 and SET 2 may be successively arranged or disposed in the first direction DR 1 that is set as the transverse direction of the emission area EMA.
  • Each of the first and second sub-electrodes SET 1 and SET 2 may extend in the second direction DR 2 that is set as the longitudinal direction of the emission area EMA.
  • each of the first and second sub-electrodes SET 1 and SET 2 in accordance with embodiments of FIGS. 14 and 15 may have a length greater than that of each of the first and second sub-electrodes SET 1 and SET 2 in accordance with an embodiment of FIG. 7 .
  • the number of electrode pairs disposed in each of the pixels PXL in accordance with embodiments of FIGS. 14 and 15 may be less than the number of electrode pairs disposed in the pixel PXL in accordance with an embodiment of FIG. 7 .
  • the number of electrode pairs disposed in each pixel PXL in accordance with embodiments of FIGS. 14 and 15 is not particularly limited.
  • the pixel PXL may include three pairs of first and second sub-electrodes SET 1 and SET 2 , or more pairs of first and second sub-electrodes SET 1 and SET 2 .
  • the pixel PXL may include only two pairs of first and second sub-electrodes SET 1 and SET 2 .
  • the pixel PXL may be formed of two or more electrode pairs, and include at least two serial stages.
  • FIGS. 16A to 16D are schematic plan views sequentially illustrating a method of fabricating a display device in accordance with an embodiment and for example illustrate an embodiment of a method of fabricating a display device including the pixel PXL of FIG. 11 .
  • FIGS. 16A to 16D illustrate a plane structure of the pixel PXL, centered on the display element layer DPL in which the light source unit LSU of the pixel PXL is disposed.
  • illustration of the bank BNK which may be formed before or after the first and second sub-electrodes SET 1 and SET 2 are formed, and of which the position and the forming step may be changed in various ways, will be omitted.
  • electrode pairs for constituting the serial stages of the light source unit LSU are formed in each pixel area (by way of example, the emission area EMA of each pixel PXL) on the base layer BSL (or the pixel circuit layer PCL and/or one surface or a surface of the base layer BSL on which the partition walls PW are formed).
  • each pixel area may be an area including an emission area EMA of each pixel PXL, and a peripheral area provided or disposed around a perimeter of the emission area EMA, and may be an area embracing the emission area EMA in which the light source unit LSU of the corresponding pixel PXL is formed, and a pixel circuit area in which the pixel circuit PXC of the pixel PXL is formed. Electrode pairs are formed in the emission area EMA of each of the pixels PXL disposed in the display area DA.
  • the pixels PXL may be formed to have a substantially identical or similar structure.
  • each of electrode pairs formed in the emission area EMA of each pixel PXL may include a pair of first and second sub-electrodes SET 1 and SET 2 .
  • the electrode pairs may be successively arranged or disposed in the first direction DR 1 in each emission area EMA.
  • the first or second sub-electrodes SET 1 or SET 2 of electrode pairs that are successively disposed based on the first direction DR 1 may be successively disposed in the first direction DR 1 .
  • the first or second sub-electrodes SET 1 or SET 2 of the successive electrode pairs may be integrally connected to each other, thus forming each double electrode pattern.
  • the first or second sub-electrodes SET 1 or SET 2 of the successive electrode pairs may be integrally connected to each other on at least one end or an end thereof (for example, on opposite ends thereof), thus forming each double electrode pattern.
  • the second sub-electrode SET 2 [ 1 ] of the first serial stage and the second sub-electrode SET 2 [ 2 ] of the second serial stage may be integrally connected to each other on the opposite ends thereof and thus formed as one double electrode pattern.
  • the first sub-electrode SET 1 [ 2 ] of the second serial stage and the first sub-electrode SET 1 [ 3 ] of the third serial stage may be integrally connected to each other on the opposite ends thereof and thus formed as one double electrode pattern.
  • the first or second sub-electrodes SET 1 or SET 2 of two successive electrode pairs may be formed as each double electrode pattern.
  • each of the sub-electrodes disposed at the first and last positions in each emission area EMA with respect to the first direction DR 1 (for example, the first sub-electrode SET 1 [ 1 ] of the first serial stage and the first sub-electrode SET 1 [ 6 ] of the sixth serial stage) each are formed as a single electrode pattern, and the other sub-electrodes disposed at the intermediate position each are formed as a double electrode pattern, the disclosure is not limited thereto.
  • each of the sub-electrodes disposed at the first and last positions in each emission area EMA may be also formed as a double electrode pattern.
  • each double electrode pattern may be divided later into sub-electrodes.
  • Each of the double electrode patterns disposed at the first and last positions in the first direction DR 1 in the emission area EMA may be divided into a first or last sub-electrode (for example, the first sub-electrode SET 1 [ 1 ] of the first serial stage or the first sub-electrode SET 1 [ 6 ] of the sixth serial stage) and a dummy electrode (for example, a first or second dummy electrode DET 1 or DET 2 of FIG. 9 ).
  • Each of the double electrode patterns disposed at the intermediate position in the emission area EMA may be divided into first or second sub-electrodes SET 1 or SET 2 of two successive serial stages.
  • a first alignment line ALI 1 to be connected in common to the first sub-electrodes SET 1 of the pixels PXL and a second alignment line ALI 2 to be connected in common to the second sub-electrodes SET 2 of the pixels PXL may be formed together.
  • the first sub-electrodes SET 1 of the pixels PXL may be integrally connected to each other through the first alignment line ALI 1 .
  • the second sub-electrodes SET 2 of the pixels PXL may be integrally connected to each other through the second alignment line ALI 2 .
  • the disclosure is not limited thereto.
  • the first sub-electrodes SET 1 of the pixels PXL may be integrally or non-integrally electrically connected to each other.
  • the second sub-electrodes SET 2 of the pixels PXL may be integrally or non-integrally electrically connected to each other.
  • light emitting elements LD may be supplied to and aligned in each pixel area (by way of example, in the emission area EMA of each pixel PXL) including the first and second sub-electrodes SET 1 and SET 2 .
  • light emitting elements LD may be supplied to each emission area EMA by an inkjet scheme, a slit-coating scheme, or other various schemes. Thereafter, the light emitting elements LD may be aligned by respectively supplying a first alignment signal (or a first alignment voltage) and a second alignment signal (or a second alignment voltage) to the first alignment line ALI 1 and the second alignment line ALI 2 .
  • the first and second alignment signals may be respectively supplied to the first and second sub-electrodes SET 1 and SET 2 through the first and second alignment lines ALI 1 and ALI 2 simultaneously with the supply of the light emitting elements LD or after the supply of the light emitting elements LD.
  • a reference potential voltage for example, a ground voltage
  • an alignment signal having an AC waveform may be applied to the second alignment line ALI 2 .
  • the disclosure is not limited thereto.
  • the alignment signal having an AC waveform may be applied to the first alignment line ALI 11
  • the reference potential voltage for example, the ground voltage
  • the type and/or waveform, etc. of the first alignment signal (or the first alignment voltage) and the second alignment signal (or the second alignment voltage) to be respectively supplied to the first alignment line ALI 1 and the second alignment line ALI 2 may be changed in various ways.
  • the light emitting elements LD may be biased-aligned between the first and second sub-electrodes SET 1 and SET 2 by controlling alignment signals or forming a magnetic field.
  • the light emitting elements LD may be biased-aligned such that the first end EP 1 of each light emitting element LD is disposed to face any one first sub-electrode SET 1 , and the second end EP 2 of each light emitting element LD is disposed to face any one second sub-electrode SET 2 that makes a pair with the any one first sub-electrode SET 1 .
  • two first sub-electrodes SET 1 or second sub-electrodes SET 2 that are successively disposed and form each double electrode pattern may be supplied with an identical alignment signal to form an equipotential surface. Therefore, the light emitting element LD may not be disposed between the two first sub-electrodes SET 1 or second sub-electrodes SET 2 that form each double electrode pattern.
  • the first and second sub-electrodes SET 1 and SET 2 may be individually separated from each other through an etching scheme or the like within the spirit and the scope of the disclosure. Furthermore, during this process, the first and second sub-electrodes SET 1 and SET 2 may be respectively separated from the first and second alignment lines ALI 1 and ALI 2 .
  • each double electrode pattern may be separated into the respective first or second sub-electrodes SET 1 and SET 2 .
  • the first and/or second alignment lines ALI 1 and/or ALI 2 may be disconnected between adjacent pixels PXL so that each pixel PXL can be independently driven.
  • connection portions between some or a part of sub-electrodes and the first or second alignment line ALI 1 or ALI 2 may selectively remain, as needed. Consequently, the first and second connection electrodes CNE 1 and CNE 2 and the intermediate connection electrodes CNEi may be formed.
  • the disclosure is not limited thereto.
  • at least one of the first and second connection electrodes CNE 1 and CNE 2 and the intermediate connection electrodes CNEi may be formed separately from the first and second sub-electrodes SET 1 and SET 2 .
  • the first and second contact electrodes CET 1 and CET 2 may be respectively formed on the first and second sub-electrodes SET 1 and SET 2 . Furthermore, in an embodiment, during a process of forming the first and second contact electrodes CET 1 and CET 2 , the first and second sub-electrodes SET 1 and SET 2 of each pixel PXL may be re-connected such that the light emitting elements LD (for example, the first to sixth light emitting elements LD 1 to LD 6 ) aligned between the first and second sub-electrodes SET 1 and SET 2 of each serial stage are connected in the forward direction between the first and second sub-electrodes SET 1 and SET 2 .
  • the second sub-electrodes SET 2 of the electrode pairs other than the last electrode pair may be electrically connected to the first sub-electrode SET 1 of a subsequent electrode pair.
  • the second sub-electrode SET 2 [ 1 ] of the first serial stage connected to the second end EP 2 of the first light emitting element LD 1 may be electrically connected to the first sub-electrode SET 1 [ 2 ] of the second serial stage connected to the first end EP 1 of the second light emitting element LD 2 .
  • the first and second sub-electrodes SET 1 and SET 2 are re-connected, whereby the light source unit LSU having a serial/parallel combination structure including serial stags may be formed.

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