US20210057461A1 - Electronic device and method for manufacturing the same - Google Patents

Electronic device and method for manufacturing the same Download PDF

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Publication number
US20210057461A1
US20210057461A1 US16/941,880 US202016941880A US2021057461A1 US 20210057461 A1 US20210057461 A1 US 20210057461A1 US 202016941880 A US202016941880 A US 202016941880A US 2021057461 A1 US2021057461 A1 US 2021057461A1
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Prior art keywords
layer
conductive pattern
electronic device
flexible layer
flexible
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US16/941,880
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English (en)
Inventor
Yu-Chia Huang
Kuan-Feng LEE
Tsung-Han Tsai
Chu-Hong Lai
Yu-Chih Tseng
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Innolux Corp
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Innolux Corp
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Assigned to Innolux Corporation reassignment Innolux Corporation ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HUANG, YU-CHIA, LAI, CHU-HONG, LEE, KUAN-FENG, TSAI, TSUNG-HAN, TSENG, YU-CHIH
Publication of US20210057461A1 publication Critical patent/US20210057461A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133305—Flexible substrates, e.g. plastics, organic film
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1218—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or structure of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1262—Multistep manufacturing methods with a particular formation, treatment or coating of the substrate
    • H01L51/0097—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/60—Forming conductive regions or layers, e.g. electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/80—Manufacture or treatment specially adapted for the organic devices covered by this subclass using temporary substrates
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the disclosure relates to an electronic device and a manufacturing method of the same, and it particularly relates to an electronic device having a conductive pattern and a manufacturing method of the same.
  • Electronic devices may include a conductive pattern having multiple functions. Since the current technology used in the formation of such a conductive pattern limits the applications for electronic devices, the industry still needs a new manufacturing method to form an electronic device having a conductive pattern.
  • Some embodiments of the present disclosure provide a manufacturing method of an electronic device.
  • the method includes providing a dummy substrate.
  • the method includes forming a conductive pattern on the dummy substrate.
  • the method includes forming a flexible layer to cover the conductive pattern. Additionally, the method includes forming a circuit layer on the flexible layer.
  • the method includes removing the dummy substrate.
  • the electronic device includes a flexible layer having a first surface and a second surface opposed to the first surface.
  • the electronic device includes a circuit layer on the first surface of the flexible layer.
  • the electronic device includes a conductive pattern, wherein the flexible layer is between the circuit layer and the conductive pattern.
  • FIGS. 1A-1G illustrate cross-sectional views showing a manufacturing method of an electronic device according to some embodiments of the present disclosure.
  • FIGS. 2A-2C illustrate cross-sectional views showing a manufacturing method of an electronic device according to some embodiments of the present disclosure.
  • FIGS. 3A-3C illustrate cross-sectional views showing a manufacturing method of an electronic device according to some embodiments of the present disclosure.
  • FIGS. 4A-4D illustrate cross-sectional views showing a manufacturing method of an electronic device according to some embodiments of the present disclosure.
  • FIGS. 5A-5B illustrate cross-sectional views showing two stages of a manufacturing method of an electronic device according to some embodiments of the present disclosure.
  • FIGS. 6A-6B illustrate cross-sectional views of an electronic device according to some embodiments of the present disclosure.
  • FIG. 7 illustrates a three-dimensional view of a conductive pattern according to some embodiments of the present disclosure.
  • FIG. 8 illustrates a cross-sectional view of an electronic device according to some embodiments of the present disclosure.
  • FIG. 9 illustrates a cross-sectional view of an electronic device according to some embodiments of the present disclosure.
  • FIG. 10 illustrates a cross-sectional view of an electronic device according to some embodiments of the present disclosure.
  • FIG. 11 illustrates a cross-sectional view of an electronic device according to some embodiments of the present disclosure.
  • FIG. 12 illustrates a cross-sectional view of an electronic device according to some embodiments of the present disclosure.
  • FIG. 13 illustrates a cross-sectional view of an electronic device according to some embodiments of the present disclosure.
  • FIG. 14 illustrates a top view of a conductive pattern according to some embodiments of the present disclosure.
  • FIGS. 15A-15C illustrate top views of a conductive pattern according to some embodiments of the present disclosure.
  • FIG. 16 illustrates a cross-sectional view of an electronic device according to some embodiments of the present disclosure.
  • FIG. 17 illustrates a cross-sectional view of an electronic device according to some embodiments of the present disclosure.
  • FIG. 18 illustrates a cross-sectional view of an electronic device according to some embodiments of the present disclosure.
  • the terms “about”, “around” and “substantially” typically mean +/ ⁇ 20% of the stated value or range, typically +/ ⁇ 10% of the stated value or range, typically +/ ⁇ 5% of the stated value or range, typically +/ ⁇ 3% of the stated value or range, typically +/ ⁇ 2% of the stated value or range, typically +/ ⁇ 1% of the stated value or range, and typically +/ ⁇ 0.5% of the stated value or range.
  • the stated number of the present disclosure is an approximate number. Namely, the meaning of “about”, “around” and “substantially” may be implied if there is no specific description of “about”, “around” and “substantially”.
  • first”, “second”, “third” etc. may be used herein to describe various elements, components, regions, layers, and/or portions, these elements, components, regions, layers, and/or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, and/or portion from another element, component, region, layer and/or portion. Thus, a first element, component, region, layer, or portion discussed below could be termed a second element, component, region, layer, or portion without departing from the teachings of the present disclosure.
  • relative terms such as “lower,” “upper,” “horizontal,” “vertical”, “below”, “above”, “top” and “bottom” should be construed to refer to the orientation as described in the paragraph or as shown in the drawing under discussion. These relative terms are only for convenience of description and do not require that the apparatus be constructed or operated in a particular orientation. Terms concerning attachments, coupling and the like, such as “connected” and “interconnected,” refer to a relationship wherein structures are secured or attached to one another either directly or indirectly through intervening structures, as well as both movable or rigid attachments or relationships, unless expressly described otherwise.
  • substrate or “panel” hereinafter may include elements formed on the substrate (such as transistor elements or circuits) and the layers overlaying the substrate, but in order to simplify the drawings here, a flat substrate is shown.
  • the electronic device may include a display device, an illumination device, an antenna device, a sensing device, a splicing device, other suitable devices, or a combination thereof, but is not limited thereto.
  • the electronic device can be a bendable or flexible device.
  • the term “flexible electronic device” as mentioned in some embodiments of the present disclosure means that the electronic device can be bent, folded, curled, flexed or the like along at least one bending axis, but is not limited thereto. According to some embodiments, the device may also be bent separately along more than two bending axes.
  • FIGS. 1A-1F illustrate cross-sectional views of a manufacturing method of an electronic device according to some embodiments of the present disclosure.
  • a dummy substrate 110 is provided.
  • the dummy substrate 110 is disposed to temporarily carry the elements formed thereon and will be removed in subsequent processes.
  • the dummy substrate 110 can be a rigid substrate.
  • the dummy substrate 110 may include glass, sapphire, ceramic, or other suitable materials, but is not limited thereto.
  • the peeling layer 120 and the protection layer 130 are sequentially formed on the dummy substrate 110 .
  • the material of the peeling layer 120 may include a metal such as chromium, nickel, cobalt or molybdenum; a metal oxide such as chromium oxide, nickel oxide, chromium phosphate or nickel phosphate; and an organic compound such as benzotriazole, a derivative thereof or a combination thereof, but is not limited thereto.
  • the peeling layer 120 can provide sufficient adhesion to reduce the peeling of the protection layer 130 from the dummy substrate 110 and can be easily peeled off from the protection layer 130 .
  • the protection layer 130 includes silicon nitride, silicon oxide, silicon oxynitride or other suitable materials, but is not limited thereto.
  • the protection layer 130 is disposed to protect a conductive pattern that is formed subsequently, and reduces the effect of an external force on the conductive pattern.
  • the peeling layer 120 and/or the protection layer 130 can be selectively formed. In some embodiments, the peeling layer 120 and/or the protection layer 130 are not formed.
  • a conductive pattern 140 is formed on the protection layer 130 .
  • the conductive pattern 140 includes a conductive material such as copper (Cu), nickel (Ni), gold (Au), titanium (Ti), aluminum (Al), chromium (Cr), palladium (Pt), silver (Ag), aluminum (Al), other metal materials, an alloy thereof or a combination thereof, but is not limited thereto.
  • the conductive pattern 140 can perform a variety of functions (e.g. at least one of the functions of a light polarizing element, an antenna element, a touch sensing element and a fingerprint sensing element).
  • the conductive pattern 140 can be at least one of a light polarizing element, an antenna element, a touch sensing element, and a fingerprint sensing element.
  • the conductive pattern 140 can serve as a wire grid polarizer (WGP).
  • WGP wire grid polarizer
  • the conductive pattern 140 may let light having a first polarization direction (such as a p-wave) through and may reflect light having a second polarization direction (such as an s-wave) perpendicular to the first polarization direction.
  • the conductive pattern 140 may be formed of a plurality of long strips of metal wires 142 , but is not limited thereto.
  • the conductive pattern 140 may be formed by a Nanoimprint Lithography (NIL), an inkjet printing technique, a micro electro mechanical system or the like, but is not limited thereto.
  • the process of the Nanoimprint Lithography includes disposing a metal material on the protection layer 130 ; forming a photoresist on the metal material; using a patterned imprinter to imprint the photoresist to pattern the photoresist; and etching the metal material by the patterned photoresist to form a conductive pattern.
  • a liquid polymer layer 150 ′ is disposed on the protection layer 130 and the conductive pattern 140 and covers the conductive pattern 140 .
  • the polymer layer 150 ′ can fill the space between two adjacent metal lines 142 .
  • the upper surface of the polymer layer 150 ′ is not flat.
  • the material of the polymer layer 150 ′ may include polyimide (PI), polyethylene terephthalate (PET), polycarbonate (PC), polyether sulfones (PES), polybutylene terephthalate (PBT), polyethylene naphthalate (PEN) or polyarylate (PAR), other suitable materials or a combination thereof, but is not limited thereto.
  • PI polyimide
  • PET polyethylene terephthalate
  • PC polycarbonate
  • PES polyether sulfones
  • PBT polybutylene terephthalate
  • PEN polyethylene naphthalate
  • PAR polyarylate
  • a curing process 160 is performed to cure the polymer layer 150 ′ to form a flexible layer 150 covering the conductive pattern 140 .
  • the curing process 160 includes irradiation of ultraviolet rays, heating, other methods, or a combination thereof, but is not limited thereto.
  • the conductive pattern 140 is embedded within the flexible layer 150 .
  • the flexible layer 150 has a first surface S 1 and a second surface S 2 opposite thereto.
  • the second surface S 2 may be adjacent to the protection layer 130 .
  • the conductive pattern 140 is embedded into the flexible layer 150 from the second surface S 2 . In other words, the conductive pattern 140 is disposed between the flexible layer 150 and the protection layer 130 .
  • a planarization process can be performed. Since a portion of the flexible layer 150 is formed on the conductive pattern 140 and a portion of the flexible layer 150 is formed over the protective layer 130 , the surface of the flexible layer 150 is uneven The first surface S 1 of the flexible layer 150 can be made a flatter surface by a planarization process.
  • circuit layer 170 is formed on the first surface S 1 of the flexible layer 150 .
  • circuit layer 170 includes a plurality of active elements and/or passive elements.
  • the active elements may include a thin film transistor.
  • the thin film transistors may include a switching transistor, a driver transistor, a reset transistor, or other thin film transistors.
  • the passive elements may include capacitors, inductors, or other passive elements, but are not limited thereto.
  • the active elements of the circuit layer 170 can be electrically connected to the conductive pattern 140 .
  • the active elements of the circuit layer 170 are not electrically connected to the conductive pattern 140 . As shown in FIG.
  • the dummy substrate 110 and the peeling layer 120 are removed to form the electronic device 10 A.
  • the dummy substrate 110 and the peeling layer 120 may be removed by a laser lift off (LLF) process or other suitable processes.
  • the electronic device 10 A includes the conductive pattern 140 that can serve as a wire grid polarizer, and the conductive pattern 140 is embedded in the bendable flexible layer 150 . Thereby, the conductive pattern 140 can be applied to the flexible electronic device 10 A.
  • the conductive pattern 140 that uses a metal material is formed on a flexible substrate by a Nanoimprint Lithography technology, there may be a problem that the metal material is not easily formed.
  • the rigid dummy substrate 110 is provided first, the conductive pattern 140 is formed thereon, and the flexible layer 150 is formed on the conductive pattern 140 , thereby reducing the problems caused by using the Nanoimprint Lithography to form the conductive pattern 140 directly on a flexible substrate.
  • an interlayer 180 may be disposed on the structure shown in FIG. 1C described above to form a structure as shown in FIG. 2A .
  • the material of the interlayer 180 may include a fluid material such as an organic layer and/or an inorganic layer, but is not limited thereto.
  • the interlayer 180 may be formed by processes including a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, a spin coating process, a Sol-Gel process, or other suitable processes, but not limited thereto.
  • the interlayer 180 can be conformally formed on the conductive pattern 140 and fills the space between the two adjacent metal lines 142 .
  • the interlayer 180 covers the upper surface and side surfaces of the metal lines 142 .
  • the flexible layer 150 is formed on the interlayer 180 and the conductive pattern 140 .
  • the process of forming the flexible layer 150 may be the same as or similar to the processes as shown in FIGS. 1D to 1E , and the details are not described herein again.
  • the flexible layer 150 can fill the space between the two adjacent metal wires 142 . It should be noted that the “to fill the space between . . . adjacent . . . ” mentioned in some embodiments of the present disclosure may refer to the case where the space is completely filled or the space is partially filled.
  • the circuit layer 170 is formed on the flexible layer 150 , and the dummy substrate 110 and the peeling layer 120 are removed to form the electronic device 10 B.
  • the foregoing processes may be the same as or similar to the processes as shown in FIGS. 1F-1G , and the details are not described herein again.
  • the formation of the interlayer 180 with a better fluidity on the conductive pattern 140 allows the polymer layer 150 ′ having a larger viscosity coefficient to more easily fill the space between the two adjacent metal lines 142 , reducing the probability of the flexible layer 150 being peeled off from the conductive pattern 140 .
  • an etching process 190 can be performed on the structure as shown in FIG. 2A above, to remove a portion of the interlayer 180 to form the interlayer 180 ′.
  • the interlayer 180 ′ does not cover the upper surface of the conductive pattern 140 , but covering at least a portion of the side surface of the conductive pattern 140 and at least a portion of the upper surface of the protection layer 130 .
  • the interlayer 180 ′ covers at least a portion of the side surface of the conductive pattern 140 .
  • the interlayer 180 ′ covers at least a portion of the upper surface of the protection layer 130 , but is not limited thereto.
  • the flexible layer 150 is formed on the interlayer 180 ′ and the conductive pattern 140 .
  • the processes of forming the flexible layer 150 may be the same as or similar to the processes as shown in FIGS. 1D to 1E , and the details are not described herein again.
  • the flexible layer 150 can fill the space between the two adjacent metal wires 142 .
  • the circuit layer 170 is formed on the flexible layer 150 , and the dummy substrate 110 and the peeling layer 120 are removed to form the electronic device 10 C.
  • the foregoing processes may be the same as or similar to the processes shown in FIGS. 1F-1G , and the details are not described herein again.
  • forming the interlayer 180 ′ with a better fluidity on the conductive pattern 140 allows the polymer layer 150 ′ having a larger viscosity coefficient to more easily fill the space between the two adjacent metal lines 142 , reducing the probability of the flexible layer 150 being peeled off from the conductive pattern 140 .
  • FIGS. 4A-4D illustrate cross-sectional views showing a manufacturing method of an electronic device 10 D according to some embodiments of the present disclosure.
  • a liquid polymer layer 200 ′ may be formed on the peeling layer 120 in place of the protection layer 130 .
  • the material and processes of polymer layer 200 ′ may be the same as or similar to those of the polymer layer 150 ′.
  • the material and processes of polymer layer 200 ′ may be different from those of the polymer layer 150 ′, but is not limited thereto. As shown in FIG.
  • a curing process is performed to cure the polymer layer 200 ′ to form a flexible layer 200 .
  • the curing process may include irradiation of ultraviolet rays, heating, other methods, or a combination thereof, but is not limited thereto.
  • the flexible layer 200 has a thickness T 1 , which may be the maximum thickness of the flexible layer 200 in the normal direction. In some embodiments, the thickness T 1 ranges between about 3 ⁇ m (micrometers) to 5 ⁇ m (3 ⁇ m ⁇ thickness T 1 ⁇ 5 ⁇ m).
  • the conductive pattern 140 is formed on the flexible layer 200 .
  • the flexible layer 150 and the circuit layer 170 are formed, and the dummy substrate 110 and the peeling layer 120 are removed to form the electronic device 10 D.
  • the foregoing processes may be the same as or similar to the processes as shown in FIGS. 1D-1G , and the details are not described herein again.
  • the flexible layer 150 has a thickness T 2 which may be the maximum thickness of the flexible layer 150 in the normal direction. In some embodiments, the thickness T 2 ranges between about 15 ⁇ m to 20 ⁇ m (15 ⁇ m ⁇ thickness T 2 ⁇ 20 ⁇ m). In some embodiments, the thickness T 1 is less than the thickness T 2 .
  • the conductive pattern 140 can be formed on the flexible layer 200 by a Nanoimprint Lithography, which can reduce the problem that the metal material cannot be formed on the flexible substrate.
  • replacing the protection layer 130 with the flexible layer 200 can enhance the ability of the electronic device 10 D to flex.
  • FIGS. 5A-5B illustrate cross-sectional views showing a manufacturing method of an electronic device 10 E according to some embodiments of the present disclosure.
  • a medium layer 210 and an another substrate 220 may be formed on the circuit layer 170 .
  • the medium layer 210 may be a liquid-crystal layer, and the liquid-crystal molecules included in the medium layer 210 may be arranged in a nematic, smectic, or cholesteric manner, but the present disclosure is not limited to thereto.
  • the medium layer 210 can be sealed between the circuit layer 170 and the another substrate 220 .
  • the medium layer 210 may include a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot (QD), a fluorescence, a phosphor, other suitable materials or a combination thereof, but is not limited thereto.
  • the light-emitting diode may include, for example, a sub-millimeter light-emitting diode (mini LED), a micro light-emitting diode (micro LED) or a quantum dot light-emitting diode (QLED, QDLED), a fluorescence, a phosphor, other suitable materials or a combination thereof, but is not limited to them.
  • some layers or structures may be added or removed depending on the type of the media layer that is selected, which will not be described herein.
  • the another substrate 220 may contain various active elements and/or passive elements depending on the use of the electronic device.
  • the active elements may include a thin film transistor or other elements.
  • the thin film transistors may include a switching transistor, a driver transistor, a reset transistor, or other thin film transistors.
  • the passive elements include capacitors, inductors, or other passive elements, but are not limited thereto.
  • the flexible layer 150 may have a curved shape and the another substrate 220 may have the same or similar shape as the flexible layer 150 does.
  • the dummy substrate 110 and the peeling layer 120 are removed to form the electronic device 10 E.
  • the dummy substrate 110 and the peeling layer 120 may be removed by a laser lift-off process or other suitable processes.
  • the dummy substrate 110 and the peeling layer 120 may be removed before the medium layer 210 and/or the another substrate 220 are disposed, but the present disclosure is not limited thereto.
  • the electronic device 10 E since the electronic device 10 E includes the medium layer 210 , the electronic device 10 E can serve as a display device.
  • replacing the polarizing plate made of polyimide with the conductive pattern 140 can reduce the thickness of the electronic device and also reduce manufacturing time and cost.
  • the another substrate 220 of the electronic device 10 F may further include a circuit layer 230 , a flexible layer 240 , and a conductive pattern 250 .
  • the circuit layer 230 is disposed on the medium layer 210
  • the flexible layer 240 is disposed on the circuit layer 230 .
  • the conductive pattern 250 can be embedded within the flexible layer 240 .
  • the conductive pattern 140 and the conductive pattern 250 may be embedded in the flexible layer 150 and the flexible layer 240 , respectively.
  • the circuit layer 230 may include a plurality of active elements and/or passive elements.
  • the active elements include a thin film transistor.
  • the thin film transistors may include a switching transistor, a driver transistor, a reset transistor, or other thin film transistors.
  • the passive elements include capacitors, inductors, or other passive elements, but are not limited thereto.
  • the circuit layer 170 and the circuit layer 230 may include a plurality of active elements and/or passive elements.
  • the active elements include a thin film transistor.
  • the thin film transistors may include a switching transistor, a driver transistor, a reset transistor, or other thin film transistors.
  • the passive elements include capacitors, inductors, or other passive elements, but are not limited thereto. In some embodiments, as shown in FIG.
  • the electronic device 10 F includes a display area DA and a non-display area NDA
  • the circuit layer 170 and/or the circuit layer 230 includes a switching transistor corresponding to the display area DA, but is not limited thereto.
  • the circuit layer 170 and/or the circuit layer 230 includes a driver transistor corresponding to the non-display area NDA, but is not limited thereto.
  • the circuit layer 170 and/or the circuit layer 230 includes a switching transistor corresponding to the display area DA and a driver transistor corresponding to the non-display area NDA as well, but is not limited thereto.
  • the conductive pattern 140 and/or the conductive pattern 250 has a light-penetrable region corresponding to the display area DA of the circuit layer 170 and/or the circuit layer 230 , and is not limited thereto.
  • the conductive pattern 140 and/or the conductive pattern 250 includes a first shielding layer SL 1 and/or a fourth shielding layer SL 4 which are areas that can reflect light and/or shield light corresponding to the non-display area NDA of the circuit layer 170 and/or the circuit layer 230 , but is not limited thereto.
  • the non-display area NDA of the circuit layer 170 and/or the circuit layer 230 includes a second shielding layer SL 2 and/or a third shielding layer SL 3 which are areas that can reflect light and/or shield light, but is not limited thereto.
  • the electronic device 10 F includes a single layer of a shielding layer, such as the first shielding layer SL 1 , the second shielding layer SL 2 , the third shielding layer SL 3 , or the fourth shielding layer SL 4 , but is not limited thereto.
  • the electronic device 10 F includes a plurality of layers of shielding layers, such as any combination of the first shielding layer SL 1 , the second shielding layer SL 2 , the third shielding layer SL 3 , or the fourth shielding layer SL 4 .
  • the flexible layer 240 includes a flexible material.
  • the material and formation method of the flexible layer 240 may be the same as or similar to those of the flexible layer 150 , which will not be repeated herein.
  • the material and formation method of the flexible layer 240 can be different from those of the flexible layer 150 .
  • the conductive pattern 250 may be a conductive material.
  • the conductive pattern 250 may include at least one of a light polarizing element, an antenna element, a touch sensing element, and a fingerprint sensing element or other sensing elements. In some embodiments, the conductive pattern 250 can serve as a wire grid polarizer. In some embodiments, the conductive pattern 250 may be formed by a Nanoimprint Lithography, an inkjet printing technique, a Micro Electro Mechanical Systems, or the like, but is not limited thereto. In some embodiments, the material and formation method of the conductive pattern 250 may be the same as or different from those of the conductive pattern 140 . In some embodiments, the material and formation method of circuit layer 230 may be the same or different from those of the circuit layer 170 .
  • the conductive pattern 140 includes a plurality of metal lines 142 extending in a first direction, for example, extending in the X direction.
  • the conductive pattern 250 includes a plurality of metal lines 252 extending in a second direction, for example, extending in the Y direction.
  • the formed angle may be between 80° and 100° (80° ⁇ angle ⁇ 100°).
  • the electronic device 10 F can serve as a normally black type electronic device.
  • the conductive pattern 140 may be disposed on the upper substrate and the lower substrate of the electronic device 10 F.
  • the upper substrate and the lower substrate may be defined by a distance from a viewer. For example, the viewer is closer to the substrate and farther from the lower substrate.
  • the upper substrate and the lower substrate may also be defined by their distances from the backlight module. For example, the backlight module is farther from the upper substrate and closer to the lower substrate.
  • the lower substrate may include the conductive pattern 140 , the flexible layer 150 and the circuit layer 170 .
  • the upper substrate may include the conductive pattern 250 , the flexible layer 240 and the circuit layer 230 .
  • FIG. 8 illustrates a cross-sectional view of an electronic device 10 G according to some embodiments of the present disclosure.
  • the electronic device 10 G includes a backlight module 260 .
  • the backlight module 260 may be disposed on the second surface S 2 of the flexible layer 150 .
  • the backlight module 260 can be a direct back-light or an edge LED back-light.
  • the backlight module 260 may include a light-emitting diode, an organic light-emitting diode, a quantum dot, a fluorescence, a phosphor, other suitable materials, or a combination thereof, but is not limited thereto.
  • the light-emitting diode may include, for example, a sub-millimeter light-emitting diode, a micro light-emitting diode, a quantum dot light-emitting diode, a fluorescence, a phosphor, other suitable materials or a combination thereof, but is not limited to them.
  • the light-emitting diode may include a semiconductor layer and a light-emitting layer.
  • the semiconductor layer may be doped In x Al y Ga (1-x-y) N, where 0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1 and 0 ⁇ (x+y) ⁇ 1, such as doped GaN, InN, AlN, In x Ga (1-x) N, Al x In y Ga (1-x-y) N or the like, where 0 ⁇ x ⁇ 1, 0 ⁇ y ⁇ 1 and 0 ⁇ (x+y) ⁇ 1.
  • the light-emitting layer may include a homojunction, a heterojunction, a single-quantum well (SQW), a multiple-quantum well (MQW) or the like.
  • the light-emitting layer may include other commonly used materials, such as Al x In y Ga (1-x-y) N, but the disclosure is not limited thereto.
  • the backlight module 260 may include an organic light-emitting diode.
  • the organic light-emitting diode may include an upper electrode, a lower electrode, and an organic light-emitting layer disposed between the upper electrode and the lower electrode.
  • the organic light-emitting layer may include an organic film.
  • the backlight module 260 may also include a light-guiding plate, a reflection layer, a diffusion plate or other elements, but is not limited thereto.
  • FIG. 9 illustrates a cross-sectional view of an electronic device 10 H according to some embodiments of the present disclosure.
  • the electronic device 10 H includes a polarizer 270 disposed on the flexible layer 240 .
  • the another substrate 220 includes the polarizer 270 in place of the conductive pattern 250 .
  • the polarizer 270 may include polyimide or other suitable material.
  • the electronic device 10 I includes the backlight module 260 .
  • the backlight module 260 may be disposed on the second surface S 2 of the flexible layer 150 .
  • the conductive pattern 140 may be disposed at the lower substrate, and the polarizer 270 may be disposed at the upper substrate.
  • the backlight module 260 may be disposed adjacent to the conductive pattern 140 and away from the polarizer 270 .
  • FIG. 11 illustrates a cross-sectional view of an electronic device 10 J according to some embodiments of the present disclosure.
  • the conductive pattern 140 of the electronic device 10 J is disposed at the upper substrate of the electronic device 10 J, and the polarizer 270 is disposed at the lower substrate.
  • the conductive pattern 140 may be disposed at the upper substrate of the electronic device or the lower substrate of the electronic device, or both.
  • FIG. 12 illustrates a cross-sectional view of an electronic device 10 K according to some embodiments of the present disclosure.
  • the electronic device 10 K includes the backlight module 260 .
  • the backlight module 260 can be disposed away from the conductive pattern 140 and adjacent to the polarizer 270 .
  • the electronic device 10 L includes a phase difference layer 280 disposed on the first surface S 1 of the flexible layer 150 .
  • the phase difference layer 280 may include a ⁇ /4 plate or a ⁇ /2 plate ( ⁇ is the wavelength of light).
  • the phase difference layer 280 may cause a phase difference, and the phase difference may be formed of a birefringence material such as a liquid-crystal material, a resin material, or the like.
  • the electronic device 10 L includes a light-emitting layer 290 disposed on the phase difference layer 280 .
  • the light-emitting layer 290 includes an organic light-emitting diode or other suitable light-emitting elements.
  • the light-emitting layer 290 may include an upper electrode, a lower electrode, and an organic light-emitting layer (not shown) disposed between the upper electrode and the lower electrode.
  • the electronic device 10 L includes a reflection layer 300 .
  • the reflection layer 300 can be used to reflect the light emitted by the light-emitting layer 290 .
  • the material of the reflection layer 300 may include a metal, such as molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), silver (Ag), tungsten (W), gold (Au), chromium (Cr), nickel (Ni), platinum (Pt), iridium (Ir), rhodium (Rh), indium (In), bismuth (Bi), an alloy thereof, but is not limited thereto.
  • the electronic device 10 L includes a substrate 310 that may be disposed on the second surface S 2 of the flexible layer 150 .
  • the substrate 310 may include a plurality of active and/or passive elements.
  • the light-emitting layer 290 can be used as a light-emitting source such that the electronic device 10 L can serve as a display device.
  • FIG. 14 illustrates a top view of the conductive pattern 140 and the conductive pattern 250 according to some embodiments of the present disclosure.
  • the angle formed by the extending direction of the metal line 142 (shown by a dashed line) of the conductive pattern 140 and the extending direction of the metal line 252 (shown by a solid line) of the conductive pattern 250 in the flexible layer 240 (or the flexible layer 150 ) is an angle ⁇ .
  • the angle ⁇ can be between 0° and 10° (0° ⁇ 0 ⁇ 10°).
  • FIGS. 15A-15C illustrate different aspects of the conductive pattern 140 according to some embodiments of the present disclosure.
  • the layout of the conductive pattern 140 can be designed as different shapes depending on the use of the electronic device.
  • the conductive pattern 140 includes a plurality of metal lines 142 , which may extend in the same direction.
  • the conductive pattern 140 includes a metal line 142 a and a metal line 142 b , and the metal line 142 a and the metal line 142 b may extend in the same direction.
  • the metal line 142 a may have a width W 1
  • the metal line 142 b may have a width W 2 , wherein the width W 1 refers to the maximum width in a direction perpendicular to the extending direction of the metal line 142 a
  • the width W 2 refers to the maximum width in a direction perpendicular to the extending direction of the metal line 142 b .
  • the width W 1 or the width W 2 may be defined depending on a partial line segment. After defining the extending direction of the partial line segment, the maximum width of the partial line segment is measured in a direction perpendicular to the extending direction. In some embodiments, the width W 1 is greater than the width W 2 .
  • the width W 1 may be between 5 um and 50 um (5 um ⁇ width W 1 ⁇ 50 um).
  • the width W 2 may be between 10 um and 1000 um (10 um ⁇ width W 2 ⁇ 1000 um), or the width W 2 may be between 10 nm and 100 nm (10 um ⁇ width W 2 ⁇ 100 um), or the width W 2 may be between 1 um and 100 um (1 um ⁇ width W 2 ⁇ 100 um), but not limited thereto. In some embodiments, there may be a distance D 2 between the two adjacent metal lines 142 b , wherein the distance D 2 refers to the minimum distance between two adjacent metal lines 142 b .
  • the distance D 2 may be in a range of 1 um to 1000 um (1 um ⁇ distance D 2 ⁇ 1000 um), or the distance D 2 may be in a range of 100 um to 1000 um (100 um ⁇ distance D 2 ⁇ 1000 um), or distance D 2 may be in a range of 50 nm to 200 nm (50 nm ⁇ distance D 2 ⁇ 200 nm), but is not limited thereto.
  • the metal line 142 may have a spiral shape, and the spiral shape may be a clockwise direction and/or a counterclockwise direction, and the disclosure is not limited thereto.
  • the conductive pattern 140 may have various layouts.
  • the conductive pattern 140 has the layout shown in FIG. 15A ; in the second region of the display device, the conductive pattern 140 has the layout shown in FIG. 15B .
  • the metal lines 142 of the conductive pattern 140 may have various extending directions.
  • the metal lines 142 may have different extending directions, but are not limited thereto.
  • FIG. 16 illustrates a cross-sectional view of an electronic device 10 M according to some embodiments of the present disclosure.
  • the electronic device 10 M includes a chip 320 , which may be disposed on a portion of the first surface S 1 of the flexible layer 150 that is not covered by the circuit layer 170 .
  • a plurality of thin film transistors 330 may be formed in the circuit layer 170 and separated by an insulation layer 340 , but are not limited thereto.
  • the thin film transistor 330 includes a gate 332 , a semiconductor layer 334 , and a source/drain 336 .
  • the gate 332 may include a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), gold (Au), chromium (Cr), nickel (Ni), palladium (Pt), titanium (Ti), but is not limited thereto.
  • the semiconductor layer 334 may be amorphous silicon, polysilicon, low temperature polysilicon, metal oxide or other materials.
  • the metal oxide includes indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), or indium gallium zinc tin oxide (IGZTO), but is not limited thereto.
  • the electronic device 10 M may include the thin film transistor 330 having the foregoing different semiconductor layers 334 .
  • some of the thin film transistors 330 include a semiconductor layer 334 of indium gallium zinc oxide, and some of the thin film transistors 330 include a semiconductor layer of low temperature polysilicon 334 , but are not limited thereto.
  • the material of the source/drain 336 may be the same as or similar to that of the gate 332 and will not be repeated herein.
  • the insulation layer 340 may include silicon oxide, silicon nitride, silicon oxynitride, but is not limited thereto.
  • the thin film transistor 330 can be formed by a deposition process, a lithography process, and an etching process.
  • the deposition process includes, but is not limited to, a physical vapor deposition process, a chemical vapor deposition process, and an atomic layer deposition process.
  • the lithography process includes photoresist coating (e.g., spin-coating), soft baking, photomask alignment, exposure, post-exposure baking, developing a photoresist, rinsing, drying (e.g., hard baking), other suitable processes, or a combination thereof.
  • the lithography process can be performed or replaced by other suitable methods, such as maskless lithography, electron-beam writing, and ion-beam writing.
  • the etching process includes dry etching, wet etching, or other etching methods, and is not limited thereto.
  • the conductive pattern 140 may include a metal line 142 c and a metal line 142 d .
  • the metal line 142 c and the metal line 142 d may have different widths.
  • the metal line 142 c may be disposed under the thin film transistor 330 as a light-shielding layer to reduce light irradiating the semiconductor layer 334 .
  • the metal line 142 d may be electrically connected to the thin film transistor 330 via a wire 350 .
  • FIG. 17 illustrates a cross-sectional view of an electronic device 10 N according to some embodiments of the present disclosure.
  • the electronic device 10 N includes a plurality of chips 320 disposed on the first surface S 1 of the flexible layer 150 ; and at least one chip 320 may be electrically connected to the conductive pattern 140 via wires 360 disposed in the flexible layer 150 .
  • FIG. 18 illustrates a cross-sectional view of an electronic device 10 O according to some embodiments of the present disclosure.
  • the chip 320 of the electronic device 10 O may be disposed on the second surface S 2 of the flexible layer 150 and electrically connected to the conductive pattern 140 via a wire 370 disposed in the protection layer 130 .
  • a conductive pattern is first disposed on a dummy substrate, and then a flexible layer and a circuit layer are formed to form an electronic device.
  • the foregoing method may form a conductive pattern on a flexible substrate by a Nanoimprint Lithography.
  • the flexible layer can be bent and the chip is disposed on the surface of the flexible layer.
  • the electronic device may have a medium layer that can be sealed between the flexible layer and the another substrate.
  • the another substrate may also have a flexible layer and a conductive pattern.
  • the conductive pattern may be disposed at the upper substrate of the electronic device, the lower substrate of the electronic device, or both.
  • the conductive pattern may have different layouts and/or shapes and may serve as a light polarizing element, an antenna element, a touch sensing element, and/or a fingerprint sensing element. In some embodiments, the conductive pattern is embedded into the flexible layer.
  • the thickness can be measured using an optical microscopy (OM), scanning electron microscope (SEM), a film thickness profiler ( ⁇ -step), an elliptical thickness gauge, or other suitable method.
  • OM optical microscopy
  • SEM scanning electron microscope
  • ⁇ -step film thickness profiler
  • elliptical thickness gauge or other suitable method.
  • a cross-sectional image of the structure is taken using a scanning electron optical microscope, and the maximum thickness in the cross-sectional image is measured.
  • the maximum thickness described above may be the maximum thickness in any of the cross-sectional images. In other words, it may be the maximum thickness in a partial region of the liquid-crystal device.

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CN115128860A (zh) * 2021-03-29 2022-09-30 瀚宇彩晶股份有限公司 可挠式显示面板的制造方法
TWI815652B (zh) * 2022-05-17 2023-09-11 群創光電股份有限公司 顯示裝置

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TWI433625B (zh) * 2011-07-04 2014-04-01 Ind Tech Res Inst 軟性電子元件的製法
TWI532162B (zh) * 2013-06-25 2016-05-01 友達光電股份有限公司 可撓式顯示面板及其製造方法
US9876064B2 (en) * 2013-08-30 2018-01-23 Lg Display Co., Ltd. Flexible organic electroluminescent device and method for fabricating the same
JP2017208254A (ja) * 2016-05-19 2017-11-24 株式会社ジャパンディスプレイ 表示装置及びその製造方法
TWI669992B (zh) * 2018-03-16 2019-08-21 友達光電股份有限公司 可撓性電子裝置及其製造方法
CN109148523A (zh) * 2018-08-10 2019-01-04 武汉华星光电半导体显示技术有限公司 一种oled器件及其制备方法

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CN115128860A (zh) * 2021-03-29 2022-09-30 瀚宇彩晶股份有限公司 可挠式显示面板的制造方法
TWI815652B (zh) * 2022-05-17 2023-09-11 群創光電股份有限公司 顯示裝置

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