US20190385954A1 - Semiconductor device with anti-deflection layers - Google Patents
Semiconductor device with anti-deflection layers Download PDFInfo
- Publication number
- US20190385954A1 US20190385954A1 US16/010,571 US201816010571A US2019385954A1 US 20190385954 A1 US20190385954 A1 US 20190385954A1 US 201816010571 A US201816010571 A US 201816010571A US 2019385954 A1 US2019385954 A1 US 2019385954A1
- Authority
- US
- United States
- Prior art keywords
- layer
- tensile
- compressive
- depositing
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000000151 deposition Methods 0.000 claims abstract description 50
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 47
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 43
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 28
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 13
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- 230000001590 oxidative effect Effects 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 20
- 238000005240 physical vapour deposition Methods 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 230000007935 neutral effect Effects 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 30
- 230000007704 transition Effects 0.000 abstract description 8
- 150000001875 compounds Chemical class 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 145
- 239000010408 film Substances 0.000 description 16
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 10
- 235000012431 wafers Nutrition 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 230000008569 process Effects 0.000 description 6
- 229910052715 tantalum Inorganic materials 0.000 description 5
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 5
- 230000008901 benefit Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 3
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000013329 compounding Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000004320 controlled atmosphere Methods 0.000 description 1
- 230000002939 deleterious effect Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 239000002355 dual-layer Substances 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 231100000572 poisoning Toxicity 0.000 description 1
- 230000000607 poisoning effect Effects 0.000 description 1
- 229910021426 porous silicon Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/0021—Reactive sputtering or evaporation
- C23C14/0036—Reactive sputtering
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
- C23C14/0641—Nitrides
- C23C14/0652—Silicon nitride
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/58—After-treatment
- C23C14/5846—Reactive treatment
- C23C14/5853—Oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02266—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by physical ablation of a target, e.g. sputtering, reactive sputtering, physical vapour deposition or pulsed laser deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02304—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
- H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
- H01L21/02326—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen into a nitride layer, e.g. changing SiN to SiON
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
Definitions
- the invention is in the field of semiconductor devices, with mechanisms to prevent deflection.
- a semiconductor device has a neutral deflection dual layer on a face of a substrate, with a tensile layer and a compressive layer.
- a semiconductor device has a silicon nitride tensile layer on a face of a substrate, with a silicon oxide compressive layer on an oxidized surface of the silicon nitride layer.
- a semiconductor device includes: a substrate; a tensile layer overlying a major surface of the substrate; and a compressive layer overlying the major surface.
- the tensile layer and the compressive layer both impart forces onto the substrate, to thereby keep the substrate from bowing.
- the device includes an intermediate layer between the tensile layer and the compressive layer.
- the intermediate layer transmits stresses between the tensile layer and the compressive layer.
- the intermediate layer is thinner than the compressive layer and the tensile layer.
- the intermediate layer is an oxidized surface of the compressive layer or the tensile layer.
- the tensile layer is closer than the compressive layer to the substrate.
- the tensile layer is a silicon nitride layer.
- the compressive layer is a silicon oxide layer.
- the intermediate layer is a silicon oxy-nitride layer.
- a tensile force of the tensile layer balances out a compressive force of the compressive layer.
- a method of making a semiconductor device includes the steps of: depositing a tensile layer overlying a major face of a substrate of the device; and depositing a compressive layer overlying the major face.
- the tensile layer and the compressive layer both impart forces onto the substrate, to thereby keep the substrate from bowing.
- depositing the tensile layer occurs before the depositing the compressive layer, with the compressive layer deposited overlying the tensile layer.
- the method includes forming an intermediate layer that is between the tensile layer and the compressive layer.
- the intermediate layer is formed after the depositing of the tensile layer, and before the depositing of the compressive layer.
- the intermediate layer is formed by oxidizing a surface of the tensile layer.
- depositing the tensile layer includes depositing silicon nitride.
- depositing the silicon nitride includes depositing the silicon nitride by physical vapor deposition.
- depositing the silicon nitride includes columnar deposition of the silicon nitride.
- forming the intermediate layer includes oxidizing a surface of the silicon nitride, to form silicon oxy-nitride.
- oxidizing includes exposing the surface of the silicon nitride to air.
- depositing the compressive layer includes depositing silicon oxide on the silicon oxy-nitride.
- depositing the silicon oxide includes depositing the silicon oxide by physical vapor deposition.
- FIG. 1 is a side cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention.
- FIG. 2 is a side cross-sectional view of the semiconductor device of FIG. 1 , with additional components installed.
- FIG. 3 is a high-level flow chart of a method of making a semiconductor device, according to an embodiment of the invention.
- FIG. 5 is a side cross-sectional view of a semiconductor device in accordance with yet another embodiment of the present invention.
- a semiconductor device has a substrate with both compressive and tensile layers deposited overlying a single major surface (front face) of the device.
- the tensile layer may be deposited directly on the substrate of the device, with the compressive layer overlying the tensile layer.
- a transition material (intermediate layer) may be located between the tensile layer and the compressive layer.
- the transition material may be a compound including the components of one or both of the tensile layer and the compressive layer.
- the tensile material may be a silicon nitride
- the compressive layer may be a silicon oxide
- the transition material may be a silicon oxy-nitride, which may be formed by oxidizing the surface of the tensile silicon nitride layer.
- the materials may be deposited using physical vapor deposition. Conditions for the vapor deposition may be controlled to achieve desired growth rates and/or characteristics of the tensile and compressive layers. By depositing both tensile and compressive layers on the same face of the device the opposite major surface (face) is free for processing.
- FIG. 1 shows a semiconductor device 10 that includes a substrate 12 , with a tensile layer 14 overlying a major surface (front face) 16 of the substrate 12 , and a compressive layer 18 overlying both the tensile layer 14 and the front face 16 .
- the intermediate layer 22 transmits stresses from the compressive layer 18 through to the tensile layer 14 and the substrate 12 .
- the intermediate layer 22 may be a compound that includes one or more components also in the tensile layer 14 and/or the compressive layer 16 .
- the intermediate layer 22 may be formed by chemical compounding of a surface of the tensile layer 14 , for example by forming an oxide layer on the surface of the tensile layer 14 .
- the intermediate layer 22 may be used to facilitate deposition of the compressive layer 18 overlying the tensile layer 14 .
- the intermediate layer 22 may make for a more consistent device 10 in its performance in terms of being able to prevent bowing of the substrate 12 .
- the intermediate layer 22 may facilitate consistency in the stresses and/or in the transmission of stresses from the compressive layer 18 to the tensile layer 14 .
- these possibilities are not definitive or exhaustive, and the intermediate layer 22 may provide different or additional benefits to the device 10 .
- Formation of the tensile layer 14 and the compressive layer 18 both overlying the front face 16 allows operations to be performed on a back face (major surface) 26 of the substrate 12 .
- a back face major surface
- the tensile layer 14 is a silicon nitride
- the compressive layer 18 is a silicon oxide
- the intermediate layer 22 is a silicon oxy-nitride.
- the layers may be formed with compositions and thicknesses so as to put a desired stress on the substrate 12 , to keep the substrate 12 from bowing.
- the silicon nitride tensile layer 14 may have a thickness from 0.1 ⁇ m to 1 ⁇ m, for example having a thickness of 0.6 ⁇ 0.02 ⁇ m.
- the silicon oxide compressive layer 18 may have a thickness of less than 1 ⁇ m, such as 0.5 ⁇ 0.02 ⁇ m.
- the silicon oxy-nitride intermediate layer 22 may have a thickness of about 200 ⁇ (200 Angstroms), such as 200 ⁇ 50 ⁇ (200 ⁇ 50 Angstroms). These values are examples, and should not be construed as limitations. For example a wide varieties of other layer thicknesses may be used, such as while maintaining the general ratios in the thicknesses of the layer. For instance, keeping the ratio of silicon nitride to silicon oxide thicknesses at 6:5 will keep the bow close to zero for thin films on the order of 0.1-10 ⁇ m.
- tantalum nitride and tantalum may be used, with an intermediate transition layer of sub-stoichiometric tantalum nitride.
- the tantalum nitride is compressive, the tantalum in tensile, and the sub-stoichiometric tantalum nitride allows the tantalum to grow with tensile stress.
- Another alternative possibility is using a bilayer of tantalum nitride and copper, with an intermediate layer of tantalum oxy-nitride, which may be created by exposing the tantalum nitride film to atmosphere to oxidize.
- FIG. 2 shows a view of the device 10 at a later stage in processing, when electronic components 40 have been placed on the front face 16 , for example engaging conductive traces and/or vias on the substrate 12 .
- Parts of the layers 14 , 18 , and 22 may be removed, such as by selective etching, in order to form or place the components 40 on the substrate 12 .
- the layers 14 , 18 , and 22 may be deposited onto or around existing components and structures. It will be appreciated that the layers 14 , 18 , and 22 may be removed only at certain discrete locations, leaving the remaining parts of the layers 14 , 18 , and 22 as continuous layers that overly large portions of the front face 16 .
- the materials used in the layers 14 , 18 , and 22 are dielectrics (electrically insulating).
- the silicon oxide, silicon nitride, and silicon oxy-nitride materials used in one embodiment of the invention satisfy this condition.
- silicon nitride has the characteristic of strongly adhering to most substrates used for electronic devices.
- the device 10 may initially have a wafer for its substrate, with the wafer being subdivided into individual devices.
- the individual devices may be used in any of a wide variety of products, and may have any of a variety of components, such as conductive traces, switches, capacitors, etc.
- Devices such as the device 10 may be stacked as a part of a larger electronic device, for 3D wafer stacking, for example.
- steps are shown for a method 100 for producing the device 10 ( FIG. 1 ).
- the steps shown in FIG. 3 and described below are only a few of the steps used in forming a final device, with the illustrated steps focused on the process of preventing bowing or other deflection.
- the tensile layer 14 ( FIG. 1 ) is deposited overlying a major surface (front face) 16 of the substrate 12 .
- the deposition may be by physical vapor deposition (PVD), which is a different process than the plasma enhanced chemical vapor deposition (PECVD) that is usually used for depositing this material.
- PVD physical vapor deposition
- PECVD plasma enhanced chemical vapor deposition
- Advantages for PVD include facilitating cassette wafer processing, providing a shorter cycle time and higher throughput, a low material consumption rate, and low contamination risk.
- the PVD process is performed in a sealed chamber, with the gaseous source materials in a pressure-controlled atmosphere. It has been found that as the chamber pressure increases the tensile film stress of the deposited layer (the tensile layer 14 ( FIG. 1 )) increases, but the deposition rate drops. Thus some sort of balance needs to be struck between a desirable tensile stress for the deposited material, and a faster rate of deposition. Additionally the chamber pressure may be selected so as to yield a deposited material that has a similar magnitude of stress as the material of the compressive layer 18 ( FIG. 1 ), so as to minimize (or reduce) the amount of the tensile material that needs to be deposited. A smaller amount of deposition is preferable because it makes the deposition process proceed faster and at lower cost. In addition, it is possible for deposited silicon nitride to be either compressive or tensile, depending on how it is deposited. For the tensile layer 14 of course tensile silicon nitride is desired.
- the chamber pressure for the PVD process in step 102 may be about 3 mTorr, for example being 3.1 ⁇ 0.1 mTorr, to give non-limiting example values.
- the primary source for the chamber pressure may be an inert gas, such as argon.
- the flow of nitrogen gas may be controlled to prevent poisoning, where material on the target used for deposition accumulates faster than the sputtering process occurs.
- Temperature in the chamber may be controlled, and/or the processing time may be controlled, to prevent damage to a target for sputtering, and/or to avoid deleterious effects to the substrate (wafer) 12 and/or to the deposited material.
- silicon nitride yields a wafer bow of ⁇ 49 ⁇ m for every 1 ⁇ m of thickness of the tensile layer 14 , to give a single non-limiting example value.
- the thickness of the layers 14 and 18 may be selected balance out tension and compression forces on the substrate 12 .
- the intermediate layer 22 ( FIG. 1 ) is formed.
- the intermediate layer 22 may be formed by oxidizing the top of the tensile layer 14 , for example oxidizing the surface of the silicon nitride to form oxy-nitride. This may be done by exposing the silicon nitride to air, for a sufficient time to form oxidize the top layers of the silicon nitride, to produce the intermediate layer 22 . This forms a film gradient from the silicon nitride tensile layer 14 to the silicon oxy-nitride of the intermediate layer 22 . This forms a solid base for the subsequent formation of the silicon oxide compression layer 18 .
- Silicon nitride may be oxidized at room temperature and atmospheric pressure to form a surface layer, such as with a thickness of 100 ⁇ 50 Angstroms of silicon oxy-nitride.
- the top monolayers of silicon nitride oxidize within the first 5-10 minutes of air exposure.
- silicon oxide directly on the silicon nitride may produce undesirable and/or unpredictable results.
- the silicon oxide stress is affected by the surface it grows upon. It is believed that when silicon oxide is deposited (grown) directly on silicon nitride, the porous silicon nitride induces columnar growth in the silicon oxide. This may produce a tensile silicon oxide, for example having a bow of ⁇ 33 ⁇ m for every 1 ⁇ m deposited, when what is desired is for the silicon oxide to be compressive, to provide a force on the substrate 12 that counteracts the tensile force of the underlying layer 14 .
- the top oxidized monolayers form a compact film surface that allows the silicon oxide form to grow densely, producing a compressive film.
- the silicon oxide may have a wafer bow of +85 ⁇ m for every 1 ⁇ m of silicon oxide thickness. This allows formation of a compressive layer that counteracts the tensile force from the silicon nitride.
- the compressive layer 18 ( FIG. 1 ) is deposited overlying the tensile layer 14 .
- the intermediate layer 22 may be used to facilitate deposition of the compressive layer 18 overlying the tensile layer 14 .
- the compressive layer 18 may be deposited by a PVD or other suitable deposition or formation process. When using PVD, compressive films form at low pressures on the order of 0.1-2 mTorr. For example, to balance the deflection from a tensile silicon nitride film deposited at 3 mTorr, a comprehensive silicon dioxide film may be deposited at 0.6 mTorr.
- FIG. 4 shows an alternative arrangement of a semiconductor device 210 that has a compressive layer 218 overlying a front face 216 of a substrate 212 .
- a tensile layer 214 overlies the compressive layer 218 , with an intermediate layer 222 between the layers 214 and 218 .
- the device 210 may function similarly to the device 10 ( FIG. 1 ) with regard to resisting bowing or deformation.
- tantalum nitride and copper allow for the compressive film to be deposited first (tantalum nitride) and the tensile film to be deposited on top (copper).
- an intermediate layer of tantalum may be used between the tantalum nitride and copper layers to promote copper adhesion.
- FIG. 5 shows another alternative of a semiconductor device 310 that has a tensile layer 314 on a front face 316 of a substrate 312 , and a compressive layer 318 is formed directly on the tensile layer 314 .
- the intervening layer 22 ( FIG. 1 ) is omitted in this embodiment.
- an intermediate layer has advantages, as described above, it may be possible to omit the intermediate layer in some situations, such as with certain materials.
- tensile copper may be deposited directly onto compressive tantalum nitride to form a balanced film stack. The two films have complimentary deflections that can cancel out without the aid of an intermediate film.
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Optics & Photonics (AREA)
- Ceramic Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Physical Vapour Deposition (AREA)
Abstract
Description
- The invention is in the field of semiconductor devices, with mechanisms to prevent deflection.
- In semiconductor devices it is desirable to keep the device from bowing. One approach to prevent bowing has been to deposit material on both opposite sides (major surfaces) of a semiconductor wafer. For example depositing compressive stress material on both front and back major surfaces balances stresses, preventing bowing. However it is not always desirable or practical to deposit material on both major surfaces.
- A semiconductor device has a neutral deflection dual layer on a face of a substrate, with a tensile layer and a compressive layer.
- A semiconductor device has a silicon nitride tensile layer on a face of a substrate, with a silicon oxide compressive layer on an oxidized surface of the silicon nitride layer.
- According to an aspect of the invention, a semiconductor device includes: a substrate; a tensile layer overlying a major surface of the substrate; and a compressive layer overlying the major surface. The tensile layer and the compressive layer both impart forces onto the substrate, to thereby keep the substrate from bowing.
- According to an embodiment of any paragraph(s) of this summary, the device includes an intermediate layer between the tensile layer and the compressive layer.
- According to an embodiment of any paragraph(s) of this summary, the intermediate layer transmits stresses between the tensile layer and the compressive layer.
- According to an embodiment of any paragraph(s) of this summary, the intermediate layer is thinner than the compressive layer and the tensile layer.
- According to an embodiment of any paragraph(s) of this summary, the intermediate layer is an oxidized surface of the compressive layer or the tensile layer.
- According to an embodiment of any paragraph(s) of this summary, the tensile layer is closer than the compressive layer to the substrate.
- According to an embodiment of any paragraph(s) of this summary, the tensile layer is a silicon nitride layer.
- According to an embodiment of any paragraph(s) of this summary, the compressive layer is a silicon oxide layer.
- According to an embodiment of any paragraph(s) of this summary, the intermediate layer is a silicon oxy-nitride layer.
- According to an embodiment of any paragraph(s) of this summary, a tensile force of the tensile layer balances out a compressive force of the compressive layer.
- According to another aspect of the invention, a method of making a semiconductor device includes the steps of: depositing a tensile layer overlying a major face of a substrate of the device; and depositing a compressive layer overlying the major face. The tensile layer and the compressive layer both impart forces onto the substrate, to thereby keep the substrate from bowing.
- According to an embodiment of any paragraph(s) of this summary, depositing the tensile layer occurs before the depositing the compressive layer, with the compressive layer deposited overlying the tensile layer.
- According to an embodiment of any paragraph(s) of this summary, the method includes forming an intermediate layer that is between the tensile layer and the compressive layer.
- According to an embodiment of any paragraph(s) of this summary, the intermediate layer is formed after the depositing of the tensile layer, and before the depositing of the compressive layer.
- According to an embodiment of any paragraph(s) of this summary, the intermediate layer is formed by oxidizing a surface of the tensile layer.
- According to an embodiment of any paragraph(s) of this summary, depositing the tensile layer includes depositing silicon nitride.
- According to an embodiment of any paragraph(s) of this summary, depositing the silicon nitride includes depositing the silicon nitride by physical vapor deposition.
- According to an embodiment of any paragraph(s) of this summary, depositing the silicon nitride includes columnar deposition of the silicon nitride.
- According to an embodiment of any paragraph(s) of this summary, forming the intermediate layer includes oxidizing a surface of the silicon nitride, to form silicon oxy-nitride.
- According to an embodiment of any paragraph(s) of this summary, oxidizing includes exposing the surface of the silicon nitride to air.
- According to an embodiment of any paragraph(s) of this summary, depositing the compressive layer includes depositing silicon oxide on the silicon oxy-nitride.
- According to an embodiment of any paragraph(s) of this summary, depositing the silicon oxide includes depositing the silicon oxide by physical vapor deposition.
- To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative embodiments of the invention. These embodiments are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.
- The annexed drawings show various aspects of the invention.
-
FIG. 1 is a side cross-sectional view of a semiconductor device in accordance with an embodiment of the present invention. -
FIG. 2 is a side cross-sectional view of the semiconductor device ofFIG. 1 , with additional components installed. -
FIG. 3 is a high-level flow chart of a method of making a semiconductor device, according to an embodiment of the invention. -
FIG. 4 is a side cross-sectional view of a semiconductor device in accordance with another embodiment of the present invention. -
FIG. 5 is a side cross-sectional view of a semiconductor device in accordance with yet another embodiment of the present invention. - A semiconductor device has a substrate with both compressive and tensile layers deposited overlying a single major surface (front face) of the device. The tensile layer may be deposited directly on the substrate of the device, with the compressive layer overlying the tensile layer. A transition material (intermediate layer) may be located between the tensile layer and the compressive layer. The transition material may be a compound including the components of one or both of the tensile layer and the compressive layer. In a specific embodiment, the tensile material may be a silicon nitride, the compressive layer may be a silicon oxide, and the transition material may be a silicon oxy-nitride, which may be formed by oxidizing the surface of the tensile silicon nitride layer. The materials may be deposited using physical vapor deposition. Conditions for the vapor deposition may be controlled to achieve desired growth rates and/or characteristics of the tensile and compressive layers. By depositing both tensile and compressive layers on the same face of the device the opposite major surface (face) is free for processing.
-
FIG. 1 shows asemiconductor device 10 that includes asubstrate 12, with atensile layer 14 overlying a major surface (front face) 16 of thesubstrate 12, and acompressive layer 18 overlying both thetensile layer 14 and thefront face 16. There may also be an intermediate layer (or transition layer) 22 between thetensile layer 14 and thecompressive layer 16. As explained in greater detail below, theintermediate layer 22 transmits stresses from thecompressive layer 18 through to thetensile layer 14 and thesubstrate 12. Theintermediate layer 22 may be a compound that includes one or more components also in thetensile layer 14 and/or thecompressive layer 16. Alternatively theintermediate layer 22 may be formed by chemical compounding of a surface of thetensile layer 14, for example by forming an oxide layer on the surface of thetensile layer 14. - The
intermediate layer 22 may be used to facilitate deposition of thecompressive layer 18 overlying thetensile layer 14. Theintermediate layer 22 may make for a moreconsistent device 10 in its performance in terms of being able to prevent bowing of thesubstrate 12. Toward that end, theintermediate layer 22 may facilitate consistency in the stresses and/or in the transmission of stresses from thecompressive layer 18 to thetensile layer 14. However these possibilities are not definitive or exhaustive, and theintermediate layer 22 may provide different or additional benefits to thedevice 10. - Formation of the
tensile layer 14 and thecompressive layer 18 both overlying thefront face 16 allows operations to be performed on a back face (major surface) 26 of thesubstrate 12. For example it may be possible to reduce thickness of thedevice 10 as needed by removing material along theback face 26. Or it may be important to keep theback side 26 available for other purposes, such as for placement of sensitive devices (components), or for bonding to other structures for stacking of wafers or semiconductor devices. - In one embodiment the
tensile layer 14 is a silicon nitride, thecompressive layer 18 is a silicon oxide, and theintermediate layer 22 is a silicon oxy-nitride. These are only example materials, and other suitable materials are possible as alternatives. The layers may be formed with compositions and thicknesses so as to put a desired stress on thesubstrate 12, to keep thesubstrate 12 from bowing. - The silicon nitride
tensile layer 14 may have a thickness from 0.1 μm to 1 μm, for example having a thickness of 0.6±0.02 μm. The silicon oxide compressivelayer 18 may have a thickness of less than 1 μm, such as 0.5±0.02 μm. The silicon oxy-nitrideintermediate layer 22 may have a thickness of about 200 Å (200 Angstroms), such as 200±50 Å (200±50 Angstroms). These values are examples, and should not be construed as limitations. For example a wide varieties of other layer thicknesses may be used, such as while maintaining the general ratios in the thicknesses of the layer. For instance, keeping the ratio of silicon nitride to silicon oxide thicknesses at 6:5 will keep the bow close to zero for thin films on the order of 0.1-10 μm. - As an alternative stoichiometric tantalum nitride and tantalum may be used, with an intermediate transition layer of sub-stoichiometric tantalum nitride. The tantalum nitride is compressive, the tantalum in tensile, and the sub-stoichiometric tantalum nitride allows the tantalum to grow with tensile stress. Another alternative possibility is using a bilayer of tantalum nitride and copper, with an intermediate layer of tantalum oxy-nitride, which may be created by exposing the tantalum nitride film to atmosphere to oxidize.
-
FIG. 2 shows a view of thedevice 10 at a later stage in processing, whenelectronic components 40 have been placed on thefront face 16, for example engaging conductive traces and/or vias on thesubstrate 12. Parts of thelayers components 40 on thesubstrate 12. In other embodiments, thelayers layers layers front face 16. - It is often desirable for the
electronic components 40 to be electrically isolated from one another. Therefore it is desirable for the materials used in thelayers - The
device 10 may initially have a wafer for its substrate, with the wafer being subdivided into individual devices. The individual devices may be used in any of a wide variety of products, and may have any of a variety of components, such as conductive traces, switches, capacitors, etc. Devices such as thedevice 10 may be stacked as a part of a larger electronic device, for 3D wafer stacking, for example. - With reference now to
FIG. 3 , steps are shown for amethod 100 for producing the device 10 (FIG. 1 ). The steps shown inFIG. 3 and described below are only a few of the steps used in forming a final device, with the illustrated steps focused on the process of preventing bowing or other deflection. - In
step 102 the tensile layer 14 (FIG. 1 ) is deposited overlying a major surface (front face) 16 of thesubstrate 12. The deposition may be by physical vapor deposition (PVD), which is a different process than the plasma enhanced chemical vapor deposition (PECVD) that is usually used for depositing this material. Advantages for PVD include facilitating cassette wafer processing, providing a shorter cycle time and higher throughput, a low material consumption rate, and low contamination risk. - The PVD process is performed in a sealed chamber, with the gaseous source materials in a pressure-controlled atmosphere. It has been found that as the chamber pressure increases the tensile film stress of the deposited layer (the tensile layer 14 (
FIG. 1 )) increases, but the deposition rate drops. Thus some sort of balance needs to be struck between a desirable tensile stress for the deposited material, and a faster rate of deposition. Additionally the chamber pressure may be selected so as to yield a deposited material that has a similar magnitude of stress as the material of the compressive layer 18 (FIG. 1 ), so as to minimize (or reduce) the amount of the tensile material that needs to be deposited. A smaller amount of deposition is preferable because it makes the deposition process proceed faster and at lower cost. In addition, it is possible for deposited silicon nitride to be either compressive or tensile, depending on how it is deposited. For thetensile layer 14 of course tensile silicon nitride is desired. - The chamber pressure for the PVD process in
step 102 may be about 3 mTorr, for example being 3.1±0.1 mTorr, to give non-limiting example values. The primary source for the chamber pressure may be an inert gas, such as argon. The flow of nitrogen gas may be controlled to prevent poisoning, where material on the target used for deposition accumulates faster than the sputtering process occurs. Temperature in the chamber may be controlled, and/or the processing time may be controlled, to prevent damage to a target for sputtering, and/or to avoid deleterious effects to the substrate (wafer) 12 and/or to the deposited material. - Increasing of the pressure in the chamber leads to growth of silicon nitride in columnar structures, which produces a more porous and tensile film. The spacing between columnar grains produces a lower refractive index that the typical stoichiometric silicon nitride (Si3N4), although the porous columnar form that may be used for the
tensile layer 14 may also have the same stoichiometric silicon nitride. - It has been found that silicon nitride yields a wafer bow of −49 μm for every 1 μm of thickness of the
tensile layer 14, to give a single non-limiting example value. The thickness of thelayers substrate 12. - In
step 104 the intermediate layer 22 (FIG. 1 ) is formed. Theintermediate layer 22 may be formed by oxidizing the top of thetensile layer 14, for example oxidizing the surface of the silicon nitride to form oxy-nitride. This may be done by exposing the silicon nitride to air, for a sufficient time to form oxidize the top layers of the silicon nitride, to produce theintermediate layer 22. This forms a film gradient from the silicon nitridetensile layer 14 to the silicon oxy-nitride of theintermediate layer 22. This forms a solid base for the subsequent formation of the siliconoxide compression layer 18. - Silicon nitride may be oxidized at room temperature and atmospheric pressure to form a surface layer, such as with a thickness of 100±50 Angstroms of silicon oxy-nitride. The top monolayers of silicon nitride oxidize within the first 5-10 minutes of air exposure.
- The deposition of silicon oxide directly on the silicon nitride may produce undesirable and/or unpredictable results. The silicon oxide stress is affected by the surface it grows upon. It is believed that when silicon oxide is deposited (grown) directly on silicon nitride, the porous silicon nitride induces columnar growth in the silicon oxide. This may produce a tensile silicon oxide, for example having a bow of −33 μm for every 1 μm deposited, when what is desired is for the silicon oxide to be compressive, to provide a force on the
substrate 12 that counteracts the tensile force of theunderlying layer 14. However when the silicon nitride surface is oxidized first, the top oxidized monolayers form a compact film surface that allows the silicon oxide form to grow densely, producing a compressive film. For example the silicon oxide may have a wafer bow of +85 μm for every 1 μm of silicon oxide thickness. This allows formation of a compressive layer that counteracts the tensile force from the silicon nitride. - The above mechanisms are conjectures for the observed advantageous performance of devices with the
intermediate layer 22. It should be appreciated that the actual mechanisms of material growth may be different from those described above. - Finally, in
step 106 the compressive layer 18 (FIG. 1 ) is deposited overlying thetensile layer 14. More specifically, theintermediate layer 22 may be used to facilitate deposition of thecompressive layer 18 overlying thetensile layer 14. Thecompressive layer 18 may be deposited by a PVD or other suitable deposition or formation process. When using PVD, compressive films form at low pressures on the order of 0.1-2 mTorr. For example, to balance the deflection from a tensile silicon nitride film deposited at 3 mTorr, a comprehensive silicon dioxide film may be deposited at 0.6 mTorr. Compressive dielectric films, for example silicon oxide and silicon nitride, may alternatively be deposited using electron beam evaporation. Other material sets of compressive films, typically metals, may be deposited using electroplating.FIG. 4 shows an alternative arrangement of asemiconductor device 210 that has acompressive layer 218 overlying afront face 216 of asubstrate 212. Atensile layer 214 overlies thecompressive layer 218, with anintermediate layer 222 between thelayers device 210 may function similarly to the device 10 (FIG. 1 ) with regard to resisting bowing or deformation. Certain materials sets, for example tantalum nitride and copper, allow for the compressive film to be deposited first (tantalum nitride) and the tensile film to be deposited on top (copper). In some cases, an intermediate layer of tantalum may be used between the tantalum nitride and copper layers to promote copper adhesion. -
FIG. 5 shows another alternative of asemiconductor device 310 that has atensile layer 314 on afront face 316 of asubstrate 312, and acompressive layer 318 is formed directly on thetensile layer 314. The intervening layer 22 (FIG. 1 ) is omitted in this embodiment. Although an intermediate layer has advantages, as described above, it may be possible to omit the intermediate layer in some situations, such as with certain materials. As an example, tensile copper may be deposited directly onto compressive tantalum nitride to form a balanced film stack. The two films have complimentary deflections that can cancel out without the aid of an intermediate film. - Although the invention has been shown and described with respect to a certain preferred embodiment or embodiments, it is obvious that equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described elements (components, assemblies, devices, compositions, etc.), the terms (including a reference to a “means”) used to describe such elements are intended to correspond, unless otherwise indicated, to any element which performs the specified function of the described element (i.e., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary embodiment or embodiments of the invention. In addition, while a particular feature of the invention may have been described above with respect to only one or more of several illustrated embodiments, such feature may be combined with one or more other features of the other embodiments, as may be desired and advantageous for any given or particular application.
Claims (22)
Priority Applications (10)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/010,571 US10515905B1 (en) | 2018-06-18 | 2018-06-18 | Semiconductor device with anti-deflection layers |
CA3104245A CA3104245C (en) | 2018-06-18 | 2019-05-06 | Semiconductor device with anti-deflection layers |
KR1020207024751A KR102478822B1 (en) | 2018-06-18 | 2019-05-06 | Semiconductor device with anti-warp layer |
JP2021516524A JP7072121B2 (en) | 2018-06-18 | 2019-05-06 | Semiconductor device with anti-deflection layer |
SG11202012678WA SG11202012678WA (en) | 2018-06-18 | 2019-05-06 | Semiconductor device with anti-deflection layers |
EP19725472.5A EP3807928A1 (en) | 2018-06-18 | 2019-05-06 | Semiconductor device with anti-deflection layers |
CN201980052599.4A CN112640092A (en) | 2018-06-18 | 2019-05-06 | Semiconductor device with anti-deflection layer |
PCT/US2019/030856 WO2019245660A1 (en) | 2018-06-18 | 2019-05-06 | Semiconductor device with anti-deflection layers |
TW108117349A TWI720487B (en) | 2018-06-18 | 2019-05-20 | Semiconductor device with anti-deflection layers |
IL276506A IL276506B (en) | 2018-06-18 | 2020-08-05 | Semiconductor device with anti-deflection layers |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/010,571 US10515905B1 (en) | 2018-06-18 | 2018-06-18 | Semiconductor device with anti-deflection layers |
Publications (2)
Publication Number | Publication Date |
---|---|
US20190385954A1 true US20190385954A1 (en) | 2019-12-19 |
US10515905B1 US10515905B1 (en) | 2019-12-24 |
Family
ID=66625281
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/010,571 Active US10515905B1 (en) | 2018-06-18 | 2018-06-18 | Semiconductor device with anti-deflection layers |
Country Status (10)
Country | Link |
---|---|
US (1) | US10515905B1 (en) |
EP (1) | EP3807928A1 (en) |
JP (1) | JP7072121B2 (en) |
KR (1) | KR102478822B1 (en) |
CN (1) | CN112640092A (en) |
CA (1) | CA3104245C (en) |
IL (1) | IL276506B (en) |
SG (1) | SG11202012678WA (en) |
TW (1) | TWI720487B (en) |
WO (1) | WO2019245660A1 (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10896821B2 (en) * | 2018-09-28 | 2021-01-19 | Lam Research Corporation | Asymmetric wafer bow compensation by physical vapor deposition |
WO2021178031A1 (en) * | 2020-03-06 | 2021-09-10 | Raytheon Company | Semiconductor device with aluminum nitride anti-deflection layer |
US20210320036A1 (en) * | 2020-04-14 | 2021-10-14 | International Business Machines Corporation | Wafer backside engineering for wafer stress control |
WO2022245516A1 (en) * | 2021-05-17 | 2022-11-24 | Raytheon Company | Electrical device with stress buffer layer and stress compensation layer |
US20220384366A1 (en) * | 2021-06-01 | 2022-12-01 | Cree, Inc. | Multilayer encapsulation for humidity robustness and related fabrication methods |
WO2022256196A1 (en) * | 2021-06-01 | 2022-12-08 | Wolfspeed, Inc. | Multilayer encapsulation for humidity robustness and highly accelerated stress tests and related fabrication methods |
US11810781B2 (en) | 2020-03-24 | 2023-11-07 | Kokusai Electric Corporation | Method of processing substrate, substrate processing apparatus, recording medium, method of manufacturing semiconductor device |
US12002773B2 (en) | 2021-03-03 | 2024-06-04 | Raytheon Company | Hybrid pocket post and tailored via dielectric for 3D-integrated electrical device |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11851785B2 (en) | 2021-05-21 | 2023-12-26 | Raytheon Company | Aluminum nitride passivation layer for mercury cadmium telluride in an electrical device |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03151637A (en) * | 1989-11-09 | 1991-06-27 | Kowa Kurieitaa:Kk | Manufacture of semiconductor device and plasma cvd equipment |
JP2822656B2 (en) | 1990-10-17 | 1998-11-11 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
JP3632256B2 (en) | 1994-09-30 | 2005-03-23 | 株式会社デンソー | Manufacturing method of semiconductor device having silicon nitride film |
JP2002076336A (en) | 2000-09-01 | 2002-03-15 | Mitsubishi Electric Corp | Semiconductor device and soi substrate |
JP2002158213A (en) * | 2000-11-21 | 2002-05-31 | Sharp Corp | Method of manufacturing semiconductor device |
KR100767950B1 (en) | 2000-11-22 | 2007-10-18 | 가부시키가이샤 히타치세이사쿠쇼 | Semiconductor device and method for fabricating the same |
US6984892B2 (en) * | 2001-03-28 | 2006-01-10 | Lam Research Corporation | Semiconductor structure implementing low-K dielectric materials and supporting stubs |
US6548422B1 (en) | 2001-09-27 | 2003-04-15 | Agere Systems, Inc. | Method and structure for oxide/silicon nitride interface substructure improvements |
CN1244144C (en) * | 2002-04-09 | 2006-03-01 | 台湾积体电路制造股份有限公司 | Method for forming low dielectric constant dielectric layer and conductive interconnector structure |
KR100761361B1 (en) * | 2006-05-02 | 2007-09-27 | 주식회사 하이닉스반도체 | Semiconductor device and method for manufacturing the same |
US7834399B2 (en) * | 2007-06-05 | 2010-11-16 | International Business Machines Corporation | Dual stress memorization technique for CMOS application |
US7998800B2 (en) * | 2007-07-06 | 2011-08-16 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing semiconductor device |
JP2009076605A (en) * | 2007-09-19 | 2009-04-09 | Fujitsu Microelectronics Ltd | Method of manufacturing semiconductor device |
US7982250B2 (en) * | 2007-09-21 | 2011-07-19 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US20090159958A1 (en) | 2007-12-20 | 2009-06-25 | Spansion Llc | Electronic device including a silicon nitride layer and a process of forming the same |
US7807586B2 (en) | 2008-03-28 | 2010-10-05 | Tokyo Electron Limited | Method of forming a stressed passivation film using a non-ionizing electromagnetic radiation-assisted oxidation process |
US9082857B2 (en) * | 2008-09-01 | 2015-07-14 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device comprising an oxide semiconductor layer |
JP5478166B2 (en) * | 2008-09-11 | 2014-04-23 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
JP5384291B2 (en) | 2008-11-26 | 2014-01-08 | 株式会社日立国際電気 | Semiconductor device manufacturing method, substrate processing method, and substrate processing apparatus |
KR20230107711A (en) * | 2009-11-13 | 2023-07-17 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Display device and electronic device including the same |
US8076250B1 (en) | 2010-10-06 | 2011-12-13 | Applied Materials, Inc. | PECVD oxide-nitride and oxide-silicon stacks for 3D memory application |
JP5867814B2 (en) | 2012-01-13 | 2016-02-24 | 住友電工デバイス・イノベーション株式会社 | Manufacturing method of semiconductor device |
CN107611012B (en) | 2017-08-31 | 2020-10-02 | 长江存储科技有限责任公司 | Stress control method and structure of prefabricated back film |
-
2018
- 2018-06-18 US US16/010,571 patent/US10515905B1/en active Active
-
2019
- 2019-05-06 SG SG11202012678WA patent/SG11202012678WA/en unknown
- 2019-05-06 JP JP2021516524A patent/JP7072121B2/en active Active
- 2019-05-06 EP EP19725472.5A patent/EP3807928A1/en active Pending
- 2019-05-06 CA CA3104245A patent/CA3104245C/en active Active
- 2019-05-06 KR KR1020207024751A patent/KR102478822B1/en active IP Right Grant
- 2019-05-06 CN CN201980052599.4A patent/CN112640092A/en active Pending
- 2019-05-06 WO PCT/US2019/030856 patent/WO2019245660A1/en unknown
- 2019-05-20 TW TW108117349A patent/TWI720487B/en active
-
2020
- 2020-08-05 IL IL276506A patent/IL276506B/en active IP Right Grant
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10896821B2 (en) * | 2018-09-28 | 2021-01-19 | Lam Research Corporation | Asymmetric wafer bow compensation by physical vapor deposition |
JP2023516429A (en) * | 2020-03-06 | 2023-04-19 | レイセオン カンパニー | Semiconductor device with aluminum nitride anti-bending layer |
WO2021178031A1 (en) * | 2020-03-06 | 2021-09-10 | Raytheon Company | Semiconductor device with aluminum nitride anti-deflection layer |
JP7479493B2 (en) | 2020-03-06 | 2024-05-08 | レイセオン カンパニー | Semiconductor device having aluminum nitride anti-deflection layer |
US11410937B2 (en) | 2020-03-06 | 2022-08-09 | Raytheon Company | Semiconductor device with aluminum nitride anti-deflection layer |
US11810781B2 (en) | 2020-03-24 | 2023-11-07 | Kokusai Electric Corporation | Method of processing substrate, substrate processing apparatus, recording medium, method of manufacturing semiconductor device |
US11569134B2 (en) * | 2020-04-14 | 2023-01-31 | International Business Machines Corporation | Wafer backside engineering for wafer stress control |
US20210320036A1 (en) * | 2020-04-14 | 2021-10-14 | International Business Machines Corporation | Wafer backside engineering for wafer stress control |
US12002773B2 (en) | 2021-03-03 | 2024-06-04 | Raytheon Company | Hybrid pocket post and tailored via dielectric for 3D-integrated electrical device |
WO2022245516A1 (en) * | 2021-05-17 | 2022-11-24 | Raytheon Company | Electrical device with stress buffer layer and stress compensation layer |
US11894477B2 (en) | 2021-05-17 | 2024-02-06 | Raytheon Company | Electrical device with stress buffer layer and stress compensation layer |
WO2022256196A1 (en) * | 2021-06-01 | 2022-12-08 | Wolfspeed, Inc. | Multilayer encapsulation for humidity robustness and highly accelerated stress tests and related fabrication methods |
US20220384366A1 (en) * | 2021-06-01 | 2022-12-01 | Cree, Inc. | Multilayer encapsulation for humidity robustness and related fabrication methods |
Also Published As
Publication number | Publication date |
---|---|
EP3807928A1 (en) | 2021-04-21 |
JP2021526318A (en) | 2021-09-30 |
WO2019245660A1 (en) | 2019-12-26 |
TW202002235A (en) | 2020-01-01 |
US10515905B1 (en) | 2019-12-24 |
JP7072121B2 (en) | 2022-05-19 |
TWI720487B (en) | 2021-03-01 |
CA3104245C (en) | 2023-03-28 |
KR20200111244A (en) | 2020-09-28 |
CA3104245A1 (en) | 2019-12-26 |
IL276506B (en) | 2021-04-29 |
CN112640092A (en) | 2021-04-09 |
IL276506A (en) | 2020-09-30 |
KR102478822B1 (en) | 2022-12-16 |
SG11202012678WA (en) | 2021-01-28 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10515905B1 (en) | Semiconductor device with anti-deflection layers | |
US6057237A (en) | Tantalum-containing barrier layers for copper | |
US5668411A (en) | Diffusion barrier trilayer for minimizing reaction between metallization layers of integrated circuits | |
US8328585B2 (en) | Modulated deposition process for stress control in thick TiN films | |
CN110235220A (en) | The metal adjustable thin film stress compensation of epitaxial wafer | |
US6429151B1 (en) | Semiconductor wafer assemblies comprising silicon nitride, methods of forming silicon nitride, and methods of reducing stress on semiconductive wafers | |
JPS595629A (en) | Double layer surface stabilizing method | |
US20090015369A1 (en) | Semiconductor device and method for manufacturing the same | |
US20010009804A1 (en) | Manufacturing process of a semiconductor device | |
US6747338B1 (en) | Composite dielectric with improved etch selectivity for high voltage MEMS structures | |
US7928016B2 (en) | Method of manufacturing semiconductor device, and semiconductor device | |
US6514850B2 (en) | Interface with dielectric layer and method of making | |
JPH08306658A (en) | Method of etching oxide | |
CN109928357A (en) | A kind of MEMS bridge structure and forming method thereof | |
JP2002158226A (en) | Silicon nitride solid surface protective film and its manufacturing method as well as hall element | |
US20230170111A1 (en) | Improved nickel chromium aluminum thin film resistor | |
JPH0193117A (en) | Manufacture of film | |
US20240170298A1 (en) | Method for producing an integrated circuit to remedy defects or dislocations | |
JP2007180394A (en) | Capacitor | |
US7166884B2 (en) | Method for fabricating semiconductor device and semiconductor device | |
US6420263B1 (en) | Method for controlling extrusions in aluminum metal lines and the device formed therefrom | |
US20090166874A1 (en) | Semiconductor Device and Method of Fabricating the Same | |
JPH0629282A (en) | Manufacture of semiconductor device | |
US7276777B2 (en) | Thin film resistor and method of making the same | |
JPH0499031A (en) | Manufacture of semiconductor integrated circuit device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: RAYTHEON COMPANY, MASSACHUSETTS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:RONDON, MICHAEL J.;CLARKE, ANDREW P.;GRAMA, GEORGE;REEL/FRAME:046114/0849 Effective date: 20180615 |
|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 4 |