JPH0499031A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To restrain the stressmigration due to the stress of a layer insulating film imposed on an Al wiring by a method wherein, when a silicon oxide film is deposited on the upper or lower layer of an aluminum wiring, the dangling bond density of the silicon contained in the silicon oxide film is specified. CONSTITUTION:The dangling bond density of the silicon in a silicon oxide film is specified to be exceeding 1X10<18>each/cm<2>, e.g. about 1X10<19>each/cm<2> each of the silicon oxide film 13a in the dangling bond density of silicon contained in the film is deposited in the initial deposition stage. The film thickness of the silicon oxide film 13a is, e.g. about 100mum. During the bias sputtering process, the film deposition and the etching step using Ar<+> ions are simultaneously advanced so as to form the dangling bond on the silicon in the film by this etching damage. Accordingly, the dangling bond density of the silicon contained in the film can be controlled by changing the specific etching rate to the deposition rate of the film by adjusting the bias requirements.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a manufacturing technology for semiconductor integrated circuit devices, and in particular to a technology that is effective when applied to reduce stress migration of 8β (aluminum) wiring. .

[Conventional technology]

As the number of layers of Al interconnects increases as semiconductor integrated circuit devices become more highly integrated, the number of heat treatment steps for interlayer insulating films increases, and stress applied to interconnects due to differences in thermal expansion coefficients between AI and insulating film materials increases. As a result, an increase in the disconnection failure rate due to stress migration becomes a serious problem. Stress migration is a phenomenon in which AI diffuses to relieve stress applied to wiring, and wire breaks occur due to AI diffusion.
It is said that the cause is the generation and growth of voids at grain boundaries. Details of this disconnection mechanism are discussed, for example, in Nikkei Microdevices JP93 to PIO4 published by Nikkei BP (May 1, 1990).

As a measure to suppress stress migration of wiring caused by stress in the interlayer insulating film, it has been proposed to use a composite interlayer insulating film. This is an attempt to reduce the stress applied to the Al wiring as a whole by stacking different types of insulating films that have different stress behavior during heat treatment, thereby canceling out the stress of each film.

[Problem to be solved by the invention]

However, measures to suppress stress migration by forming an interlayer insulating film into a composite film have the problem of increasing the number of insulating film deposition steps.Therefore, there is a need for an interlayer insulating film that applies less stress to wiring during heat treatment.

An object of the present invention is to provide a technique that can suppress stress migration caused by stress in an interlayer insulating film applied to an AI2 wiring.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

One invention of the present application is to increase the density of silicon dangling bonds in the silicon oxide film to I×101 bonds/ctl or more when depositing a silicon oxide film on the upper or lower layer of the Al wiring. .

[Effect]

There is a correlation between the amount of stress change in a silicon oxide film (the difference between the film stress at room temperature and the film stress during heat treatment) and the dangling bond density in the film. The lower the density, the greater the amount of stress change. On the other hand, the amount of stress change in the Al wiring is relatively small. Therefore, if a silicon oxide film with a low dangling bond density is deposited on the top or bottom layer of the Al wiring, the difference in the amount of stress change between the two during heat treatment, that is, the stress of the silicon oxide film applied to the Al wiring, increases, causing the Al wiring to Stress migration becomes more likely to occur.

For these reasons, the density of silicon dangling bonds in the silicon oxide film is set to lXl0''/cfll (conventionally, 5
By increasing the density to X 10" to I becomes possible.

〔Example〕

A method of depositing an interlayer insulating film according to an embodiment of the present invention is shown in FIGS.
This will be explained using FIG.

As shown in FIG. 6, an argon (Ar) gas supply source 3 and a vacuum pump 4 are connected to the chamber 2 of the bias sputtering apparatus 1 used in this embodiment. chamber 2
A wafer jig 6 made of quartz to which an electrode 5 is connected is disposed inside, and a semiconductor wafer 7 that has undergone the first layer wiring formation process is placed on top of the wafer jig 6. A quartz (silicon oxide) target 9 to which a counter electrode 8 is connected is placed above the electrode 5, and the counter electrode 8 and the electrode 5 are connected to each other.
A high frequency power source 10 is connected between the two.

As shown in FIG. 1, a first layer of Al is formed on the main surface of the wafer 7 made of single crystal silicon through a thin thermal oxide film 11.
Wiring 12 is formed. The Al wiring 12 is made of an Al alloy containing, for example, 0.7% silicon and 3% copper, and has a line width x film thickness of 3.0 μm x 0.5 μm.

To deposit a silicon oxide film on the surface of the wafer 7, first, the chamber 2 of the apparatus 1 is evacuated with the vacuum pump 5 to a predetermined degree of vacuum.
A predetermined amount of Ar gas is introduced into the chamber. Subsequently, power is applied to the electrode 5.8 to form a plasma atmosphere in the chamber 2, and a bias is applied to the wafer 7, so that the generated A
Target 9 is sputtered with r'' ions.

As shown in FIG. 2, in this embodiment, in the initial stage of depositing a silicon oxide film, the density of silicon dangling bonds in the film is, for example, about lXl0''/Cd.
Deposit 3a. The thickness of the upper silicon oxide film 13a is, for example, about 100 μm. In the bias sputtering method, film deposition and film etching by Ar♦ ions proceed simultaneously, and this etching damage causes dangling bonds in the silicon in the film. Therefore, by adjusting the bias conditions and changing the ratio of the etching rate to the deposition rate of the film, the density of silicon dangling bonds in the film can be controlled.

Next, as shown in FIG. 3, a silicon oxide film 13b having a silicon dangling bond density of about 3×10'' pieces/Cd is formed on the silicon oxide film 13a by reducing the etching rate ratio to the film deposition rate. The silicon oxide film 13 is deposited.
The film thickness of b is, for example, about 100 to 200 μm.

Next, as shown in FIG. 4, the ratio of the etching rate to the film deposition rate is increased again to increase the density of silicon dangling bonds on the silicon oxide film 13b by lXl0''/
A silicon oxide film 13a of approximately the same thickness as cut is deposited. The thickness of the silicon oxide film 13a is, for example, about 100 μm.

After depositing the interlayer insulating film 13 made of silicon oxide in which the dangling bond density of silicon is high in the upper and lower layers and low in the middle layer, as shown in FIG. A second layer of Al wiring 11 is formed thereon. The A1 wiring 14 is made of, for example, 0.7% silicon and 3% silicon.
% of copper, and the line width x film thickness is 3.0 μm×0.5 μm.

Next, the functions and effects obtained by the above-described interlayer insulating film deposition method will be explained with reference to FIGS. 7 and 8.

FIG. 7 is a diagram showing the temperature dependence of the compressive stress of a silicon oxide film (ASB) deposited on a wafer by bias sputtering. In the figure, the silicon dangling bond density of the silicon oxide film (A) is 1×1, which is the same as that of the silicon oxide film 13a.
The silicon dangling bond density of the silicon oxide film (B) is approximately 0.01s/cat, and the silicon dangling bond density of the silicon oxide film (B) is approximately
It is about 3x1011 pieces/crl, which is the same as . Also, the 8th
The figure shows the temperature dependence of compressive stress when an A1 alloy film (C) containing 0.7% silicon and 3% copper, which is the same as the β wiring 12.14, is deposited on a wafer. It is.

As shown in FIG. 7, silicon oxide film (A) at room temperature
There is almost no difference between the compressive stress of the silicon oxide film (B) and the compressive stress of the silicon oxide film (B). On the other hand, there is a considerable difference between the compressive stress of the two during heat treatment at 500°C, and the amount of stress change in the silicon oxide film (A) with high dangling bond density (film stress at room temperature and heat treatment The difference in stress from that of the film (B) is small, and the amount of stress change in the silicon oxide film (B) with low dangling bond density is large. Thus, there is a correlation between the stress of the silicon oxide film and the dangling bond density in the film, and the higher the dangling bond density, the smaller the amount of stress change. On the other hand, the amount of stress change in the A1 alloy film (C) is
As shown in Figure 5118, it is relatively small. Therefore, when depositing a silicon oxide film on top or bottom of an Al wiring, the higher the dangling bond density of silicon in the film, the greater the difference in the amount of stress change between the two during heat treatment. Since the stress can be reduced, stress migration of the A7 wiring can be reduced.

In this way, the interlayer insulating film 13 of this embodiment has a silicon oxide film 13a with high dangling bond density on the right side of the interface and in the vicinity of each of the first layer A1 wiring 12 and the second layer Al wiring 14. Since the interlayer insulating film 13 is formed
Stress migration of the Al arrangement 112.14 due to stress can be suppressed, and the reliability of the AJ wiring 12.14 can be improved.

In addition, in this example, since the interlayer insulating film is composed only of silicon oxide, the number of insulating film deposition steps is reduced compared to the conventional technology that attempts to reduce the stress applied to the Al wiring by making the interlayer insulating film a composite film. .

The table below shows A containing 0.7% silicon and 3% copper.
1 alloy (line width x film thickness x length = 3, Oμm x
Two types of silicon oxide films with different dangling bond densities (A.

The number of Δl chips (E
SR measurement data).

In the table, dangling bond density of silicon oxide film A = IX1
0"/crl, silicon oxide r!xB (7) Dangling bond density = 3X10"/C11! , the cooling rate is
1 = 0.1℃/min, II = 1.0℃/min, ■=
The temperature is 20°C/min.

Table 1 As is clear from the above table, the dangling bond density in the silicon oxide film is 3x10''/cj to 1x lQ
11 pieces/CIl! By increasing the number of AJs, the number of missing AJs has been significantly reduced.

As above, the invention made by the present inventor has been specifically explained based on Examples, but the present invention is not limited to the above-mentioned Examples, and it is understood that various changes can be made without departing from the gist thereof. Needless to say.

In the above example, the dangling bond density of silicon in the film was controlled by changing the etching rate ratio to the deposition rate of the silicon oxide film. Bond density can also be varied.

In the interlayer insulating films of the previous and examples, silicon oxide films with high dangling bond density were formed at and near the interfaces of the first-layer Al wiring and the second-layer Al wiring, but the interlayer insulating film The entire structure may be made of a silicon oxide film with high dangling bond density. However, in this case, there is a disadvantage that the dangling bond density of the entire film becomes high, and the characteristics of the film deteriorate. Furthermore, since the ratio of etching rate to film deposition rate must be increased over the entire film, the film deposition time also increases.

In the embodiments described above, the interlayer insulating film is made of silicon oxide, but the present invention can also be applied to a case where the interlayer insulating film is made of silicon nitride. In other words, even in the case of silicon nitride, there is a correlation between the amount of stress change in the film and the dangling bond density, and it is possible to reduce the stress applied to the Al wiring by increasing the dangling bond density in the film. can. In the case of a silicon nitride film, the density of silicon dangling bonds in the film must be at least lX101 pieces/cI11.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

(1) When depositing a silicon oxide film on the upper or lower layer of the /l wiring, by setting the silicon dangling bond density in the silicon oxide film to lXl0'1 piece/cd or more, the A1 wiring Since the stress applied to the silicon oxide film can be reduced, stress migration of the Al wiring can be suppressed.

(2) When depositing a silicon nitride film on the upper or lower layer of the A1 wiring, the above (1) can be achieved by setting the silicon dangling bond density in the silicon nitride film to lXl0'' pieces/cd or more. A similar effect can be obtained.

[Brief explanation of drawings]

1 to 5 are cross-sectional views of main parts of a semiconductor wafer showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention in order of steps. FIG. 6 is a bias sputtering apparatus used in this embodiment. 7 is a graph showing the temperature dependence of the compressive stress of the silicon oxide film deposited on the semiconductor wafer, and FIG. 8 is a graph showing the temperature dependence of the compressive stress of the A1 alloy film deposited on the semiconductor wafer. FIG. 1... Bias sputtering device, 2... Chamber, 3
... Argon gas supply source, 4... Vacuum pump, 5.
... Electrode, 6... Wafer jig, 7... Semiconductor wafer, 8... Counter electrode, 9... Target, 10...
High frequency power supply, 11...thermal oxide film, 12.14...A
l wiring, 13... interlayer insulating film, 13a, 13b...
Silicon oxide film. (XIO” Pa) (XIO’ Pa) Degree of diagram (”C)

Claims (1)

[Claims] 1. When depositing a silicon oxide film on the upper or lower layer of the aluminum wiring, the silicon dangling bond density in the silicon oxide film is set to 1×10^1^8 pieces/cm^3 or less. A method for manufacturing a semiconductor integrated circuit device characterized by the above steps. 2. A dangling bond density of silicon in the silicon oxide film at the interface with the aluminum wiring and in the vicinity thereof is set to 1×10^1^8 bonds/cm^3 or more. A method of manufacturing the semiconductor integrated circuit device described above. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1 or 2, wherein the silicon oxide film is deposited by bias sputtering. 4. When depositing a silicon nitride film on the upper or lower layer of the aluminum wiring, the silicon dangling bond density in the silicon nitride film is set to 1×10^1^7/cm^3 or more. A method for manufacturing a semiconductor integrated circuit device.