CN1244144C - Method for forming low dielectric constant dielectric layer and conductive interconnector structure - Google Patents
Method for forming low dielectric constant dielectric layer and conductive interconnector structure Download PDFInfo
- Publication number
- CN1244144C CN1244144C CN 02105938 CN02105938A CN1244144C CN 1244144 C CN1244144 C CN 1244144C CN 02105938 CN02105938 CN 02105938 CN 02105938 A CN02105938 A CN 02105938A CN 1244144 C CN1244144 C CN 1244144C
- Authority
- CN
- China
- Prior art keywords
- conductive
- insulating barrier
- layer
- dielectric constant
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Abstract
The present invention relates to a method for forming a dielectric layer with low dielectric constant, which comprises the steps: forming an insulation layer on a bottom layer; then, engraving the insulation layer in order to form an opening in the insulation layer; afterwards, forming a conductive layer on the insulation layer and backfilling the opening; flattening the conductive layer in order to form a conductive structure in the conductive layer; diffusing metal ions of the conductive layer in order to lead the metal ions to enter the insulation layer and reduce the dielectric constant of the insulation layer, wherein the conductive layer comprises materials containing cuprum, and the insulation layer comprises aromatic hydrocarbon polymer.
Description
Technical field
The present invention relates to a kind of method of making lead in the integrated circuit manufacturing, particularly, can be applicable to dual damascene manufacturing process about forming the method and the conductive interconnector structure of dielectric layer with low dielectric constant.
Background technology
When the aggregation degree of semiconductor element increased, the area of each memory cell can dwindle usually.For the area that makes memory cell dwindles, few techniques has been cited and has improved the performance of element, for example promotes the memory cell capacitance by the effective area that increases memory cell electric capacity.So-called stack electric capacity, ditching type capacitance structure and combination thereof for increasing the effective area of memory cell electric capacity, having developed.With dwindling of work component size, the manufacturing of integrated circuit has also faced many challenges.Each element all needs intraconnections.Electric signal between exchange component.Specifically, the line that dynamical integrated circuit has multilayer to isolate with dielectric layer, when the feature structure of circuit reduced, the demand that reduces the resistance of following electrically connect or contact hole can seem more important more in the past.
Many elements have the lead that can carry out some function, for example the DRAM cell memory cell indispensable bit line and storage node contact hole.Therefore, need dwindle the design rule of area and guarantee enough manufacturing process errors.The bit line of dynamic random access memory memory cell comprises one usually by insulating barrier and be connected to the metal wire of active area.Because of resistance and its sectional area of lead is inversely proportional to, along with the raising of the integration density of integrated circuit, the live width and the thickness of metal interconnecting all dwindle thereupon, so its resistance just improves thereupon; Especially bad, the raising along with the integration density of integrated circuit also makes the line-spacing of metal interconnecting dwindle thereupon, thereby causes the coupling capacitance between the lead to raise.Therefore after the manufacturing process of integrated circuit entered the deep-sub-micrometer field, the resistance-capacitance sluggishness of metal interconnecting significantly improved, and also therefore influenced the arithmetic speed and the access rate of integrated circuit.In order to improve the integration density of integrated circuit, the condition that all should not improve at live width and line-spacing following, the material of changing metal interconnecting and interlayer dielectric layer is best selection.
Aspect metal interconnecting, metal material changes the copper metal into by original Al-Si-Cu alloy or aluminium copper, except having low-resistance characteristic, have more good anti-electron transfer and good anti-stress, except the operation rate that can improve element, reliability that simultaneously can lift elements; On the other hand, interlayer dielectric layer then must select the material of low-k (Dielectric Constant) to replace original silicon dioxide, to reduce the coupling capacitance between the metal interconnecting.The dielectric constant of silicon dioxide is about 4.2, therefore must choose dielectric constant less than 4.2 dielectric medium as interlayer dielectric layer, can reach the effect that reduces the resistance-capacitance sluggishness, for example: fluorine doped silica (SiOF), organic spin-coating glass (HSQ) or the like.The material of another effective low-k is black diamond (blackdiamond), and it is formed by methyl-monosilane (methyl silane), and its composition is silicon 20%, oxygen 30%, carbon 9%, hydrogen 36%, reaches other elements.It is hole that 36% volume is arranged approximately because of black diamond, so the tool dielectric constant only is about 2.9, is a kind of low-k material of having very much potentiality.
In addition, doing in the process in copper is to make intraconnections or path, has developed the method that is called dual damascene (dualdamascene), and tool comprises the manufacturing process that relates to irrigation canals and ditches and bottom path.Irrigation canals and ditches and path are inserted conductive material simultaneously, therefore form intraconnections and metal bolt simultaneously.The relevant prior art of relevant dual damascene can be consulted the Boeck of motorola inc; People such as Bruce Allen are at No. the 5880018th, United States Patent (USP) disclosed " Method for manufacturing a low ielectric constant inter-levelintegrated circuit structure ".U.S. Patent No. 6140226, the invention people is people such as Grill, and denomination of invention is " Dual damascene processing for semiconductor chip interconnects ", and this patent relates to dual damascene manufacturing process.Another preceding case can be consulted U.S. Patent No. 6133140, and the invention people is people such as Yu, and denomination of invention is " method of manufacturing dual damascene utilizinganisotropic and isotropic properties ".The manufacturing process that another relevant two systems are inlayed is exposed in U.S. Patent No. 6077770.
Consulting Fig. 5, is a kind of typical dual-damascene structure shown in the figure.Comprise a underlying metal 22 in insulating barrier 20.One barrier layer 24 is positioned at the diffusion that prevents metal ion on the insulating barrier 20.One dielectric layer 26 is formed on the barrier layer 24, and as those who are familiar with this art as can be known, the dual-damascene structure of T type is formed among the dielectric layer 26, wherein inserts copper material 30.The dual-damascene structure surface that one barrier layer 28 also is formed at the T type intercepts between copper material and dielectric layer 26.
Summary of the invention
In view of the demand of low-k (low k) dielectric medium, the objective of the invention is to form the method for dielectric layer with low dielectric constant, can be applicable in the dual damascene manufacturing process.
Another object of the present invention is to utilize the mode of diffusion copper ion, form conductive interconnector structure.
A kind of conductive interconnector structure comprises: an insulating barrier is formed on the substrate, and above-mentioned insulating barrier comprises a underlying metal.One dielectric layer is formed on the above-mentioned insulating barrier, and above-mentioned dielectric layer comprises conductive structure and is formed among the above-mentioned dielectric layer.Wherein above-mentioned dielectric layer comprises ring-type hydrocarbon polymer (aromatichydrocarbon polymer).One metal ion diffusion zone is formed near the conductive structure, in order to reduce the dielectric constant of above-mentioned dielectric layer.The material that wherein above-mentioned conductive structure comprises dual-damascene structure and above-mentioned conductive structure comprises copper.Therefore, above-mentioned metal ion diffusion zone comprises the copper ion diffusion zone.
A kind of method that forms dielectric layer with low dielectric constant comprises and forms first insulating barrier on substrate, and first insulating barrier of etching afterwards is to form irrigation canals and ditches in wherein.Now forms first conductive layer on first insulating barrier, and the planarize conductive layer, to form conductive structure among irrigation canals and ditches.Follow-up formation second insulating barrier is on first insulating barrier.Form first and be opened among above-mentioned first insulating barrier, expose first conductive layer at least, and form one and be opened among above-mentioned second insulating barrier greater than second of above-mentioned first opening.Afterwards, backfill second conductive layer is in first opening and second opening, and then planarization second conductive layer is to form dual-damascene structure.Enter among second insulating barrier with the metal ion of thermal diffusion second conductive layer, in order to reduce its dielectric constant.
Effect provided by the present invention is and can therefore reduces coupling capacitance by the dielectric constant that reduces polarity and then reduction dielectric layer with low dielectric constant.And the present invention need not be with the barrier layer of physical vaporous deposition formation, and therefore having preferable copper fills out the ditch ability.As prior art as can be known, use barrier layer such as TaN, WN, Ta when dual-damascene structure, because of the higher and relatively poor gradient coating performance of the resistance on barrier layer.Therefore utilize the present invention not only not need the barrier layer, and the ditch of filling out that can improve resistance problems and be beneficial to copper.In addition, limited copper is spread in the macromolecule (polymer) of low-k and can reduces intermetallic leakage current (intra-metal leakage).
Description of drawings
Figure one is that the present invention forms the semiconductor substrate sectional view of path in dielectric layer;
Figure two is the semiconductor substrate sectional view of backfill conductive material of the present invention in two glass embedding structures;
Figure three is after the present invention carries out cmp, implements the semiconductor substrate sectional view of copper ion diffusion;
Figure four is the semiconductor substrate sectional view of another dual-damascene structure of the present invention;
Figure five is the semiconductor substrate sectional view of prior art dual-damascene structure.
The figure number explanation:
Embodiment
The present invention system is about a kind of method of utilizing dual damascene technology to make the intraconnections conductor structure.And the present invention also provides a kind of method that forms the low-k dielectric medium, and the present invention is applicable to any element.The method that the present invention forms dielectric layer with low dielectric constant comprises the formation insulating barrier on the bottom with conductive material, and etching isolation layer is opened on wherein with formation, continues to form conductive layer on insulating barrier.Planarize conductive layer afterwards is to form conductive structure among irrigation canals and ditches.The metal ion of diffusion conductive layer enters insulating barrier in order to reduce its dielectric constant.
Below will make an embodiment with the structure that is applied to form dual damascene, and see also shown in Figure 1ly, a wafer or substrate (not shown) are provided, the composition material of this wafer or substrate can be materials such as silicon, GaAs or germanium and forms.For example, in one embodiment, just use a crystal orientation＜100〉the crystal silicon substrate.Has one or more semiconductor element among this substrate.The lead of this element is not a theme of the present invention, so particular element or its function and the present invention there is no too big connection, so do not give unnecessary details.
One insulating barrier 2 (for example silica or silicon nitride) is formed on this substrate, and this silicon oxide layer is to form with thermal oxidation method in the aerobic environment on the typical case.In one embodiment, this silicon oxide layer is to form in the oxygen steam ambient of 800 to 1100 degree Celsius; Or this oxide layer is can be any suitable contains oxidation constituent and the formation of relative production process.The silicon nitride series of strata are with any suitable manufacturing process deposition, and for example Low Pressure Chemical Vapor Deposition (LPCVD), ion increase chemical vapour deposition technique (PECVD), high density Plasma-activated Chemical Vapor Deposition method (HDPCVD).The thickness of this silicon nitride layer is about 1000 to 2000 dusts.In a preferred embodiment, this reacting gas that forms the step of silicon nitride layer comprises SiH
4, NH
3, N
2, N
2O, SiH
2Cl
2, NH
3, N
2And N
2O.Then, form the pattern of insulating barrier 2 to define a plurality of irrigation canals and ditches among insulating barrier 2.One conductive material 4 be formed on the above-mentioned insulating barrier 2 and backfill among irrigation canals and ditches, continue and utilize a planarization manufacturing process that above-mentioned conductive material 4 parts are removed, generally can use chemical mechanical milling method, as shown in Figure 1.Continue formation etching stopping layer 6 and dielectric layer with low dielectric constant 8 in above-mentioned surface through grinding.Subsequent steps is for forming the step of conductive plugs.Usually comprise photoetching and etching step and reach above-mentioned purpose, earlier this forms opening or path (via hole) 9 in dielectric layer with low dielectric constant 8 because of need, and exposes the conductive material 4 of bottom.The composition of etching stopping layer 6 can comprise SiC or SiN.Dielectric layer with low dielectric constant 8 can be selected alleged ring-type hydrocarbon polymer (aromatichydrocarbon polymer) for use.Dielectric layer with low dielectric constant 8 also can be selected from other material.
Still see also Fig. 1, the opening that photoresist pattern 10 has a broad exposes passage opening 9, and as etched photomask, the control etching period is in the opening 11 of dielectric layer with low dielectric constant 8 etchings one broad with photoresist pattern 10.Remove photoresist pattern 10 afterwards.Consult Fig. 2, conductive material 12 is formed at then and reaches backfill on the dielectric layer with low dielectric constant 8 among opening 11,9.In like manner, conductive material 12 is removed with planarization mode such as chemical mechanical milling method.If conductive material 18 comprises copper, it should be noted that the present invention need not form adhesion layer and barrier layer in the surface of opening 11,9 in advance.
Consult Fig. 3, the copper ion that is embedded in the dual-damascene copper material in the dielectric layer with low dielectric constant 8 is diffused out dual-damascene structure, enter in the dielectric layer with low dielectric constant 8, and be distributed in dual-damascene structure near, but avoid excess diffusion and cause short circuit between dual-damascene structure.Copper is among ring-type hydrocarbon polymer (aromatichydrocarbon polymer), have very low diffusivity, can utilize ring-type hydrocarbon polymer (aromatic hydrocarbon polymer) BTS (bias temperature stress) mode to determine.Therefore can utilize heat treatment between 150-300 degree Celsius, copper ion to be spread.This heat treatment can be for carrying out an add-on step or the heat treatment of any subsequent step after forming dual damascene.
Figure 2 shows that the result after the diffusion, copper ion is distributed in the near zone of dual-damascene structure.Copper ion itself is nonpolarity (polarization), exists an amount of copper ion in dielectric layer with low dielectric constant 8, can reduce the polarity of dielectric medium.Polarity can cause the rising of dielectric constant, therefore can reduce dielectric constant by reducing polarity by nationality.And the present invention utilizes non-polar copper ion to diffuse among the dielectric layer with low dielectric constant 8, can reduce its polarity and reach the purpose that reduces dielectric constant.The present invention can utilize control temperature and time to reach suitable diffusion concentration and distributed areas (dotted line is represented).
Structure of the present invention comprises an insulating barrier 2, and is formed at underlying metal 4 in the insulating barrier 2.One etching stopping layer 6 is positioned on the insulating barrier 2.One dielectric layer with low dielectric constant 8 is formed on the etching stopping layer 6, and the dual-damascene structure of T type is formed among the dielectric layer 8, wherein inserts copper material 12.One copper ion diffusion zone forms near the T type dual-damascene structure, in order to reduce the dielectric constant of above-mentioned dielectric layer with low dielectric constant 8.
Fig. 4 is another embodiment of structure of the present invention, does not comprise the etching stopping layer 6 of first embodiment in this embodiment.Therefore, if the material of underlying metal 4 also is a copper, therefore the copper ion in the bottom material 4 can diffuse into zone, dielectric layer with low dielectric constant 8 bottom side via heating, increase the bottom section that copper ion is distributed in dual-damascene structure, increase distributed areas thus and then more reduce the dielectric constant of dielectric layer with low dielectric constant 8.
The above is preferred embodiment of the present invention only, is not in order to limiting claim scope of the present invention, and all other do not break away from the equivalence of being finished under the disclosed spirit and change or modify, and all should comprise within the scope of the claims.
Claims (8)
1, a kind of method that forms dielectric layer with low dielectric constant, this method comprises:
Form insulating barrier on bottom with conductive material;
This insulating barrier of etching is opened on wherein with formation;
Form conductive layer on this insulating barrier;
This conductive layer of planarization is to form conductive structure among this opening; And
The copper ion that spreads this conductive layer enters this insulating barrier in order to reduce its dielectric constant.
2, the method for formation dielectric layer with low dielectric constant as claimed in claim 1 is characterized in that: above-mentioned insulating barrier comprises the ring-type hydrocarbon polymer.
3, a kind of method that forms dielectric layer with low dielectric constant, this method comprises:
Form first insulating barrier on substrate;
This first insulating barrier of etching is to form irrigation canals and ditches in wherein;
Form first conductive layer on this first insulating barrier;
This conductive layer of planarization is to form conductive structure among these irrigation canals and ditches;
Form second insulating barrier on this first insulating barrier and this conductive structure;
Form first and be opened among above-mentioned first insulating barrier, expose this first conductive layer at least;
Formation one is opened among above-mentioned second insulating barrier greater than second of above-mentioned first opening;
Backfill second conductive layer is in this first opening and second opening;
This second conductive layer of planarization is to form dual-damascene structure;
The copper ion that spreads this second conductive layer enters this second insulating barrier in order to reduce its dielectric constant.
4, the method for formation dielectric layer with low dielectric constant as claimed in claim 3 is characterized in that: above-mentioned insulating barrier comprises the ring-type hydrocarbon polymer.
5, a kind of conductive interconnector structure comprises:
One dielectric layer is formed on the substrate, and described dielectric layer comprises conductive structure and is formed among the above-mentioned dielectric layer; And
One copper ion diffusion zone is formed near the conductive structure, in order to reduce the dielectric constant of above-mentioned dielectric layer.
6, conductive interconnector structure as claimed in claim 5 is characterized in that: above-mentioned conductive structure comprises dual-damascene structure.
7, conductive interconnector structure as claimed in claim 5 is characterized in that: the material of above-mentioned conductive structure comprises copper.
8, conductive interconnector structure as claimed in claim 5 is characterized in that: above-mentioned dielectric layer comprises the ring-type hydrocarbon polymer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02105938 CN1244144C (en) | 2002-04-09 | 2002-04-09 | Method for forming low dielectric constant dielectric layer and conductive interconnector structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02105938 CN1244144C (en) | 2002-04-09 | 2002-04-09 | Method for forming low dielectric constant dielectric layer and conductive interconnector structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1450624A CN1450624A (en) | 2003-10-22 |
| CN1244144C true CN1244144C (en) | 2006-03-01 |
Family
ID=28680109
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02105938 Expired - Lifetime CN1244144C (en) | 2002-04-09 | 2002-04-09 | Method for forming low dielectric constant dielectric layer and conductive interconnector structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1244144C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI707448B (en) * | 2018-05-14 | 2020-10-11 | 日商東芝記憶體股份有限公司 | Semiconductor device and manufacturing method thereof |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7670947B2 (en) * | 2007-01-11 | 2010-03-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Metal interconnect structure and process for forming same |
| JP5304536B2 (en) * | 2009-08-24 | 2013-10-02 | ソニー株式会社 | Semiconductor device |
| US9142517B2 (en) * | 2012-06-05 | 2015-09-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Hybrid bonding mechanisms for semiconductor wafers |
| JP2017537389A (en) * | 2014-11-07 | 2017-12-14 | ティ−タッチ・インターナショナル・ソシエテ・ア・レスポンサビリテ・リミテＴ−Ｔｏｕｃｈ Ｉｎｔｅｒｎａｔｉｏｎａｌ Ｓ．ａ．ｒ．ｌ． | Selective dielectric coating |
| US10515905B1 (en) * | 2018-06-18 | 2019-12-24 | Raytheon Company | Semiconductor device with anti-deflection layers |
-
2002
- 2002-04-09 CN CN 02105938 patent/CN1244144C/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI707448B (en) * | 2018-05-14 | 2020-10-11 | 日商東芝記憶體股份有限公司 | Semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1450624A (en) | 2003-10-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2814972B2 (en) | Method for manufacturing semiconductor device | |
| CN100442474C (en) | Method of manufacturing semiconductor device | |
| JP3583794B2 (en) | Method of forming an interconnect channel on a semiconductor substrate and semiconductor device | |
| US7679193B2 (en) | Use of AIN as cooper passivation layer and thermal conductor | |
| US20060097397A1 (en) | Method for forming a dual layer, low resistance metallization during the formation of a semiconductor device | |
| EP2356674B1 (en) | Dual metal interconnects | |
| US7189615B2 (en) | Single mask MIM capacitor and resistor with in trench copper drift barrier | |
| JP5039267B2 (en) | Capacitor structure and method for manufacturing the same in a dual damascus process | |
| US6274923B1 (en) | Semiconductor device and method for making the same | |
| US8212330B2 (en) | Process for improving the reliability of interconnect structures and resulting structure | |
| JP3481965B2 (en) | Method of forming integrated circuit submicron contact and structure forming part of semiconductor device | |
| US6870263B1 (en) | Device interconnection | |
| CN1244144C (en) | Method for forming low dielectric constant dielectric layer and conductive interconnector structure | |
| CN1114942C (en) | Method for forming contact plugs and simultaneously planarizing substrate surface in integrated circuit | |
| KR100434508B1 (en) | Method for forming metal interconnection layer of semiconductor device using modified dual damascene process | |
| JP2001284355A (en) | Semiconductor device and its manufacturing method | |
| US20060076682A1 (en) | Advanced copper damascene structure | |
| EP0834920A1 (en) | Improvements in or relating to semiconductor device metallization and interconnects | |
| JPH10116906A (en) | Manufacture of semiconductor device | |
| KR100373357B1 (en) | Method for forming wiring using multi-step sputtering of aluminum in semiconductor device | |
| Kikkawa et al. | Quarter-Micron Interconnection Technologies for 256-Mbit Dynamic Random Access Memories | |
| KR100273905B1 (en) | Poly-aluminum exchange for aluminum fill of high aspect ratio shapes | |
| KR100753132B1 (en) | Method for fabricating metal line using dual damascene | |
| KR20100043906A (en) | Method for manufacturing semiconductor device using local interconnect | |
| KR20020068132A (en) | Copper barrier layer for copper layer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term |
Granted publication date: 20060301 |
|
| CX01 | Expiry of patent term |