CN107611012B

CN107611012B - Stress control method and structure of prefabricated back film

Info

Publication number: CN107611012B
Application number: CN201710775897.9A
Authority: CN
Inventors: 姚兰; 吕震宇; 陈俊; 胡思平; 戴晓望; 朱继锋; 肖莉红; 郑阿曼; 鲍琨; 杨号号; 朱紫晶; 罗世金; 肖攀
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2017-08-31
Filing date: 2017-08-31
Publication date: 2020-10-02
Anticipated expiration: 2037-08-31
Also published as: CN107611012A

Abstract

The invention relates to a stress control method and a structure of a prefabricated back film, wherein the method comprises the following steps: forming one or more stress films on the back of the wafer; forming a semiconductor device layer on the front surface of the wafer; the wafer bow is balanced to a level by intermittently removing or thinning all or a portion of the one or more stress films on the wafer backside. By adopting the stress control method and the structure of the prefabricated back film, stress change can be better controlled, so that the wafer is always in a smaller deformation state in the process, and the process capability and the quality are improved.

Description

Stress control method and structure of prefabricated back film

Technical Field

The invention relates to a stress control method and structure of a prefabricated back film, and relates to the technical field of 3D NAND memory manufacturing.

Background

The degree of wafer warpage (warp) has a significant effect. During the baking step, the warpage of the wafer will cause the photoresist covering the wafer to be heated unevenly, which will eventually affect the CD. The data shows that wafer warpage results in a 31% deviation for the gate CD and a 62% deviation for the contact hole layer CD. In addition, for some special products, such as backside-illuminated cis (cmos Image sensor) chips, the front side of the wafer needs to be bonded to the supporting wafer before the back side of the wafer is thinned, so that the warpage of the wafer is also strictly required.

Generally, when the wafer is warped, the wafer will have a bowl-shaped warped state as a whole, i.e., the warped wafer will have the edge higher than the center thereof to form a bowl shape, so that a gap is formed between the edge of the wafer and the horizontal plane. Generally, the warp of the wafer can be adjusted by depositing a stress film. For example, a compressive stress film, such as a silicon nitride film, may be deposited on the bowl-shaped warped wafer, and the warpage of the wafer is reduced by the stress effect generated by the stress film. The improvement degree of the wafer warping is positively correlated with the stress generated by the deposited stress film.

When a silicon nitride film with larger compressive stress is used, the improvement degree of the warping of the wafer in the X-axis direction is obviously improved.

However, we have found that there is a significant difference in the degree of warpage of the wafer in different directions at X, Y. The detection data show that even a bare wafer (barewafer) has a significant difference in the warpage degree in the X, Y direction, for example, the difference in the warpage degree of the bare wafer in the X, Y direction reaches 38 μm in one actual measurement; in one actual measurement on a patterned wafer (structured wafer), the degree of warpage in the X direction was 184 μm, the degree of warpage in the Y direction was 214 μm, and there was a difference of 30 μm.

From the above experimental data, it can be seen that the warpage in the overall direction of the wafer can be improved by the deposition of the stress film, but the significant difference existing after the warpage is improved in the X, Y direction cannot be controlled. Since the general warpage specification requires that the absolute value of the warpage of the whole wafer product is less than 20 μm, it is difficult to ensure that the warpage of the wafer in all directions can be kept within a limited specification range by the deposition method of the stress film.

With the development of 3D NAND technology, stress control of wafers is more and more important. In the traditional process, the stress in the process is mainly balanced by the growth and removal of various films in the main process flow.

For example, as shown in fig. 1, chinese patent application No. 201610186873.5 discloses a method for improving wafer warpage, which comprises depositing a stress film 21 on a wafer 20, patterning the wafer by photolithography, protecting the stress film in a specific region with a photoresist 22, and performing ion implantation on the wafer 20 to release the stress in the specific direction, so as to adjust the warpage in the specific direction of the wafer in a targeted manner, thereby controlling the entire warpage of the wafer within a reasonable range.

However, due to the influence of the process target structure such as step thickness and device density, the selection of the thickness growth mode of the thin film of the above patent is greatly limited, resulting in limited effect of process stress control, and often causing problems such as stress bending. In addition, the above patent requires steps such as photoresist and ion implantation, and the process is complicated.

Disclosure of Invention

The invention discloses a novel method for controlling stress in a technological process, which can customize a back stress film with required stress change in advance, and selectively remove or thin in the intermediate process to achieve the aim of balancing the intermediate stress of the process.

Specifically, the invention provides a stress control method for a prefabricated back film, which comprises the following steps:

forming one or more stress films on the back of the wafer;

forming a semiconductor device layer on the front surface of the wafer;

the wafer bow is balanced to a level by intermittently removing or thinning all or a portion of the one or more stress films on the wafer backside.

Preferably, the one or more stressed films are formed by a Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD) process.

Preferably, the one or more stress films are silicon nitride and/or silicon oxide films.

Preferably, the thickness of the silicon nitride and/or silicon oxide film may be between 500-2000 angstroms.

Preferably, the method further comprises, during the forming, performing ion implantation on the one or more silicon nitride and/or silicon oxide films.

Preferably, the ion implantation is N ion implantation or P ion implantation.

Preferably, the semiconductor device layer is a peripheral device and/or an array device.

Preferably, the semiconductor device layer is formed by a Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD) process.

Preferably, the removing or thinning process employs grinding or mechanical polishing.

In particular, the invention also provides a memory, which comprises the stress control structure prepared according to the method.

By adopting the novel method, the stress change can be better controlled, so that the wafer is always in a smaller deformation state in the process, and the process capability and quality are improved.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

fig. 1 is a schematic diagram illustrating a conventional method for improving wafer warpage.

FIG. 2 is a schematic diagram of a step of a method for controlling stress of a pre-fabricated back side film according to the present invention;

FIG. 3 is a diagram illustrating a second step of the method for controlling stress of a pre-fabricated backside film according to the present invention;

FIG. 4 is a schematic diagram of the third step of the method for controlling the stress of the prefabricated back surface film according to the present invention.

Detailed Description

Embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Like reference numerals refer to like elements throughout the specification.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element is referred to as being "on," "connected to" or "coupled to" another element, it can be directly on or connected or coupled to the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" or "directly coupled to" another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between," "adjacent" with respect to "directly adjacent," etc.). When an element is referred to herein as being "on" or "under" another element, it can be directly coupled to the other element, or intervening elements may be present, or the elements may be separated by gaps or spaces.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

The method comprises the following steps:

s1, as shown in fig. 2, one or more stress films are initially formed sequentially on the back side of the wafer 1 by line-down of the wafer. In the embodiment shown in fig. 2,

different stress films

2, 3, 4 are formed, and the entire wafer is made horizontal by the stress balance of the various stress films.

Preferably, the wafer is a silicon substrate.

Preferably, the various stressed thin films may be formed by a Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD) process.

Preferably, a stress film is deposited on the back side of the wafer by a conventional process, for example, one or more layers of stressed silicon nitride and/or silicon oxide films may be deposited. The improvement of the wafer warpage is positively correlated with the magnitude of stress generated by the deposited silicon nitride and/or silicon oxide film. Also, the greater the stress of the silicon nitride and/or silicon oxide film, the thinner the required deposition thickness. In embodiments of the present invention, the thickness of the silicon nitride and/or silicon oxide film may be between 500 and 2000 angstroms.

Preferably, one or more of the silicon nitride and/or silicon oxide films may be ion implanted during formation, such as N ion implantation, using conventional techniques.

It is understood that other auxiliary films, such as shallow trench isolation layers, stop layers of the CMP process, etc., may be disposed on the wafer, and the auxiliary films do not substantially affect the forming method of the embodiment and do not belong to the invention of the present invention, so that the present embodiment is not described in detail.

S2, as shown in fig. 3, a semiconductor device layer 5 is formed on the front surface of the wafer according to the process. The semiconductor device layer 5 is a structure or a device deposited on a silicon substrate when manufacturing in a 3D NAND memory. Peripheral devices such as CMOS, or array devices, etc. Step S2 is a conventional process in the art, and is not the point of the invention, and therefore, the description of this embodiment is omitted. Preferably, the various semiconductor device layers may be formed by a Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD) process. Chemical Vapor Deposition (CVD) is the most widely used technique in the semiconductor industry for depositing a variety of materials, including a wide range of insulating materials, most metallic materials and metal alloy materials. Theoretically, it is simple: two or more gaseous starting materials are introduced into a reaction chamber and then chemically react with each other to form a new material that is deposited on the wafer surface. A good example is the deposition of a silicon nitride film (Si3N4) which is formed by the reaction of silane and nitrogen. The Physical Vapor Deposition (PVD) technique is a technique of vaporizing a material source, i.e., a solid or liquid surface, into gaseous atoms, molecules or partially ionized ions by a Physical method under a vacuum condition, and depositing a thin film having a specific function on a substrate surface by a low-pressure gas (or plasma) process. The main methods of physical vapor deposition include vacuum evaporation, sputter coating, arc plasma coating, ion coating, and molecular beam epitaxy. The physical vapor deposition technique can deposit not only a metal film, an alloy film, but also a compound, a ceramic, a semiconductor, a polymer film, and the like.

S3, the bow is balanced back to level by intermittently removing or thinning all or a portion of the particular stressed film 4 on the wafer backside.

Preferably, at this step, as shown in fig. 4, all or a part of the specific stress film 4 on the back side of the wafer may be removed first, and then all or a part of the stress film 3 may be thinned, so that the balance is completely leveled.

Preferably, the removing or thinning process is grinding or mechanical polishing, and the like, and the processes do not substantially affect the forming method of the embodiment and do not belong to the invention point of the present invention, so the present embodiment is not described in detail. Thinning may be by, for example, grinding and/or etching or by an ion cutting process followed by Chemical Mechanical Polishing (CMP). A chemical mechanical polishing process is a processing method using the polishing principle of solid phase reaction, namely, a mixture containing abrasive and a polishing pad are used for polishing the surface of an integrated circuit.

In summary, the stress film is deposited on the back surface of the wafer, the back surface stress film with the required stress variation is customized in advance, and the selective removal or thinning is performed in the intermediate process, so that the intermediate stress of the process is balanced, the stress in the specific direction is released, the warping degree of the wafer in the specific direction can be adjusted in a targeted manner, and the overall warping degree of the wafer is controlled within a reasonable range.

The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims

1. A method of stress control of a prefabricated backside film, said method comprising the steps of:

forming one or more stress films on the back of the wafer; the one or more layers of stress films are silicon nitride films and/or silicon oxide films; in the forming process, ion implantation is carried out on one or more layers of silicon nitride and/or silicon oxide films;

forming a semiconductor device layer on the front surface of the wafer; the semiconductor device layer is a peripheral device and/or an array device;

the bow of the wafer is balanced to a level by intermittently thinning all or a portion of the one or more stress films on the back side of the wafer.

2. The method of claim 1, wherein:

the one or more stressed films are formed by a Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD) process.

3. The method of claim 1, wherein:

the ion implantation is N ion implantation or P ion implantation.

4. The method of claim 1, wherein:

the semiconductor device layer is formed by a Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD) process.

5. The method of claim 1, wherein:

the thinning process adopts grinding or mechanical polishing.

6. A memory comprising a stress-controlling structure prepared according to the method of any one of claims 1-5.