CN110718449A - Deposition method of wafer back side film structure and wafer back side film structure - Google Patents
Deposition method of wafer back side film structure and wafer back side film structure Download PDFInfo
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- CN110718449A CN110718449A CN201910922989.4A CN201910922989A CN110718449A CN 110718449 A CN110718449 A CN 110718449A CN 201910922989 A CN201910922989 A CN 201910922989A CN 110718449 A CN110718449 A CN 110718449A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67288—Monitoring of warpage, curvature, damage, defects or the like
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
Abstract
The embodiment of the invention discloses a deposition method of a wafer back surface film structure, which comprises the following steps: forming a first thin film structure covering a first area on the back surface of the wafer by adopting a first deposition process; forming a second thin film structure covering a second area at the edge position of the back of the wafer by adopting a second deposition process; and the first area and the second area are overlapped and then cover the whole area of the back surface of the wafer. In addition, the embodiment of the invention also discloses a wafer back surface film structure prepared and formed by the method provided by the embodiment of the invention.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a deposition method of a wafer back surface film structure and the wafer back surface film structure.
Background
Memory (Memory) is a Memory device used in modern information technology to store information. With the increasing demands of various electronic devices for integration and data storage density, it is increasingly difficult for a common two-dimensional memory device to meet the demands, and in such a situation, a three-dimensional (3D) memory has come into play.
In the chemical vapor deposition process of the 3D NAND memory, the excessive warpage (bow value) of the wafer may cause the capacitive reactance impedance of the plasma in the deposition process to be abnormal, which is easy to generate arc discharge (arc), and seriously affects the hardware maintenance of the machine and the improvement of the product yield. Therefore, the control wafer bow value has great economic benefit and research value within a reasonable range.
Currently, in actual production and process development, depositing a SiN film on the back side (back side) of a wafer is an effective way to change the value of the wafer bow. However, since the cleaning condition of the wafer Back is generally poor, a wafer edge (wafer edge) cannot be deposited to form a film when a Back-side-deposition (BSD) SiN film is deposited, and the BSD SiN film is easily peeled and peeled off at the wafer edge in a high-temperature and low-pressure environment. Therefore, the improvement of the peeling and falling problems of the BSD SiN film has great significance on the improvement of the semiconductor integration process.
Disclosure of Invention
In view of the above, the main objective of the present invention is to provide a deposition method for a wafer backside film structure and a wafer backside film structure.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
the embodiment of the invention provides a deposition method of a wafer back surface film structure, which comprises the following steps:
forming a first thin film structure covering a first area on the back surface of the wafer by adopting a first deposition process;
forming a second thin film structure covering a second area at the edge position of the back of the wafer by adopting a second deposition process;
and the first area and the second area are overlapped and then cover the whole area of the back surface of the wafer.
In the above scheme, the second region is annular, and the diameter of the annular outer ring is greater than or equal to the diameter of the wafer.
In the above scheme, the first thin film structure and the second thin film structure form a stress adjustment structure of the wafer.
In the above scheme, the material of the first thin film structure and the second thin film structure includes silicon nitride.
In the above scheme, the first deposition process and the second deposition process are performed by using the same machine, or performed by using different machines.
In the above scheme, in the first deposition process, the wafer contacts a machine performing the first deposition process through a first position; in the second deposition process, the wafer is contacted with a machine table for executing the second deposition process through a second position; the first position is not coincident with the second position.
In the above solution, the first position includes a position extending from the edge of the wafer to the center of the wafer by a first distance; the second area is annular, and the annular width is greater than or equal to the first distance.
In the above scheme, the second thin film structure formed by the second deposition process further covers the end face of the wafer and covers a partial area at the edge position of the front surface of the wafer.
The embodiment of the invention also provides a wafer back surface film structure, and the film structure is prepared by the method in any one of the schemes.
According to the deposition method of the wafer back surface film structure and the wafer back surface film structure provided by the embodiment of the invention, on one hand, the method comprises the following steps: forming a first thin film structure covering a first area on the back surface of the wafer by adopting a first deposition process; forming a second thin film structure covering a second area at the edge position of the back of the wafer by adopting a second deposition process; the first area and the second area are overlapped and then cover the whole area of the back of the wafer; on the other hand, the wafer back surface film structure is prepared and formed through the method provided by the embodiment of the invention. Therefore, on the basis of depositing the film structure on the back of the traditional wafer, a second deposition process is added, namely, the deposition process aiming at the wafer edge is executed again, the defect that the film structure with the required thickness cannot be deposited at the wafer edge position due to self cleaning conditions, machine hardware conditions (hardware) and the like is overcome through the combination of the two processes, the second film structure formed in the second area at the wafer edge position has good adhesion with the first film structure formed in the first area, and the risk that the film structure is peeled and falls off from the back of the wafer can be greatly reduced; while not adversely affecting the balance stress provided by the thin film structure to the wafer.
Drawings
FIG. 1 is a cross-sectional view illustrating a structure of forming a SiN film on a backside of a wafer according to the related art;
FIG. 2 is an electron microscope image of a SiN film peeling structure in the related art;
FIG. 3 is a schematic flowchart illustrating a deposition method of a thin film structure on the back surface of a wafer according to an embodiment of the present invention;
FIG. 4 is a schematic cross-sectional view of a wafer backside film structure according to an embodiment of the present invention;
fig. 5 is a schematic cross-sectional view illustrating a film structure on the back surface of a wafer according to another embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. And the discussion of a second element, component, region, layer or section does not necessarily imply that a first element, component, region, layer or section is present in the invention.
Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
FIG. 1 is a cross-sectional view illustrating a structure of forming a SiN film on a backside of a wafer according to the related art. As shown in the figure, the SiN thin film 11 formed on the back surface of the wafer 10 by only one BSD process in the related art is prone to peeling and peeling in a subsequent high-temperature and low-pressure environment, which is especially obvious at the wafer edge pointed by the finger in the figure.
FIG. 2 is an electron microscope image of a SiN film exfoliation structure in the related art. In the actual production process, a plurality of wafers usually participate in production and preparation at the same time, and if the film structure falls off from the back surface of the wafer positioned on the upper layer, the upper surface of the wafer on the lower layer is possibly polluted, so that the defect density of the wafer on the lower layer is high. The peeling and falling off problem of the thin film structure on the back surface of the wafer is common, which has adverse effect on the integration process of the semiconductor.
Based on this, the embodiment of the invention provides a deposition method of a wafer back surface film structure; please refer to fig. 3. As shown, the method comprises the steps of:
and the first area and the second area are overlapped and then cover the whole area of the back surface of the wafer.
It can be understood that, in the embodiment of the present invention, on the basis of the conventional wafer back side deposition film structure, a second deposition process is added, that is, the deposition process for the wafer back side edge position is performed again, and through the combination of the two processes, the defect that the film structure with the required thickness cannot be deposited at the wafer back side edge position due to the self-cleaning condition, the machine hardware condition, and the like is made up, and the second film structure formed at the wafer back side edge position in the second area and the first film structure formed in the first area have good adhesion, so that the risk of peeling and falling off of the film structure from the wafer back side can be greatly reduced, and the problem of high defect density of the lower layer wafer caused by falling of the film structure to the lower layer wafer is prevented; while not adversely affecting the balance stress provided by the thin film structure to the wafer.
Fig. 4 is a schematic cross-sectional view illustrating a wafer backside film structure prepared by the method according to an embodiment of the present invention. As shown, the wafer backside thin film structure is formed to include the first thin film structure 311 and the second thin film structure 312; wherein the first thin film structure 311 covers a first area of the back surface of the wafer 30, where the first area includes most of the area of the back surface of the wafer; the second thin-film structure 312 covers a second area at the edge position of the back side of the wafer 30, where the second thin-film structure 312 at least covers the second area, but the second thin-film structure 312 may of course also be formed in other predetermined areas during the second deposition process, for example, at the end face of the wafer 30, or even at the predetermined area of the front side of the wafer 30.
In one embodiment, the second region is annular, and the outer diameter of the annular is greater than or equal to the diameter of the wafer 30.
The material of the wafer 30 may include at least one of: silicon (Si), Germanium (Ge), Silicon Germanium (SiGe), Silicon On Insulator (SOI), Germanium On Insulator (Germanium On Insulator), and the like; in one embodiment, the wafer 30 is a single crystal silicon wafer. The wafer 30 has a front side for forming semiconductor devices (e.g., 3D NAND memory) and a back side. In executing the steps of the method provided in this embodiment, the wafer 30 may be a wafer without any process, or may be a semi-finished wafer after being processed by multiple semiconductor processing processes (e.g., plating, photolithography, deposition, grinding, etc.); that is, a semiconductor device, a dielectric layer, and the like, which are not shown, may be included in fig. 4.
The materials of the first thin film structure 311 and the second thin film structure 312 may be the same, and the process conditions of the first deposition process and the second deposition process may also be the same; thus, the first thin-film structure 311 and the second thin-film structure 312 are only thin-film structures formed on the back surface of the wafer 30 in two steps, and there is no difference therebetween.
In one embodiment, the first thin film structure and the second thin film structure constitute a stress adjustment structure of the wafer. The first thin film structure and the second thin film structure exert stress on the back of the wafer, so that the stress generated by deposition of various material layers on the upper surface of the wafer in the process is balanced, the bow value of the wafer is effectively changed, and the wafer is prevented from warping.
In one embodiment, the material of the first thin film structure and the second thin film structure includes silicon nitride.
In addition, as a wafer back surface film structure, the first film structure and the second film structure may also constitute other functional layer structures such as a protective layer and a dielectric layer of the wafer. The material of the first thin film structure and the second thin film structure is not limited to silicon nitride, and may further include at least one of the following: silicon oxide, silicon oxynitride, polysilicon, amorphous carbon, aluminum oxide.
The first deposition process and the second deposition process may be chemical vapor deposition processes. In practical applications, the first deposition process and the second deposition process are performed by using the same machine, or performed by using different machines.
In one embodiment, in the first deposition process, the wafer is in contact with a machine performing the first deposition process through a first location; in the second deposition process, the wafer is contacted with a machine table for executing the second deposition process through a second position; the first position is not coincident with the second position. Therefore, in the second deposition process, the influence of the machine hardware condition in the first deposition process on the deposition position of the film structure on the back surface of the wafer is compensated, and the full coverage of the film structure on the back surface of the wafer is realized through two deposition processes.
In one embodiment, the first location comprises a location extending a first distance from an edge of the wafer toward a center of the wafer; the second area is annular, and the annular width is greater than or equal to the first distance. It is understood that the second region in the second deposition process can be dynamically adjusted according to the actual situation of the first deposition process, so that the deposition of the thin film structure is completed through the cooperation of the second deposition process and the first deposition process.
In another embodiment of the present invention, the second thin film structure formed by the second deposition process further covers the end surface of the wafer and covers a partial area of the front surface edge of the wafer. FIG. 5 is a schematic cross-sectional view illustrating a thin film structure on the back surface of a wafer in the present embodiment; as shown, a first thin film structure 411 covering a first region of the back surface of the wafer 40 is formed by a first deposition process; forming a second thin film structure 412 covering a second area at the edge position of the back side of the wafer 40 by using a second deposition process; wherein, during the second deposition process, the second thin film structure 412 is further deposited on the end face of the wafer 40 and a partial area at the edge position of the front face of the wafer 40; therefore, the film structure for coating the wafer can be formed in the second deposition process, so that the wafer is protected from being exposed, and the working stability of the device is improved; the second deposition process is synchronously completed, so that the process steps can be saved, and the production cost can be reduced.
On the basis, the embodiment of the invention also provides a wafer back surface film structure, and the film structure is prepared and formed by the method in any one of the schemes. Fig. 4 and fig. 5 are schematic cross-sectional views of a wafer backside film structure according to an embodiment and another embodiment of the invention. Therefore, the formed film structure is not easy to peel off or fall off from the back of the wafer in the high-temperature and low-pressure environment of the subsequent process.
The above description is only exemplary of the present invention and should not be taken as limiting the scope of the present invention, and any modifications, equivalents, improvements, etc. that are within the spirit and principle of the present invention should be included in the present invention.
Claims (9)
1. A method for depositing a thin film structure on a backside of a wafer, the method comprising:
forming a first thin film structure covering a first area on the back surface of the wafer by adopting a first deposition process;
forming a second thin film structure covering a second area at the edge position of the back of the wafer by adopting a second deposition process;
and the first area and the second area are overlapped and then cover the whole area of the back surface of the wafer.
2. The method of claim 1, wherein the second region is annular in shape, and an outer diameter of the annular shape is equal to or greater than a diameter of the wafer.
3. The method of claim 1, wherein the first thin film structure and the second thin film structure constitute a stress adjustment structure of the wafer.
4. The method of claim 1, wherein the material of the first thin film structure and the second thin film structure comprises silicon nitride.
5. The method of claim 1, wherein the first deposition process and the second deposition process are performed using the same tool or different tools.
6. The method of claim 1, wherein in the first deposition process, the wafer is in contact with a tool performing the first deposition process through a first location; in the second deposition process, the wafer is contacted with a machine table for executing the second deposition process through a second position; the first position is not coincident with the second position.
7. The method of claim 6, wherein the first position comprises a position extending a first distance from an edge of the wafer toward a center of the wafer; the second area is annular, and the annular width is greater than or equal to the first distance.
8. The method of claim 1, wherein the second film structure formed by the second deposition process further covers the end surface of the wafer and covers a portion of the edge of the front surface of the wafer.
9. A wafer backside film structure formed by the method of any of claims 1 to 8.
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| TW200307996A (en) * | 2002-04-26 | 2003-12-16 | Accretech Usa Inc | Method and apparatus for shaping thin films in the near-edge regions of in process semiconductor substrates |
| US7572737B1 (en) * | 2006-06-30 | 2009-08-11 | Lam Research Corporation | Apparatus and methods for adjusting an edge ring potential substrate processing |
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