CN106298922A - Transistor and forming method thereof - Google Patents
Transistor and forming method thereof Download PDFInfo
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- CN106298922A CN106298922A CN201510293280.4A CN201510293280A CN106298922A CN 106298922 A CN106298922 A CN 106298922A CN 201510293280 A CN201510293280 A CN 201510293280A CN 106298922 A CN106298922 A CN 106298922A
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 239000000758 substrate Substances 0.000 claims abstract description 113
- 239000000463 material Substances 0.000 claims description 84
- 238000005530 etching Methods 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 238000001020 plasma etching Methods 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 238000000576 coating method Methods 0.000 claims description 4
- 239000012159 carrier gas Substances 0.000 claims description 3
- 239000003795 chemical substances by application Substances 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 239000011248 coating agent Substances 0.000 claims description 3
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 3
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims 1
- 239000002023 wood Substances 0.000 claims 1
- 230000009286 beneficial effect Effects 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 228
- 238000002955 isolation Methods 0.000 description 21
- 229910052751 metal Inorganic materials 0.000 description 17
- 239000002184 metal Substances 0.000 description 17
- 229910021332 silicide Inorganic materials 0.000 description 17
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 17
- 230000000694 effects Effects 0.000 description 16
- 239000011241 protective layer Substances 0.000 description 12
- 239000010409 thin film Substances 0.000 description 9
- -1 boron ion Chemical class 0.000 description 8
- 239000010408 film Substances 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 8
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000001105 regulatory effect Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000001276 controlling effect Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000003667 anti-reflective effect Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2229/00—Indexing scheme for semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, for details of semiconductor bodies or of electrodes thereof, or for multistep manufacturing processes therefor
Abstract
The present invention provides a kind of transistor and forming method thereof, described forming method is included on described grid structure top and sidewall and substrate formation compressive stress thin layer, compressive stress thin layer on described substrate mainly provides the compressive stress along channel width dimension to channel region, and the compressive stress thin layer on described grid structure top and sidewall mainly provides the compressive stress of vertical-channel width to channel region.By adjusting the thickness of compressive stress thin layer on the thickness of compressive stress thin layer on described substrate and described grid structure top and sidewall, make the combined stress direction that described channel region is provided by described compressive stress thin layer closer to channel width dimension, the effective stress applying channel region is bigger, it is more beneficial for improving the carrier mobility of channel region, thus improves the electrical property of transistor.
Description
Technical field
The present invention relates to semiconductor applications, be specifically related to a kind of transistor and forming method thereof.
Background technology
In semiconductor applications, transistor is arranged stressor layers can to channel region provide tensile stress or
It is compression stress, thus reaches to improve the effect of cmos device carrier mobility, and then improve transistor
Performance.
Such as: in the substrate that PMOS transistor source region is corresponding with drain region, form groove, then at described groove
Middle epitaxial growth Ge silicon layer, carries out ion implanting and forms source region and drain region, described germanium silicon described germanium silicon layer
The raceway groove of layer energy pair pmos transistor applies compressive stress.In order to further enhance the ditch of pair pmos transistor
The compressive stress in road, prior art proposition is a kind of forms compressive stress thin layer on grid structure and substrate
Mode, increases the compressive stress to raceway groove.
With reference to Fig. 1, it is shown that the schematic diagram of a kind of PMOS transistor applying stress technique of prior art.
Shallow trench isolation 02 it is formed with, with by PMOS transistor and other adjacent NMOS crystal in substrate 01
Pipe or PMOS transistor isolation, be formed with grid structure 05 on substrate 01.At described grid structure 05
Being formed with source region 03 and drain region 04 in the substrate 01 of both sides, described source region 03 and drain region 04 are for enter germanium silicon layer
Row ion implanting is formed, and the substrate 01 between source region 03 and drain region 04 is as the channel region of PMOS transistor.
Described source region 03 and drain region 04 are also formed with metal silicide layer 07, at described metal silicide layer 07
Upper formation is to conductive plunger (not shown).On described substrate 01, metal silicide layer 07 and grid
Being formed with compressive stress thin layer 06 on the top of structure 05 and sidewall, described compressive stress thin layer 06 uses energy
The material enough providing compressive stress is made.Described compressive stress thin layer 06 can be the channel region of PMOS transistor
Compressive stress is provided.
But, the useful effect power that prior art compressive stress thin layer provides to transistor channel region is less,
It is difficult to meet the requirement improving transistor performance.
Summary of the invention
The problem that the present invention solves is to provide a kind of transistor and forming method thereof, improves compressive stress thin layer
Useful effect power to transistor channel region, and then improve the performance of transistor.
For solving the problems referred to above, the present invention provides a kind of transistor and forming method thereof, including:
Substrate is provided；
Form grid structure over the substrate；
Source region and drain region is formed in the substrate of described grid structure both sides；
Described grid structure top and sidewall and substrate are formed compressive stress thin layer, is positioned at described lining
, the thickness of compressive stress thin layer is more than the thickness of compressive stress thin layer on described grid structure top and sidewall at the end
Degree.
Optionally, described grid structure top and sidewall and substrate form compressive stress thin layer, position
Compressive stress thin film layer thickness on described substrate is more than the compressive stress on described grid structure top and sidewall
The step of thin film layer thickness includes:
Described grid structure top and sidewall and substrate are formed compressive stress material layer；
Covering anti-reflecting layer on described compressive stress material layer, the upper surface of described anti-reflecting layer is higher than described
The top of grid structure；
Etch described anti-reflecting layer, and remove the compressive stress material layer of described grid structure upper part thickness,
Remaining compressive stress material layer forms compressive stress thin layer；
Remove remaining described anti-reflecting layer.
Optionally, described grid structure top and sidewall and substrate are formed the step of compressive stress material layer
In Zhou, chemical vapour deposition technique is used to form described compressive stress material layer.
Optionally, described grid structure top and sidewall and substrate are formed the step of compressive stress material layer
In Zhou, the thickness of described compressive stress material layer is in the range of 50 to 2000 angstroms.
Optionally, the step covering anti-reflecting layer on described compressive stress material layer includes: use coating
Method forms described anti-reflecting layer.
Optionally, the method etching described anti-reflecting layer is plasma etching method.
Optionally, the etching agent that described plasma etching method uses includes: CF4、CH3F、HBr、NF3、
Cl2、O2And N2In one or more, carrier gas includes one or more in Ar and He.
Optionally, described grid structure top and sidewall and substrate form compressive stress thin layer, position
Compressive stress thin film layer thickness on described substrate is more than the compressive stress on described grid structure top and sidewall
The step of thin film layer thickness includes:
On described substrate, the thickness of compressive stress thin layer is in the range of 50 to 2000 angstroms, and described grid is tied
The thickness of the compressive stress thin layer on structure top and sidewall is within 1000 angstroms；
Optionally, described grid structure top and sidewall and substrate are formed the step of compressive stress thin layer
Suddenly include:
The material of described compressive stress thin layer is silicon nitride.
The present invention also provides for a kind of transistor, including:
Substrate；
It is positioned at the grid structure on described substrate；
It is positioned at the source region in the substrate of described grid structure both sides and drain region；
It is positioned at the compressive stress thin layer on described grid structure top and sidewall and substrate, is wherein positioned at institute
State the thickness of compressive stress thin layer on substrate and be more than compressive stress thin layer on described grid structure top and sidewall
Thickness.
Optionally, on described substrate, the thickness of compressive stress thin layer is in the range of 50 to 2000 angstroms, institute
State the thickness of compressive stress thin layer on grid structure top and sidewall within 1000 angstroms.
Optionally, the material of described compressive stress thin layer is silicon nitride.
Optionally, described transistor is PMOS transistor, doped with boron ion in described source region and drain region
Or boron difluoride ion.
Optionally, described grid structure includes grid and is positioned at the side wall of gate lateral wall.
Optionally, described source region and drain region are the stressor layers through overdoping.
Compared with prior art, technical scheme have the advantage that transistor of the present invention and
Forming method forms compressive stress thin layer, described lining on described grid structure top and sidewall and substrate
Compressive stress thin layer at the end mainly provides the compressive stress along channel width dimension, described grid to channel region
Channel region is mainly provided vertical-channel width to answer by the compressive stress thin layer in structural top and sidewall
Power.It is positioned at the thickness of compressive stress thin layer on described substrate to press more than on described grid structure top and sidewall
The thickness of stress film layer, is tied by the thickness and described grid adjusting compressive stress thin layer on described substrate
The thickness of compressive stress thin layer on structure top and sidewall so that described compressive stress thin layer is to described channel region
The combined stress direction provided is closer to channel width dimension, and the effective stress applying channel region is bigger,
It is more beneficial for improving the carrier mobility of channel region, thus improves the electrical property of transistor.Additionally,
By controlling on the thickness of compressive stress thin layer on described substrate and described grid structure top and sidewall, pressure should
The thickness of power thin layer, it is possible to need the compressive stress size along channel width dimension is entered for device performance
Row effectively regulation；Simultaneously can also be by regulating compressive stress thin layer and described grid structure top on described substrate
The thickness difference of compressive stress thin layer in portion and sidewall, controls compressive stress direction, in order to formed not easily
Transistor with performance requirement.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of a kind of PMOS transistor of prior art；
Fig. 2 to Fig. 9 is the schematic diagram of forming method one each step of embodiment of transistor of the present invention；
Figure 10 is the schematic diagram of transistor one embodiment of the present invention.
Detailed description of the invention
As stated in the Background Art, in the transistor of existing employing stress technique, compressive stress thin layer is to PMOS
The useful effect power of transistor channel region is less.
Divide please continue to refer to Fig. 1, analyze the useful effect of compressive stress thin layer pair pmos transistor channel region
The reason that power is less, prior art generally uses the method for deposition to form described compressive stress thin layer 06,
On substrate 01, compressive stress thin layer 06 thickness at grid structure 05 sidewall and top more uniform, so
Compressive stress arrow F1 institute along figure that the channel region that described compressive stress thin layer 06 is PMOS transistor provides
Finger direction is bigger with angle b1 of channel width dimension (direction with reference to shown in dotted line the end of a thread).Stress and raceway groove
The angle of width is the least, and stress is the biggest to the useful effect power of channel region, on the contrary then useful effect power
The least, therefore, prior art formed with the compressive stress thin layer 06 useful effect force direction to channel region
Fixing, and the stress applying channel region is less, improves the limited use of transistor performance.
In order to solve above-mentioned technical problem, the present invention proposes a kind of transistor and forming method thereof, described
Forming compressive stress thin layer on grid structure top and sidewall and substrate, the compressive stress on described substrate is thin
Film layer mainly provides the compressive stress along channel width dimension, described grid structure top and sidewall to channel region
On compressive stress thin layer mainly to channel region provide vertical-channel width stress.It is positioned at described lining
, the thickness of compressive stress thin layer is more than the thickness of compressive stress thin layer on described grid structure top and sidewall at the end
Degree, by adjusting on the thickness of compressive stress thin layer on described substrate and described grid structure top and sidewall
The thickness of compressive stress thin layer so that the combined stress side that described channel region is provided by described compressive stress thin layer
To closer to channel width dimension, the effective stress applying channel region is bigger, is more beneficial for improving ditch
The carrier mobility in road district, thus improve the electrical property of transistor.Additionally, by controlling described lining
The thickness of compressive stress thin layer on the thickness of compressive stress thin layer and described grid structure top and sidewall at the end
Degree, it is possible to need the compressive stress size along channel width dimension is effectively regulated for device performance；
Simultaneously can also be by pressing on compressive stress thin layer on the described substrate of regulation and described grid structure top and sidewall
The thickness difference of stress film layer, controls compressive stress direction, in order to form different performance demand easily
Transistor.Understandable for enabling the above-mentioned purpose of the present invention, feature and advantage to become apparent from, below in conjunction with
The specific embodiment of the present invention is described in detail by accompanying drawing.
The showing of forming method one each step of embodiment of transistor of the present invention is shown referring to figs. 2 to Figure 10
It is intended to, it should be noted that transistor to be formed in the present embodiment is PMOS transistor, but
Transistor types to be formed is not limited by the present invention.
With reference to Fig. 2, it is provided that substrate 100, in the present embodiment, described substrate 100 is silicon substrate, described
Substrate 100 can also be other Semiconductor substrate such as germanium silicon substrate or silicon-on-insulator substrate, sends out this
Bright do not do any restriction.
In the present embodiment, forming isolation structure 101 in substrate 100, isolation structure 101 is by described substrate
100 for forming the region of PMOS transistor and for forming the zone isolation of other transistors.This reality
Executing in example, described isolation structure 101 is isolated for shallow trench, but the present invention is to described isolation structure 101
Particular type do not limit, in other embodiments, described isolation structure 101 can also be local oxygen
Compound is isolated.
In the present embodiment, after forming isolation structure 101, at substrate 100 surface and isolation structure
101 surfaces form gate dielectric layer 120, and the material of gate dielectric layer 120 is silicon oxide, but the present invention
Without limitation, in other embodiments, the material of described gate dielectric layer 120 can also be for oxidation
The hafniums such as hafnium.
With continued reference to Fig. 2, described substrate 100 forms grid structure 106, described grid structure 106
Including the grid 103 that material is polysilicon, it is positioned at grid 103 sidewall and side wall 104 that material is silicon nitride.
It should be noted that in the present embodiment, the material of described grid 103 is polysilicon, but this
The bright material to grid 103 does not limits, and in other embodiments, the material of described grid 103 also may be used
For metal.
It should be noted that in the present embodiment, form protective layer 105 at described grid 103 top, described
Grid structure 106 also includes that protective layer 105, the effect of described protective layer 105 are protection grids 103, institute
The material stating protective layer 105 is silicon nitride, but the material of protective layer of the present invention 105 and whether being formed
Protective layer 105 does not limits.After forming grid structure 106, remove what grid structure 106 exposed
Gate dielectric layer 120.
With reference to Fig. 3, with grid structure 106 as mask, substrate 100 is performed etching, remove grid structure
The section substrate 100 that 106 expose, forms groove 107 in described substrate 100.
In the present embodiment, the method performing etching substrate 100 is plasma etching method, but this
Bright without limitation, it would however also be possible to employ wet etching forms described groove 107.
It should be noted that in the present embodiment, after forming described groove 107, described grid is tied
The substrate 100 of structure 106 both sides is lightly doped, and lightly doped effect is the electric leakage reducing transistor channel
Stream.Lightly doped ion can select boron ion or boron difluoride ion, but the present invention is to lightly doped
Ionic type does not limits.
With reference to Fig. 4, the substrate 100 of described grid structure 106 both sides forms stressor layers 108.
Specifically, in the present embodiment, using epitaxy technique, in described groove 107, epitaxial growth is partly led
Body material layer, forms described stressor layers 108, and makes the surface of stressor layers 108 higher than gate dielectric layer 102
Bottom, thus realize the filling to groove 107.
After epitaxial growth stressor layers 108, the forming method of transistor also includes: to described stressor layers 108
It is doped, to form source region and drain region.Specifically, in the present embodiment, described stressor layers 108 is entered
Row ion implanting, the ion that ion implanting is used include the one in boron ion or boron difluoride ion or
Two kinds, but the ionic type injected becoming source region and drain region is not limited by the present invention.
It should be noted that in other embodiments, it is also possible to it is formed without described stressor layers 108, but right
The substrate 100 of grid structure 106 both sides is doped formation source region and drain region, and the present invention is to source region and leakage
The forming method in district does not limits.
It should be noted that after performing the ion implant, in addition it is also necessary to described stressor layers 108 is moved back
Fire.
It is positioned at below grid structure 106, and the substrate 100 of the segment thickness between source region and drain region
Channel region for transistor.
With reference to Fig. 5, described stressor layers 108 forms metal silicide layer 110.
Described metal silicide layer 110 is for reducing the contact resistance between conductive plunger and source region or drain region.
In the present embodiment, the material of described metal silicide layer 110 is NiPt silicide, but the present invention couple
The material of described metal silicide layer 110 does not limits
With reference to Fig. 6 to Figure 10, described grid structure 106 top and sidewall and substrate 100 are formed
Compressive stress thin layer, is positioned at the thickness of compressive stress thin layer on described substrate 100 and is more than described grid structure
The thickness of compressive stress thin layer on top and sidewall.
Specifically, referring initially to Fig. 6, shape on described grid structure 106 top and sidewall and substrate 100
Become compressive stress material layer 111.
In the present embodiment, described substrate 100 is formed with fleet plough groove isolation structure 101, described stressor layers
It is formed with metal silicide layer 110 on 108, on described substrate 100, therefore forms compressive stress material layer 111
Step include: on fleet plough groove isolation structure 101 and metal silicide layer 110 formed compressive stress material
Layer 111.
In the present embodiment, chemical vapour deposition technique is used to form described compressive stress material layer 111, described pressure
The material of stress material layer 111 is silicon nitride.Silicon nitride is a kind of material that can produce compressive stress, institute
Stating compressive stress material layer 111 for forming compressive stress thin layer, the compressive stress thin layer of silicon nitride can be
Channel region applies compressive stress, thus improves the carrier mobility of channel region.But the present invention is to described pressure
The concrete material of stress material layer 111 does not limits, in other embodiments, and described compressive stress material layer
The material of 111 can also can provide the material of compressive stress for other.
Described compressive stress material layer 111 will be etched to form two parts that thickness is different in subsequent process
Compressive stress thin layer, the compressive stress thin film that the thickness of described compressive stress material layer 111 is namely subsequently formed
The maximum gauge of layer, say, that the thickness of described compressive stress material layer 111 determines and is subsequently formed
The maximum of two parts compressive stress thin film layer thickness difference, in the present embodiment, described compressive stress material layer 111
Thickness in the range of 50 to 2000 angstroms so that two parts compressive stress thin film layer thickness being subsequently formed
Difference has bigger adjustable range.
With reference to Fig. 7, described compressive stress material layer 111 covers anti-reflecting layer (BarC) 112, described
The upper surface of anti-reflecting layer 112 is higher than the top of described grid structure 106.
In the present embodiment, use the method for coating to cover described anti-reflecting layer 112, such be advantageous in that,
The described anti-reflecting layer 112 that coating is formed has smooth surface so that in subsequent process, it is possible to logical
Cross back and carve the method for described anti-reflecting layer 112 and remove the anti-reflective on described grid structure 106 top and sidewall
Penetrate layer 112, and retain the anti-reflecting layer 112 of grid structure 106 two side portions thickness, but the present invention couple
Whether do not limit as the mask layer of etching compressive stress material layer 111 using described anti-reflecting layer 112, also may be used
To form other kinds of mask layer on described compressive stress material layer 111.
With reference to Fig. 8, etch described anti-reflecting layer 112, remove described grid structure 106 top section thickness
Compressive stress material layer 111, remaining compressive stress material layer 111 forms compressive stress thin layer 113.
Specifically, in conjunction with reference to Fig. 7, before etching starts, described anti-reflecting layer 112 has smooth table
Face, therefore, as it is shown in fig. 7, above described grid structure 106 and described grid structure 106 both sides
Anti-reflecting layer 112 thickness is different.With continued reference to Fig. 8, during etching described anti-reflecting layer 112,
On described substrate 100 and described grid structure 106 top and anti-reflecting layer 112 thickness on sidewall are continuous
Reducing, the anti-reflecting layer 112 at described grid structure 106 top is entirely removed, described grid structure 106
The compressive stress material layer 111 at top exposes, along with proceeding of etching, resisting on described substrate 100
Reflecting layer 112 thickness keeps reduction, the compressive stress material simultaneously exposed on grid structure 106 sidewall
Layer 111 is also removed segment thickness.
After the compressive stress material layer 111 exposed at grid structure 106 top is also removed segment thickness, stop
Only etching process, after stopping etching, as shown in Figure 8, described substrate 100 there remains part thick
The anti-reflecting layer 112 of degree.The compressive stress material layer 111 exposed due to grid structure 106 top is removed portion
Divide thickness, therefore in described compressive stress thin layer 113, be positioned at compressive stress thin film on described substrate 100
The thickness of layer 113 is more than the thickness of compressive stress thin layer 113 on described grid structure 106 top and sidewall.
It should be noted that in the present embodiment, the method etching described anti-reflecting layer 112 is plasma
Body etching method.
The etching agent that described plasma etching method uses can use CF4、CH3F、HBr、NF3、Cl2、
O2、N2In one or more, carrier gas includes one or more in Ar, He.The present invention is to this not
It is restricted.
With reference to Fig. 9, after forming compressive stress thin layer 113, remove described remaining anti-reflecting layer 112.
It should be noted that in the transistor, the direction that between source region and drain region, line extends is raceway groove width
Degree direction, channel region is mainly provided along channel width by the compressive stress thin layer 113 on described substrate 100
The compressive stress in direction (direction as shown in phantom in Figure 9), on described grid structure 106 top and sidewall
Compressive stress thin layer 113 mainly channel region is provided the compressive stress of vertical-channel width.Due to position
On described substrate 100, the thickness of compressive stress thin layer 113 is more than described grid structure 106 top and side
The thickness of compressive stress thin layer 113 on wall, on described substrate 100, compressive stress thin layer 113 is to channel region
The compressive stress provided more than compressive stress thin layer 113 on described grid structure 106 top and sidewall to raceway groove
The compressive stress that district provides so that the combined stress F2 direction that described channel region is provided by described compressive stress thin layer
Less with the angle a1 of channel width dimension, i.e. combined stress F2 direction close to channel width dimension, because of
In this transistor of the present invention, the effective stress that described channel region is applied by compressive stress thin layer 113 is bigger,
It is more beneficial for improving the carrier mobility of channel region, thus improves the electrical property of transistor.Additionally,
By controlling the thickness of compressive stress material layer, and control gate structure 106 top compressive stress material layer
Removal amount, it is possible to control the thickness of compressive stress thin layer 113 on described substrate 100 and described grid easily
The thickness of compressive stress thin layer 113 on electrode structure 106 top and sidewall, it is possible to need for device performance
Compressive stress size along channel width dimension is effectively regulated, simultaneously can also be by regulating described substrate
Compressive stress thin layer 113 on compressive stress thin layer 113 and described grid structure 106 top and sidewall on 100
Thickness difference, easily control compressive stress direction, in order to formed different performance demand transistor.
It should be noted that when the thickness of compressive stress thin layer 113 and grid structure 106 on substrate 100
When the thickness difference of the compressive stress thin layer 113 on top and sidewall reaches certain limit, increase compressive stress thin
The thickness of film layer 113 DeGrain to improving useful effect power；If compressive stress is thin on substrate 100
The thickness difference of the compressive stress thin layer 113 on the thickness of film layer 113 and grid structure 106 top and sidewall
Too small, then compressive stress thin layer 113 is to the combined stress F2 direction of channel region and channel width dimension angle a1
Bigger.Therefore, in the present embodiment, and on described substrate 100 (in the present embodiment, shallow trench isolation junction
Structure 101 and metal silicide layer 110) on the thickness of compressive stress thin layer 113 at 50 to 2000 angstroms
In the range of, the thickness of the compressive stress thin layer 113 on described grid structure 106 top and sidewall arrives 0
In the range of 200 angstroms, the useful effect power to channel region can either be increased, save again compressive stress thin layer
The material of 113, it is ensured that production efficiency.
The present invention also provides for a kind of transistor, refer to Figure 10, it is shown that transistor one embodiment of the present invention
Schematic diagram.
As shown in Figure 10, the present embodiment transistor is PMOS transistor, but the present invention is to transistor
Particular type does not limits.The present embodiment transistor includes:
Substrate 100`, in the present embodiment, described substrate 100` is silicon substrate, and described substrate 100` also may be used
Think other Semiconductor substrate such as germanium silicon substrate or silicon-on-insulator substrate, this present invention is not done any limit
System.
In the present embodiment, being formed with isolation structure 101` in substrate 100`, isolation structure 101` is by described
Substrate 100` is for forming the region of PMOS transistor and for forming the zone isolation of other transistors.
In the present embodiment, described isolation structure 101` is shallow trench isolation, but the present invention is to described isolation structure
The particular type of 101` does not limits, and in other embodiments, described isolation structure 101` can also be office
Portion's oxide-isolated.
In the present embodiment, substrate 100` surface and isolation structure 101` surface are additionally provided with gate dielectric layer
120`, the material of gate dielectric layer 120` is silicon oxide, but the present invention is without limitation, at other
In embodiment, the material of described gate dielectric layer 120` can also be the hafniums such as hafnium oxide.
With continued reference to Figure 10, described substrate 100` is provided with grid structure 106`, described grid structure 106`
Including grid 103`, the side wall 104` that is positioned at grid 103` sidewall.
It should be noted that in the present embodiment, the material of described grid 103` is polysilicon, described side wall
The material of 104` is silicon nitride, but the material of grid 103` and side wall 104` is not limited by the present invention,
In other embodiments, the material of described grid 103` can be also metal.
It should be noted that in the present embodiment, be provided with protective layer 105` at described grid 103` top,
Described grid structure 106` also includes that protective layer 105`, the effect of described protective layer 105` are protection grids
103`, the material of described protective layer 105` is silicon nitride, but the material of protective layer 105` of the present invention and
Whether form protective layer 105` not limit.After forming grid structure 106`, remove grid structure 106`
The gate dielectric layer 120` exposed.
With continued reference to Figure 10, the present embodiment transistor also includes the lining being positioned at described grid structure 106` both sides
Stressor layers 108` in end 100`.
Described stressor layers 108` is used separately as source through overdoping, stressor layers 108` of grid structure 106` both sides
District and drain region.In stressor layers 108` doping ion include the one in boron ion or boron difluoride ion or
Two kinds, but the ionic type adulterated becoming source region and drain region is not limited by the present invention.
Below grid structure 106`, and the section substrate 100` between source region and drain region is transistor
Channel region.
It should be noted that in the present embodiment, described stressor layers 108` is additionally provided with metal silicide
Layer 110`.
Described metal silicide layer 110` contacts electricity for reducing between conductive plunger with source region or drain region
Resistance.In the present embodiment, the material of described metal silicide layer 110` is NiPt silicide, but this
The bright material to described metal material layer with described metal silicide layer 110` does not limits
With continued reference to Figure 10, the present embodiment transistor also includes being positioned at described grid structure 106` top and side
Compressive stress thin layer 113` on wall and substrate 100`, is positioned at compressive stress thin layer on described substrate 100`
The thickness of 113` is more than the thickness of compressive stress thin layer 113` on described grid structure 106` top and sidewall.
In the present embodiment, the material of described compressive stress thin layer 113` is silicon nitride.Silicon nitride is a kind of
Easily producing the material of compressive stress, the compressive stress thin layer 113` of silicon nitride can apply pressure for channel region should
Power, thus improve the carrier mobility of channel region.But the present invention is to described compressive stress thin layer 113`
Concrete material do not limit, in other embodiments, the material of described compressive stress thin layer 113` also may be used
Think that other can provide the material of compressive stress.
It should be noted that in the transistor, the direction that between source region and drain region, line extends is raceway groove width
Degree direction, channel region is mainly provided along channel width by the compressive stress thin layer 113` on described substrate 100`
The compressive stress in direction (direction as shown in phantom in Figure 10), on described grid structure 106` top and sidewall
Compressive stress thin layer 113` mainly to channel region provide vertical-channel width compressive stress.Due to position
On described substrate 100`, the thickness of compressive stress thin layer 113` is more than described grid structure 106` top and side
The thickness of compressive stress thin layer 113` on wall, on described substrate 100`, compressive stress thin layer 113` is to channel region
The compressive stress provided more than compressive stress thin layer 113` on described grid structure 106` top and sidewall to raceway groove
The compressive stress that district provides so that the combined stress F3 direction that described channel region is provided by described compressive stress thin layer
Less with the angle a2 of channel width dimension, i.e. combined stress F3 direction close to channel width dimension, because of
In this transistor of the present invention, compressive stress thin layer 113` is relatively big, more favorably to the useful effect power of channel region
In the carrier mobility of raising channel region, thus improve the electrical property of transistor.Additionally, by control
The thickness of compressive stress material layer processed, and the removal amount of control gate structure 106` top compressive stress material layer,
The thickness of compressive stress thin layer 113` on described substrate 100` and described grid structure can be controlled easily
The thickness of compressive stress thin layer 113` on 106` top and sidewall, it is possible to need along raceway groove for device performance
The compressive stress size of width effectively regulates, and can also press on described substrate 100` by regulating simultaneously
The thickness of compressive stress thin layer 113` on stress film layer 113` and described grid structure 106` top and sidewall
Difference, controls compressive stress direction, in order to form the transistor of different performance demand easily.
It should be noted that as the thickness of compressive stress thin layer 113` and grid structure 106` on substrate 100`
When the thickness difference of the compressive stress thin layer 113` on top and sidewall reaches certain limit, increase compressive stress thin
The thickness of the film layer 113` DeGrain to improving useful effect power；If compressive stress is thin on substrate 100`
The thickness difference of the compressive stress thin layer 113` on the thickness of film layer 113` and grid structure 106` top and sidewall
Too small, then defeat and answer thin layer 113` to the combined stress F3 direction of channel region and channel width dimension angle a2
Increase.Therefore, in the present embodiment, it is positioned on described substrate 100` and (in the present embodiment, is positioned at shallow ridges
On recess isolating structure 101` and metal silicide layer 110`) the thickness of compressive stress thin layer 113` arrive 50
In the range of 2000 angstroms, the thickness of the compressive stress thin layer 113` on described grid structure 106 top and sidewall
Degree, in the range of 0 to 200 angstroms, can either increase the useful effect power to channel region, save again pressure
The material of stress film layer 113`, it is ensured that production efficiency.
It should be noted that in other embodiments, the manufacture method that the present invention provides can be also used for
Nmos pass transistor, when described manufacture method is for nmos pass transistor, described compressive stress thin layer
The material of 113 can be the material that channel region can provide tension.
Although present disclosure is as above, but the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, all can make various changes or modifications, therefore the guarantor of the present invention
The scope of protecting should be as the criterion with claim limited range.
Claims (15)
1. the forming method of a transistor, it is characterised in that including:
Substrate is provided；
Form grid structure over the substrate；
Source region and drain region is formed in the substrate of described grid structure both sides；
Described grid structure top and sidewall and substrate are formed compressive stress thin layer, is positioned on described substrate
The thickness of compressive stress thin layer is more than the thickness of compressive stress thin layer on described grid structure top and sidewall.
2. forming method as claimed in claim 1, it is characterised in that form the step bag of compressive stress thin layer
Include:
Described grid structure top and sidewall and substrate are formed compressive stress material layer；
Covering anti-reflecting layer on described compressive stress material layer, the upper surface of described anti-reflecting layer is higher than described grid
The top of structure；
Etch described anti-reflecting layer, and remove the compressive stress material layer of described grid structure upper part thickness, residue
Compressive stress material layer formed compressive stress thin layer；
Remove remaining described anti-reflecting layer.
3. forming method as claimed in claim 2, it is characterised in that at described grid structure top and sidewall
And formed in the step of compressive stress material layer on substrate, using chemical vapour deposition technique to form described pressure should
The dead-wood bed of material.
4. forming method as claimed in claim 2, it is characterised in that at described grid structure top and sidewall
And formed on substrate in the step of compressive stress material layer, the thickness of described compressive stress material layer arrives 50
In the range of 2000 angstroms.
5. forming method as claimed in claim 2, it is characterised in that cover on described compressive stress material layer
The step of anti-reflecting layer includes: use the method for coating to form described anti-reflecting layer.
6. forming method as claimed in claim 2, it is characterised in that the method etching described anti-reflecting layer is
Plasma etching method.
7. forming method as claimed in claim 6, it is characterised in that described plasma etching method uses
Etching agent includes: CF4、CH3F、HBr、NF3、Cl2、O2And N2In one or more, carrier gas
Including one or more in Ar and He.
8. forming method as claimed in claim 1, it is characterised in that form the step bag of compressive stress thin layer
Include:
On described substrate, the thickness of compressive stress thin layer is in the range of 50 to 2000 angstroms；Described grid structure top
The thickness of the compressive stress thin layer in portion and sidewall is within 1000 angstroms.
9. forming method as claimed in claim 1, it is characterised in that at described grid structure top and sidewall
And the step forming compressive stress thin layer on substrate includes:
The material of described compressive stress thin layer is silicon nitride.
10. a transistor, it is characterised in that including:
Substrate；
It is positioned at the grid structure on described substrate；
It is positioned at the source region in the substrate of described grid structure both sides and drain region；
It is positioned at the compressive stress thin layer on described grid structure top and sidewall and substrate, is wherein positioned at described
On substrate, the thickness of compressive stress thin layer is more than compressive stress thin layer on described grid structure top and sidewall
Thickness.
11. transistors as claimed in claim 10, it is characterised in that the thickness of compressive stress thin layer on described substrate
Degree compressive stress thin layer in the range of 50 to 2000 angstroms, on described grid structure top and sidewall
Thickness within 1000 angstroms.
12. transistors as claimed in claim 10, it is characterised in that the material of described compressive stress thin layer is nitrogen
SiClx.
13. transistors as claimed in claim 10, it is characterised in that described transistor is PMOS transistor,
Doped with boron ion or boron difluoride ion in described source region and drain region.
14. transistors as claimed in claim 10, it is characterised in that described grid structure includes grid and position
Side wall in gate lateral wall.
15. transistors as claimed in claim 10, it is characterised in that described source region and drain region are through overdoping
Stressor layers.
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| CN201510293280.4A CN106298922A (en) | 2015-06-01 | 2015-06-01 | Transistor and forming method thereof |
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| CN201510293280.4A CN106298922A (en) | 2015-06-01 | 2015-06-01 | Transistor and forming method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107611012A (en) * | 2017-08-31 | 2018-01-19 | 长江存储科技有限责任公司 | A kind of stress control method and structure of prefabricated back film |
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