CN110858565B - Semiconductor device and method of forming the same - Google Patents
Semiconductor device and method of forming the same Download PDFInfo
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- CN110858565B CN110858565B CN201810971791.0A CN201810971791A CN110858565B CN 110858565 B CN110858565 B CN 110858565B CN 201810971791 A CN201810971791 A CN 201810971791A CN 110858565 B CN110858565 B CN 110858565B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention discloses a method for forming a semiconductor device, which comprises the following steps: providing a semiconductor substrate and a fin part, wherein the semiconductor substrate is divided into a PMOS area and an NMOS area, the fin part comprises a P area fin part and an N area fin part, and the P area fin part and the N area fin part are respectively and correspondingly formed above the PMOS area and the NMOS area; forming a first protective layer covering the surface of the fin part; forming an interlayer dielectric layer between the adjacent fin parts; and removing part of the interlayer dielectric layer and part of the first protection layer to expose the side wall of the upper part of the P-region fin part and the side wall of the upper part of the N-region fin part, wherein the width dimension of the P-region fin part at the exposed side wall is smaller than that of the N-region fin part at the exposed side wall. The smaller width of the P region fin part increases the control capability of a subsequent grid structure on a device, effectively inhibits the short channel effect and improves the performance of the semiconductor device.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor device and a method for forming the same.
Background
The advent of FinFET processes and structures has led to the development of semiconductor devices with ever smaller dimensions. But due to the reduction of the size of the structure, the structure is compact, short channel effect is easy to generate, and along with the occurrence of leakage phenomenon, the control capability of the gate structure is weakened, and the performance of the semiconductor device is reduced.
Therefore, a method for forming a semiconductor device with improved control capability of a gate structure and a corresponding semiconductor device are needed.
Disclosure of Invention
The embodiment of the invention provides a method for forming a semiconductor device, which enables the width of a P-region fin part and the width of an N-region fin part to be different in size and improves the control capability of a grid structure.
The invention discloses a method for forming a semiconductor device, which comprises the following steps: providing a semiconductor substrate and a fin part, wherein the semiconductor substrate comprises a PMOS area and an NMOS area, the fin part comprises a P area fin part and an N area fin part, and the P area fin part and the N area fin part are respectively and correspondingly formed above the PMOS area and the NMOS area; forming a first protective layer covering the surface of the fin part; forming an interlayer dielectric layer between adjacent fin parts; and removing part of the interlayer dielectric layer and part of the first protection layer to expose the side wall of the upper part of the P-region fin part and the side wall of the upper part of the N-region fin part, wherein the width dimension of the P-region fin part at the exposed side wall is smaller than that of the N-region fin part at the exposed side wall.
According to one aspect of the present invention, the process of exposing the sidewalls of the upper portions of the P region fins and the sidewalls of the upper portions of the N region fins comprises: etching part of the interlayer dielectric layer to expose the first protective layer formed on the upper part of the P region fin part; etching the first protective layer exposed at the upper part of the fin part in the P region; etching a part of interlayer dielectric layer formed in the NMOS area to expose the first protective layer formed on the upper part of the fin part in the N area; and etching to remove the first protective layer exposed in the NMOS region and etching the remaining first protective layer or the fin part in the P region.
According to one aspect of the present invention, the process of exposing the sidewalls of the upper portions of the P region fins and the sidewalls of the upper portions of the N region fins comprises: etching part of the interlayer dielectric layer to expose the upper parts of the N-region fin parts and the P-region fin parts; etching a part of the first protective layer formed on the upper part of the P region fin part; and etching to remove the first protective layer formed on the upper part of the N-region fin portion and the remaining first protective layer or the P-region fin portion on the upper part of the etched P-region fin portion.
According to an aspect of the present invention, after exposing sidewalls of an upper portion of the P-region fin and sidewalls of an upper portion of the N-region fin, a width dimension of the upper portion of the P-region fin is smaller than a width dimension of a lower portion of the P-region fin.
According to an aspect of the invention, after forming the first protection layer and before forming the interlayer dielectric layer, the method further includes: forming a sacrificial layer between adjacent fin portions; removing part of the sacrificial layer to expose part of the first protective layer formed in the PMOS region; removing the first protective layer exposed in the PMOS area to expose part of the P area fin part; removing the remaining sacrificial layer to expose the remaining first protective layer; forming a second protective layer on the surface of the first protective layer and the surface of the exposed P-region fin part, wherein the protective layer comprises the first protective layer and the second protective layer;
according to one aspect of the present invention, the process of exposing a portion of sidewalls of the P-region fins and a portion of sidewalls of the N-region fins comprises: removing part of the interlayer dielectric layer to expose part of the second protective layer; etching and removing the exposed second protective layer to expose the P-region fin portion and the first protective layer on the N-region fin portion; and etching and removing the exposed first protective layer and the exposed P-region fin part formed on the N-region fin part.
According to one aspect of the invention, the material of the protective layer comprises SiNx、SiO2Or one or more combinations of alpha-Si.
According to one aspect of the invention, the thickness dimension of the first protective layer or the second protective layer is in the range of
According to one aspect of the invention, after the interlayer dielectric layer is formed, the thickness of the protective layer on the upper surface of the P-region fin portion is smaller than that of the protective layer on the upper surface of the N-region fin portion.
According to one aspect of the invention, after the interlayer dielectric layer is formed, the thickness of the protective layer on the upper surface of the P-region fin portion is smaller than that of the protective layer on the lower surface of the P-region fin portion, and the thickness of the protective layer on the lower surface of the P-region fin portion is equal to that of the protective layer on the lower surface of the N-region fin portion.
According to one aspect of the invention, the process for forming the interlevel dielectric layer includes a fluid chemical vapor deposition process.
According to one aspect of the invention, after the forming the interlayer dielectric layer, the annealing process is performed on the interlayer dielectric layer.
According to one aspect of the invention, the step of annealing the process comprises: firstly, carrying out water vapor annealing process treatment, and then carrying out rapid thermal annealing process treatment.
According to one aspect of the invention, the process parameters of the water vapor annealing process comprise: the annealing temperature range is 550-750 ℃, the annealing time range is 30-200 min, and the technological parameters of the rapid thermal annealing process comprise: the annealing temperature range is 950 ℃ to 1050 ℃, and the annealing time range is 15min to 100 min.
According to one aspect of the present invention, the N-region fin has a width dimension of l at the exposed sidewalls2The width of the P region fin at the exposed sidewall isl1And then 0.7 is not more than l1:l2≤0.9。
According to one aspect of the invention, 1 nm. ltoreq. l2-l 1. ltoreq.2.5 nm.
Accordingly, the present invention also provides a semiconductor device comprising: the semiconductor substrate comprises a PMOS region and an NMOS region, the fin portion comprises a P region fin portion and an N region fin portion, the P region fin portion and the N region fin portion are respectively and correspondingly arranged above the PMOS region and the NMOS region, and the width dimension of the upper portion of the P region fin portion is smaller than that of the upper portion of the N region fin portion; the protective layer is arranged on the surface of the lower part of the fin part; and the interlayer dielectric layer is formed between the adjacent fin parts.
According to one aspect of the present invention, the upper portion of the N region fin has a width dimension of l2The width of the upper part of the P region fin portion is l1And then 0.7 is not more than l1:l2≤0.9。
According to one aspect of the invention, 1nm ≦ l2-l1≤2.5nm。
According to one aspect of the present invention, the protective layer includes a first protective layer and a second protective layer disposed between the interlayer dielectric layer and the first protective layer.
According to one aspect of the present invention, the width dimension of the upper portion of the P-region fin is smaller than the width dimension of the lower portion of the P-region fin.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the method for forming the semiconductor device, the width dimension of the P-region fin at the exposed side wall is smaller than the width dimension of the N-region fin at the exposed side wall. The width of the exposed side wall of the P-region fin part is small, an electron full depletion layer can be formed in the channel of the P region, the control capability of the grid structure is improved, and meanwhile, the short channel effect is restrained.
Further, an interlayer dielectric layer is formed by adopting a fluid chemical vapor deposition process. The process can ensure that the formed interlayer dielectric layer has a compact structure and reduce defects.
Furthermore, the annealing process of the interlayer dielectric layer comprises the steps of firstly carrying out water vapor annealing process treatment and then carrying out rapid thermal annealing process treatment. The water vapor annealing process can eliminate hydrogen bonds or nitrogen bonds in the interlayer dielectric layer and reduce impurities. Meanwhile, the rapid thermal annealing process can accelerate the forming of the interlayer dielectric layer.
Correspondingly, the embodiment of the invention also provides a semiconductor device, wherein the width dimension of the upper part of the P-region fin part is smaller than that of the upper part of the N-region fin part. The smaller width of the P region fin part can form an electron fully-depleted layer in a subsequent channel, so that the control capability of the grid structure is improved, and meanwhile, the short-channel effect is inhibited.
Drawings
FIGS. 1-5 are process structure diagrams of a method of forming a semiconductor device according to one embodiment of the present invention;
6-8 are process structure diagrams of a method of forming a semiconductor device according to another embodiment of the invention;
fig. 9-10 are process structure diagrams of a method of forming a semiconductor device according to yet another embodiment of the invention.
Detailed Description
As described above, the conventional semiconductor device has a problem that the gate structure has a poor controllability and a short channel effect.
The research finds that the reasons causing the problems are as follows: when no voltage is applied, a small amount of carriers still exist in a channel, the accumulation of the carriers easily causes a short-channel effect, and meanwhile, electric leakage occurs, so that the capability of controlling a device by a grid structure is reduced.
In order to solve the problem, the invention provides a method for forming a semiconductor device and the semiconductor device, wherein a fully depleted layer of electrons is formed in a channel of a P-region fin part, all surplus electrons are consumed, and no surplus carriers exist when no voltage is applied, so that the problem is solved.
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the relative arrangement of parts and steps, numerical expressions, and numerical values set forth in these embodiments should not be construed as limiting the scope of the present invention unless it is specifically stated otherwise.
Further, it should be understood that the dimensions of the various elements shown in the figures are not necessarily drawn to scale relative to actual scale, for example, the thickness or width of some layers may be exaggerated relative to other layers for ease of illustration.
The following description of the exemplary embodiment(s) is merely illustrative and is not intended to limit the invention or its application or uses in any way.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification as applicable.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus, once an item is defined or illustrated in one figure, further discussion thereof will not be required in the subsequent description of the figures.
First embodiment
Referring to fig. 1, a semiconductor substrate 100 is provided with a fin portion.
The semiconductor substrate 100 serves as a process foundation for forming a semiconductor device. The material of the semiconductor substrate 100 is at least one of the following materials: polysilicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-germanium (S-SiGeOI), silicon-on-insulator-germanium (SiGeOI), and the like. In the embodiment of the present invention, the material of the semiconductor substrate 100 is polysilicon. And other structures may be included in the semiconductor substrate 100, such as: the structures of metal plugs, metal connection layers, dielectric layers, etc., or other semiconductor devices including these structures, are not limited in this respect.
In an embodiment of the present invention, the semiconductor substrate 100 includes a PMOS region and an NMOS region, and a fin portion is disposed above the semiconductor substrate 100, as shown in the figure. P-region fins 101 and N-region fins 102 are correspondingly arranged above the PMOS region and the NMOS region respectively. In the embodiment of the present invention, the material of the fin portion is the same as the material of the semiconductor substrate 100.
The embodiment of the present invention further includes forming a first protection layer 110 covering the surface of the fin portion. The first protection layer 110 is used to protect the fin portion and prevent the fin portion from being excessively worn in the subsequent process. Meanwhile, when the interlayer dielectric layer is formed in the follow-up process, the fin portion is prevented from being pulled by stress.
The material of the first protective layer 110 includes SiNx、SiO2Or one or more combinations of alpha-Si. Specifically, in the embodiment of the present invention, the material of the first protection layer 110 is SiNx。
The thickness of the first passivation layer 110 is within a range of
(Here, the thickness is in the range of not less than
Is less than or equal to
I.e., ranges include the end point values, and ranges are expressed as such). Specifically, in the embodiment of the present invention, the thickness of the first passivation layer 110 is
In another embodiment of the present invention, the first passivation layer 110 has a thickness of
In yet another embodiment of the present invention, the first protective layer 110 has a thickness of 
In the embodiment of the present invention, the first protective layer 110 also covers the surface of the semiconductor substrate 100. Covering both the semiconductor substrate 100 and the fin surface can facilitate the process. In other embodiments of the present invention, the first protection layer 110 may cover only the surface of the fin portion, and is not limited herein.
Referring to fig. 2, a sacrificial layer 120 is formed between adjacent fins, and then a portion of the surface of the P-region fin 101 is exposed.
The sacrificial layer 120 is formed to etch and remove the first protection layer 110 at a specific position, thereby exposing the fin portion in a specific region. As in the embodiment of the invention, after the sacrificial layer 120 is formed, a portion of the sacrificial layer 120 above the P-region fin 101 is removed by etching, and a portion of the first protection layer 110 in the PMOS region is exposed. In the embodiment of the invention, after exposing a portion of the first passivation layer 110 in the PMOS region, removing the exposed first passivation layer 110 to expose a portion of the P region fin.
The P-region fin 101 is exposed so that the thicknesses of the protection layers at the positions of the N-region fin 102 and the P-region fin 101 are not equal.
It should be noted that, in the embodiment of the present invention, when the exposed first protective layer 110 is removed to expose the P-region fin 101, the P-region fin 101 may be properly etched, so that the width of the exposed portion of the P-region fin 101 is smaller than that of the N-region fin 102. In other embodiments of the present invention, the P-region fin 101 may not be etched, and is not limited herein.
Referring to fig. 3, the remaining sacrificial layer is removed, and a second protection layer 130 is formed on the first protection layer 110 and the surface of the exposed P-region fin 101.
The second protection layer 130 is formed to further protect the fin from being over-etched.
The thickness of the second passivation layer 130 may be equal to or different from that of the first passivation layer 110. Specifically, in the embodiment of the present invention, the thickness of the second passivation layer 130 is equal to that of the first passivation layer 110. The material of the second passivation layer 130 may be the same as or different from that of the first passivation layer 110. Specifically, in the embodiment of the present invention, the material of the second protection layer 130 is different from the material of the first protection layer 110, and the material of the second protection layer 130 is SiNxAnd alpha-Si.
In the embodiment of the present invention, the protective layer includes the first protective layer 110 and the second protective layer 130. The material types or the thicknesses of the two protective layers are controlled, so that the P-region fin portion 101 can be partially etched conveniently, the etching end point can be controlled accurately, and the situation that the width of the P-region fin portion 101 exceeds a specific range and the performance of a final semiconductor device is affected is avoided.
Also, since the first protective layer 110 covers over the semiconductor substrate 100, the second protective layer 130 is also formed over the semiconductor substrate 100. In other embodiments of the present invention, the second protection layer 130 may also be formed only on the fin portion, and is not limited herein.
Referring to fig. 4, an interlayer dielectric layer 140 is formed between adjacent fins.
The interlayer dielectric layer 140 is formed to simultaneously etch the protective layers on the surfaces of the P-region fin 101 and the N-region fin 102 in the following process, so as to control the etching synchronization degree and make the exposed fin uniform in height.
The process for forming the interlayer dielectric layer 140 includes a Fluid Chemical Vapor Deposition (FCVD) process. The FCVD process can flow and fill the required material, making the formed interlayer dielectric layer 140 denser and having fewer defects.
In the embodiment of the present invention, an annealing process is further performed on the formed interlayer dielectric layer 140. The annealing process can make the interlayer dielectric layer 140 more compact, and simultaneously, the interlayer dielectric layer 140 is molded, and stress can be eliminated.
Specifically, in the embodiment of the present invention, the process of annealing the interlayer dielectric layer 140 includes: firstly, carrying out water vapor annealing process treatment, and then carrying out rapid thermal annealing process treatment. Because the liquid material also has redundant hydrogen bonds or nitrogen bonds, water vapor is introduced at a lower temperature, oxygen is introduced into the unformed interlayer dielectric layer 140, the hydrogen bonds or the nitrogen bonds are eliminated, and the final interlayer dielectric layer 140 is ensured to contain less impurities. Rapid thermal annealing can accelerate the formation of the interlevel dielectric layer 140.
In an embodiment of the present invention, the process parameters of the water vapor annealing process include: the annealing temperature range is 550-750 ℃, and the annealing time range is 30-200 min. The technological parameters of the rapid thermal annealing process comprise: the annealing temperature range is 950 ℃ to 1050 ℃, and the annealing time range is 15min to 100 min. Specifically, in the embodiment of the invention, the temperature of the water vapor annealing is 750 ℃, and the annealing time is 30 min. The temperature of the rapid thermal annealing process is 1050 ℃, and the annealing time is 15 min. In another embodiment of the present invention, the temperature of the water vapor annealing is 550 ℃ and the annealing time is 200 min. The temperature of the rapid thermal annealing process is 950 ℃, and the annealing time is 100 min. In yet another embodiment of the present invention, the temperature of the water vapor annealing is 600 ℃ and the annealing time is 100 min. The temperature of the rapid thermal annealing process is 1000 ℃, and the annealing time is 60 min.
After the interlayer dielectric layer 140 is formed, the fin portion is divided into two parts: fin portion upper portion and fin portion lower part. Here, the upper and lower portions of the fin are divided by using the P-region fin 101 as a standard: the range of the P region fin 101 not contacting the first protection layer 110 is referred to as an upper fin portion, whereas the range contacting the first protection layer 110 is referred to as a lower fin portion, and hereinafter, the upper fin portion and the lower fin portion have the same meaning as that of the above. In the embodiments of the present invention, the ranges specified for the upper fin portion and the lower fin portion apply equally to the N-region fin 102.
Obviously, in the embodiment of the present invention, since the first protective layer 110 and the second protective layer 130 are formed on the upper portion of the N-region fin 102, and only the second protective layer 130 is formed on the upper portion of the P-region fin 101, after the interlayer dielectric layer 140 is formed, the thickness of the protective layer on the upper surface of the P-region fin 101 is smaller than that of the protective layer on the upper surface of the N-region fin 102. The thicknesses of the protective layers on the N-region fin 102 and the P-region fin 101 are different, so that the exposed part of the P-region fin 101 and the exposed part of the N-region fin 102 are different when the protective layer is removed to expose the upper part of the fin.
In addition, in the embodiment of the present invention, since only the first protection layer 110 is formed on the upper surface of the P-region fin 101, and the first protection layer 110 and the second protection layer 130 are formed on the lower surface of the P-region fin 101, the thickness of the protection layer on the upper surface of the P-region fin 101 is smaller than the thickness of the protection layer on the lower surface of the P-region fin 101. Obviously, the thickness of the passivation layer on the lower surface of the P-region fin 101 is equal to the thickness of the passivation layer on the lower surface of the N-region fin 102. The protective layers on the lower portions of the P-region fin portion 101 and the N-region fin portion 102 are equal in thickness, so that when the interlayer dielectric layers 140 are formed, traction of the interlayer dielectric layers 140 to the lower portions of the fin portions is weakened, stress generated when the interlayer dielectric layers 140 are formed is buffered, and the fin portions are protected. Meanwhile, the lower part of the fin part is provided with a thicker protective layer, so that the control capability of the fin part is further improved.
Referring to fig. 5, a portion of the interlayer dielectric layer 140 and a portion of the passivation layer are removed to expose the upper portion of the fin.
In an embodiment of the invention, the step of exposing the fin portion includes: after removing a part of the interlayer dielectric layer 140, exposing a part of the second protection layer 130, then etching and removing the exposed second protection layer 140 to expose the P-region fin portion 101 and the first protection layer 110 on the N-region fin portion 102, then etching and removing the first protection layer 110 exposed on the N-region fin portion 102 and the exposed P-region fin portion 101 to expose a part of the sidewall of the N-region fin portion 102 and a part of the sidewall of the P-region fin portion 101.
Obviously, when the first protection layer 110 on the N-region fin 102 is etched and removed, part of the side surface of the P-region fin 101 is exposed, so that the P-region fin 101 is also partially etched in the process of etching the first protection layer 110 on the N-region fin 102. Thus, after the first protection layer 110 on the N-region fins 102 is finally removed, the width dimension l of the P-region fins 101 at the exposed sidewalls1Is smaller than the width dimension l of the N-region fin 102 at the exposed sidewalls2。
Obviously, after the sidewalls of the P-region fin 101 and the N-region fin 102 are exposed, the width of the upper portion of the P-region fin 101 is smaller than the width of the lower portion of the P-region fin 101.
In the embodiment of the invention, after the gate structure, the source/drain and the channel are formed on the exposed P-region fin portion 101 and the exposed N-region fin portion 102, the narrower P-region fin portion 101 can enable holes in the source/drain to diffuse towards the channel, and deplete electrons in the channel, that is, form an electron fully depleted layer. While avoiding leakage when no voltage is appliedThis occurs. Further, the upper width dimension l of the N-region fin 102 is larger than the upper portion of the P-region fin 1012The size is larger, after a subsequent structure is formed, the parasitic resistance can be reduced, and the performance of the semiconductor device is improved.
Because the materials of the fin portion and the protection layer are different, the etching rate and the etching degree of the etching process to the P region fin portion 101 and the first protection layer 110 are different. Therefore, in the embodiment of the present invention, 0.7. ltoreq. l1:l2≤0.9，1nm≤l2-l1Less than or equal to 2.5 nm. Specifically, in the present example,/1:l2＝0.7，l2-l1＝1nm。
In summary, in the method for forming the semiconductor device disclosed in the present invention, the width of the P region fin portion is smaller than the width of the N region fin portion at the channel, so that an electron fully-depleted layer is formed in the P region channel, the control capability of the gate structure on the semiconductor device is improved, the short channel effect is effectively suppressed, and the performance of the semiconductor device is improved.
Accordingly, with continued reference to fig. 5, an embodiment of the present invention further provides a semiconductor device, including: a semiconductor substrate 100 and a fin.
The semiconductor substrate 100 includes a PMOS region and an NMOS region, the fin portion includes a P-region fin portion and an N-region fin portion, and the P-region fin portion and the N-region fin portion are respectively disposed above the PMOS region and the NMOS region.
The semiconductor substrate 100 serves as a process base for forming a semiconductor device. The material of the semiconductor substrate 100 is at least one of the following materials: polysilicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and the like. In the embodiment of the present invention, the material of the semiconductor substrate 100 is polysilicon. Other structures may also be included in the semiconductor substrate 100, such as: the structures of metal plugs, metal connection layers, dielectric layers, etc., or other semiconductor devices including these structures, are not limited in this respect.
In the embodiment of the present invention, the material of the fin portion is the same as that of the semiconductor substrate 100.
In an embodiment of the present invention, the width dimension l of the upper portion of the P region fin 1011Is smaller than the width dimension l of the upper portion of the N region fin 102 2. After a channel is formed on the fin portion subsequently, the narrower P-region fin portion 101 enables holes to diffuse into the channel, and a fully depleted layer of electrons is formed in the channel, so that the control capability of the gate structure is improved, the short channel effect is effectively inhibited, and the performance of the semiconductor device is improved. Meanwhile, the wider N-region fin 102 can reduce parasitic resistance and improve the performance of the semiconductor device.
In the examples of the present invention, 0.7. ltoreq. l1:l2≤0.9，1nm≤l2-l1Less than or equal to 2.5 nm. Specifically, in the present example,/1:l2＝0.7，l2-l1＝1nm。
The embodiment of the invention also comprises a protective layer. The protective layer is arranged on the surface of the lower part of the fin part. The protective layer is used for protecting the fin portion and preventing the fin portion from being pulled by the stress of the interlayer dielectric layer 140.
In the embodiment of the present invention, the protective layer includes the first protective layer 110 and the second protective layer 130. The second passivation layer 130 is disposed between the interlayer dielectric layer 140 and the first passivation layer 110.
The material of the protective layer comprises SiNx、SiO2Or one or more combinations of alpha-Si. In the embodiment of the present invention, the materials of the first protection layer 110 and the second protection layer 130 are different, and the material of the first protection layer 110 is SiNxThe second passivation layer 130 is made of SiNxAnd alpha-Si. In other embodiments of the present invention, the materials of the first protective layer 110 and the second protective layer 130 may be the same.
The thickness of the first passivation layer 110 or the second passivation layer 130 is within a range of
Specifically, in the embodiment of the invention, the first protection layer 110 and the second protection layer 130 have the same thickness and are both the same
In other embodiments of the inventionIn an embodiment, the thicknesses of the first protective layer 110 and the second protective layer 130 may not be equal.
Here, the range of the lower portion of the fin portion is a region where the fin portion is in contact with the first protection layer 110, whereas the range of the upper portion of the fin portion is a region where the fin portion is not in contact with the first protection layer 110, please refer to fig. 5.
Obviously, in the embodiment of the present invention, the width dimension of the upper portion of the P-region fin portion is smaller than the width dimension of the lower portion of the P-region fin portion.
The embodiment of the invention also comprises the following steps: an interlevel dielectric layer 140. The interlayer dielectric layer 140 plays a role of isolation.
An interlevel dielectric layer 140 is formed between adjacent fins. In the embodiment of the present invention, the interlayer dielectric layer 140 covers the lower portion of the fin portion.
In summary, in the semiconductor device provided in the embodiments of the present invention, the width of the P-region fin is smaller than the width of the N-region fin, so that an electron fully-depleted layer is formed in the P-region channel, the control capability of the gate structure on the semiconductor device is improved, the short channel effect is effectively suppressed, and the performance of the semiconductor device is improved.
Second embodiment
Referring to fig. 6-8, the second embodiment is different from the first embodiment in that: a sacrificial layer and a second protective layer are not formed, and an interlayer dielectric layer is directly formed between the adjacent fin portions after the first protective layer is formed. The other process steps are identical to those of the first embodiment.
Referring to fig. 6, after forming an interlayer dielectric layer 240 between adjacent fins, the P-region fin 201 is etched and exposed.
The role of the semiconductor substrate 200 and the fin portion, and the selection of the material refer to the first embodiment.
The interlayer dielectric layer 240 makes the process steps for exposing the P-region fin portion and the N-region fin portion asynchronous, and also plays a role in isolation.
Please refer to the first embodiment, which will not be described herein.
The embodiment of the invention also comprises the following steps: a portion of the interlayer dielectric layer 240 is etched to expose the first protection layer 210 on the P region fin 201, and then the first protection layer 210 exposed on the P region fin 201 is etched. Etching only the first protection layer 210 on the P-region fin 201 can ensure that the thickness of the first protection layer 210 on the N-region fin 202 is always greater than the thickness of the first protection layer 210 on the P-region fin 201 in the subsequent process.
Specifically, in the embodiment of the present invention, the first protection layer 210 on the P-region fin 201 is completely removed, and the P-region fin 201 is exposed.
It should be noted that, in other embodiments of the present invention, only a portion of the first protection layer 210 on the P-region fin 201 may be removed as long as the condition that the thickness of the remaining first protection layer 210 on the P-region fin 201 is smaller than the thickness of the first protection layer 210 on the N-region fin 202 is satisfied.
In the embodiment of the present invention, the division standard of the upper portion and the lower portion of the fin portion is the same as that of the first embodiment, and is not described herein again.
Referring to fig. 7-8, the first passivation layer 210 on the N region fin 202 is exposed.
The embodiment of the invention also comprises the following steps: a portion of the ild layer 240 formed in the NMOS region is etched to expose the first protection layer 210 formed on the N region fin 202. The first protective layer 210 exposed in the NMOS region is then removed by etching, and the P region fin 201 is simultaneously etched to expose sidewalls of an upper portion of the P region fin 201 and sidewalls of an upper portion of the N region fin 202.
In the embodiment of the invention, since the thickness of the first protection layer 210 on the P-region fin 201 is less than the thickness of the first protection layer 210 on the N-region fin 202, after the etching is terminated, the width l of the P-region fin 201 at the exposed sidewall is larger than the width l of the P-region fin 201 at the exposed sidewall 1Is smaller than the width dimension l of the N region fin 202 at the exposed sidewalls2。l1And l2Please refer to the first embodiment. Specifically, in the present example,/1:l2＝0.9，l2-l1＝2.5nm。
Accordingly, please refer to fig. 8, and the embodiment of the present invention further provides a semiconductor device, a position relationship of the structures, and material selection and functions of the structures, which are not described herein again with reference to the first embodiment.
Since the second passivation layer is not formed in the embodiment of the invention, the interlayer dielectric layer 240 covers the surface of the first passivation layer 210.
Specifically, in the present example,/1:l2＝0.9，l2-l1＝2.5nm。
Third embodiment
Referring to fig. 9-10, the third embodiment is different from the second embodiment in that: and after etching part of the interlayer dielectric layer, simultaneously exposing the first protective layer on the upper parts of the N-region fin part and the P-region fin part. The same applies to the second embodiment.
Referring to fig. 9-10, a portion of the interlayer dielectric layer 340 is etched while exposing the first passivation layer 310 on the N-region fin and the P-region fin.
Then, a portion of the first protection layer 310 formed on the P region fin 301 is etched. Similarly, the first passivation layer 310 on the P region fin 301 may be removed entirely or only partially. As long as the condition that the thickness of the first protection layer 310 on the P-region fin 301 after the etching is smaller than the thickness of the first protection layer 310 on the N-region fin 302 is satisfied.
Similarly, the division criteria of the upper portion and the lower portion of the fin portion in the embodiment of the present invention are the same as those in the second embodiment, and are not described herein again.
The subsequent process steps are the same as those in the second embodiment, and are not described herein again.
Accordingly, the structure and the position relationship of the semiconductor device according to the embodiment of the present invention refer to the second embodiment, which is not described herein again.
Thus far, the present invention has been described in detail. Some details well known in the art have not been described in order to avoid obscuring the concepts of the present invention. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.
Although some specific embodiments of the present invention have been described in detail by way of illustration, it should be understood by those skilled in the art that the above illustration is only for the purpose of illustration and is not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (33)
1. A method of forming a semiconductor device, comprising:
Providing a semiconductor substrate and a fin part, wherein the semiconductor substrate comprises a PMOS area and an NMOS area, the fin part comprises a P area fin part and an N area fin part, and the P area fin part and the N area fin part are correspondingly formed above the PMOS area and the NMOS area respectively;
forming a first protective layer covering the surface of the fin part;
forming an interlayer dielectric layer between the adjacent fin parts;
removing part of the interlayer dielectric layer and part of the first protective layer to expose the side wall of the upper part of the P-region fin part and the side wall of the upper part of the N-region fin part;
the process step of exposing the side wall of the upper part of the P-area fin part and the side wall of the upper part of the N-area fin part comprises the following steps of:
etching part of the interlayer dielectric layer to expose the first protective layer formed on the upper part of the P-region fin part;
etching the first protection layer exposed at the upper part of the P-region fin part;
etching a part of the interlayer dielectric layer formed in the NMOS region to expose the first protective layer formed on the upper part of the N region fin part; and
and etching to remove the first protective layer exposed in the NMOS region, and etching the remaining first protective layer on the upper part of the P region fin part and part of the P region fin part, so that the width dimension of the upper part of the P region fin part on the exposed side wall is smaller than the width dimension of the upper part of the N region fin part on the exposed side wall.
2. The method as claimed in claim 1, wherein a width dimension of an upper portion of the P-region fin is smaller than a width dimension of a lower portion of the P-region fin after exposing sidewalls of the upper portion of the P-region fin and sidewalls of an upper portion of the N-region fin.
3. The method of claim 1, further comprising, after forming the first protective layer and before forming the interlevel dielectric layer:
forming a sacrificial layer between the adjacent fin parts;
removing a portion of the sacrificial layer to expose a portion of the first protection layer formed in the PMOS region;
removing the first protection layer exposed in the PMOS area to expose part of the P area fin part;
removing the remaining sacrificial layer to expose the remaining first protective layer; and
and forming a second protective layer on the surface of the first protective layer and the surface of the exposed P-region fin part, wherein the protective layer comprises the first protective layer and the second protective layer.
4. The method of claim 3, wherein the step of exposing the portion of the sidewall of the P-region fin and the portion of the sidewall of the N-region fin comprises:
Removing part of the interlayer dielectric layer to expose part of the second protective layer;
etching and removing the exposed second protective layer to expose the P-region fin portion and the first protective layer on the N-region fin portion; and
and etching and removing the first protective layer formed on the N-region fin portion and the exposed P-region fin portion.
5. The method according to claim 3, wherein a material of the protective layer comprises SiNx、SiO2Or one or more combinations of alpha-Si.
6. The semiconductor of claim 3A method of forming a bulk device, wherein the thickness dimension of the first protective layer or the second protective layer is in the range of
7. The method as claimed in claim 3, wherein after the interlayer dielectric layer is formed, a thickness of the protective layer on the upper surface of the P-region fin portion is smaller than a thickness of the protective layer on the upper surface of the N-region fin portion.
8. The method of claim 7, wherein after the inter-layer dielectric layer is formed, a thickness of the protective layer on the upper surface of the P-region fin is smaller than a thickness of the protective layer on the lower surface of the P-region fin, and the thickness of the protective layer on the lower surface of the P-region fin is equal to the thickness of the protective layer on the lower surface of the N-region fin.
9. The method of claim 1, wherein the process of forming the interlevel dielectric layer comprises a fluid chemical vapor deposition process.
10. The method as claimed in claim 9, further comprising performing an annealing process on the interlayer dielectric layer after the interlayer dielectric layer is formed.
11. The method of claim 10, wherein the annealing process comprises: firstly, carrying out water vapor annealing process treatment, and then carrying out rapid thermal annealing process treatment.
12. The method of claim 11, wherein the process parameters of the water vapor annealing process comprise: the annealing temperature range is 550-750 ℃, the annealing time range is 30-200 min, and the technological parameters of the rapid thermal annealing process comprise: the annealing temperature range is 950 ℃ to 1050 ℃, and the annealing time range is 15min to 100 min.
13. The method of claim 1, wherein the N-region fin has a width dimension of/, at exposed sidewalls2The width dimension of the P region fin part at the exposed side wall is l 1And then 0.7 is not more than l1:l2≤0.9。
14. The method of claim 13, wherein 1nm ≦ l2-l1≤2.5nm。
15. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate and a fin part, wherein the semiconductor substrate comprises a PMOS area and an NMOS area, the fin part comprises a P area fin part and an N area fin part, and the P area fin part and the N area fin part are respectively and correspondingly formed above the PMOS area and the NMOS area;
forming a first protective layer covering the surface of the fin portion;
forming an interlayer dielectric layer between the adjacent fin parts;
removing part of the interlayer dielectric layer and part of the first protective layer to expose the side wall of the upper part of the P-region fin part and the side wall of the upper part of the N-region fin part;
the process step of exposing the side wall of the upper part of the P-region fin part and the side wall of the upper part of the N-region fin part comprises the following steps:
etching part of the interlayer dielectric layer to expose the upper parts of the N-region fin parts and the P-region fin parts;
etching a part of the first protective layer formed on the upper part of the P-region fin part; and
and etching to remove the first protective layer formed on the upper part of the N-region fin part, the first protective layer left on the upper part of the P-region fin part and part of the P-region fin part, so that the width dimension of the upper part of the P-region fin part at the exposed side wall is smaller than the width dimension of the upper part of the N-region fin part at the exposed side wall.
16. The method of claim 15, wherein a width dimension of an upper portion of the P-region fin is less than a width dimension of a lower portion of the P-region fin after exposing sidewalls of the upper portion of the P-region fin and sidewalls of the upper portion of the N-region fin.
17. The method as claimed in claim 15, further comprising, after forming the first passivation layer and before forming the interlayer dielectric layer:
forming a sacrificial layer between the adjacent fin parts;
removing a portion of the sacrificial layer to expose a portion of the first protection layer formed in the PMOS region;
removing the first protection layer exposed in the PMOS area to expose part of the P area fin part;
removing the remaining sacrificial layer to expose the remaining first protective layer; and
and forming a second protective layer on the surface of the first protective layer and the surface of the exposed P-region fin part, wherein the protective layer comprises the first protective layer and the second protective layer.
18. The method of claim 17, wherein the step of exposing the sidewalls of the P-region fins and the sidewalls of the N-region fins comprises:
Removing part of the interlayer dielectric layer to expose part of the second protective layer;
etching and removing the exposed second protective layer to expose the P-region fin portion and the first protective layer on the N-region fin portion; and
and etching to remove the exposed first protective layer formed on the N-region fin part and the exposed P-region fin part.
19. According to the rightThe method of forming a semiconductor device according to claim 17, wherein a material of the protective layer includes SiNx、SiO2Or one or more combinations of alpha-Si.
20. The method for forming a semiconductor device according to claim 17, wherein a thickness of the first protective layer or the second protective layer is in a range of
21. The method as claimed in claim 17, wherein after the formation of the interlayer dielectric layer, a thickness of the protection layer on the upper surface of the P-region fin portion is smaller than a thickness of the protection layer on the upper surface of the N-region fin portion.
22. The method of claim 21, wherein after the inter-layer dielectric layer is formed, a thickness of the protective layer on the upper surface of the P-region fin is smaller than a thickness of the protective layer on the lower surface of the P-region fin, and the thickness of the protective layer on the lower surface of the P-region fin is equal to the thickness of the protective layer on the lower surface of the N-region fin.
23. The method of claim 15, wherein the process of forming the interlevel dielectric layer comprises a fluid chemical vapor deposition process.
24. The method as claimed in claim 23, further comprising performing an annealing process on the interlayer dielectric layer after the interlayer dielectric layer is formed.
25. The method of claim 24, wherein the annealing process comprises: firstly, carrying out water vapor annealing process treatment, and then carrying out rapid thermal annealing process treatment.
26. The method of forming a semiconductor device according to claim 25, wherein the process parameters of the water vapor annealing process comprise: the annealing temperature range is 550-750 ℃, the annealing time range is 30-200 min, and the technological parameters of the rapid thermal annealing process comprise: the annealing temperature range is 950 ℃ to 1050 ℃, and the annealing time range is 15min to 100 min.
27. The method of claim 15, wherein the N-region fin has a width dimension of/, at exposed sidewalls2The width of the P region fin portion at the exposed side wall is l 1And then 0.7 is not more than l1:l2≤0.9。
28. The method of claim 27, wherein 1nm ≦ l2-l1≤2.5nm。
29. A semiconductor device formed by the method for forming a semiconductor device according to any one of claims 1 to 28, the semiconductor device comprising:
the semiconductor substrate comprises a PMOS (P-channel metal oxide semiconductor) region and an NMOS (N-channel metal oxide semiconductor) region, the fin part comprises a P region fin part and an N region fin part, the P region fin part and the N region fin part are respectively and correspondingly arranged above the PMOS region and the NMOS region, and the width size of the upper part of the P region fin part is smaller than that of the upper part of the N region fin part;
the protective layer is arranged on the surface of the lower part of the fin part; and
and the interlayer dielectric layers are formed between the adjacent fin parts.
30. The semiconductor device of claim 29, wherein a width dimension of an upper portion of the N-region fin is/2The width dimension of the upper part of the P region fin partIs 11And then 0.7 is not more than l1:l2≤0.9。
31. The semiconductor device of claim 30, wherein 1nm ≦ l2-l1≤2.5nm。
32. The semiconductor device according to claim 29, wherein the protective layer comprises a first protective layer and a second protective layer, the second protective layer being provided between the interlayer dielectric layer and the first protective layer.
33. The semiconductor device of claim 29, wherein a width dimension of an upper portion of the P-region fin is less than a width dimension of a lower portion of the P-region fin.
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| CN113506732A (en) * | 2021-06-21 | 2021-10-15 | 上海华力集成电路制造有限公司 | Method for reducing cut-off effect of pseudo gate of FinFET (Fin field effect transistor) device |
| CN113782436A (en) * | 2021-08-12 | 2021-12-10 | 上海华力集成电路制造有限公司 | Method for reducing pseudo gate cut-off effect of fin type transistor |
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