US20180315673A1 - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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Publication number
US20180315673A1
US20180315673A1 US15/954,121 US201815954121A US2018315673A1 US 20180315673 A1 US20180315673 A1 US 20180315673A1 US 201815954121 A US201815954121 A US 201815954121A US 2018315673 A1 US2018315673 A1 US 2018315673A1
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Prior art keywords
pattern
monitor
product
semiconductor device
film
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Shigeya Toyokawa
Shuhei Yamaguchi
Koji Hasegawa
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Renesas Electronics Corp
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Renesas Electronics Corp
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Assigned to RENESAS ELECTRONICS CORPORATION reassignment RENESAS ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TOYOKAWA, SHIGEYA, HASEGAWA, KOJI, YAMAGUCHI, SHUHEI
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Definitions

  • the present invention relates to a semiconductor device and a manufacturing technique of the same, and relates to a technique effectively applied to, for example, a miniaturized semiconductor device in which a pattern defect may become apparent.
  • Patent Document 1 has described a technique relating to a testing circuit or a testing pattern known as TEG (Test Element Group).
  • a device structure and a wiring structure configuring the semiconductor device are miniaturized.
  • a pattern defect is likely to occur in a patterning process that uses a photolithography technique.
  • a pattern defect that becomes apparent as the semiconductor device is miniaturized is desired to be detected with high accuracy.
  • a semiconductor device includes a monitor pattern.
  • This monitor pattern has an evaluation pattern constituted by a first pattern and a second pattern opposite to each other in a first direction. Further, the first pattern is constituted by a convex shape protruding in a direction away from the second pattern in the first direction.
  • a pattern defect can be detected with high accuracy.
  • FIG. 1 is a diagram showing a layout configuration of a semiconductor chip according to a first embodiment of the present invention
  • FIG. 2 is a cross-sectional view showing a schematic device structure that includes a transistor and configures a logic circuit
  • FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment
  • FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 3 ;
  • FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 4 ;
  • FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 5 ;
  • FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 6 ;
  • FIG. 8 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 7 ;
  • FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor device continued from FIG. 8 ;
  • FIG. 10 is a flowchart showing a process flow in forming a wiring
  • FIG. 11 is a flowchart showing a process flow in testing for a pattern defect in a wiring pattern
  • FIG. 12 is a schematic diagram showing a planar layout configuration of a monitor pattern according to a related art
  • FIG. 13 is a photograph showing line-and-space patterns having a minimal line width and a minimal space width as an evaluation pattern
  • FIG. 14 is a photograph showing fine dot patterns formed at a minimal space interval as an evaluation pattern
  • FIG. 15A is a photograph showing a portion of a circuit pattern patterned at a best focus point
  • FIG. 15B is a photograph showing a portion of another circuit pattern patterned in a state where the focal position is deviated
  • FIG. 16 is a schematic diagram showing a planar layout configuration of a monitor pattern according to the first embodiment
  • FIG. 17 is a schematic diagram showing an enlarged evaluation pattern formed on a portion within a region of FIG. 16 ;
  • FIG. 18 is a schematic diagram showing another enlarged evaluation pattern formed on a portion within the region of FIG. 16 ;
  • FIG. 19A is a photograph showing a portion of a circuit pattern patterned at a best focus point
  • FIG. 19B is a photograph showing a first evaluation pattern patterned at the best focus point
  • FIG. 19C is a photograph showing a second evaluation pattern patterned at the best focus point
  • FIG. 20A is a photograph showing a portion of another circuit pattern patterned in a state where a focal position is deviated
  • FIG. 20B is a photograph showing the first evaluation pattern patterned in the state where the focal position is deviated
  • FIG. 20C is a photograph showing the second evaluation pattern patterned in the state where the focal position is deviated.
  • FIG. 21 is a schematic diagram showing a modification of the evaluation pattern
  • FIG. 22 is a schematic diagram showing another modification of the evaluation pattern
  • FIG. 23 is a schematic diagram showing another modification of the evaluation pattern
  • FIG. 24 is a schematic diagram showing a one-shot region that indicates a single exposure region corresponding to a unit for one projection in an exposure process of a photolithography technique
  • FIG. 25 is a schematic diagram showing an example of respectively arranging a plurality of monitor patterns within a predetermined number of chip regions.
  • FIG. 26 is a schematic diagram showing an example of arranging a plurality of monitor patterns within a semiconductor chip (chip region).
  • the number of a component when referring to the number of a component (including number of pieces, numerical value, amount, and range), the number is not limited to a specified number and may be less than or greater than this number unless otherwise clearly specified or unless it is obvious from the context that the number is limited to the specified number in principle.
  • each component (including an element step) is not indispensable unless otherwise clearly specified or unless it is obvious from the context that the component is indispensable in principle.
  • a substantially approximate shape, a similar shape, or the like is included unless otherwise clearly specified or unless it is obvious from the context that the shape, the positional relation, or the like of the component differs in principle. The same applies to the above-described numerical value and range.
  • FIG. 1 is a diagram showing a layout configuration of a semiconductor chip CHP according to a first embodiment of the present invention.
  • the semiconductor chip CHP of the first embodiment is rectangular in shape and includes, for example, an analog circuit region in which an analog circuit 1 is formed, a logic circuit region in which a logic circuit 2 controlling the analog circuit 1 is formed, and an I/O circuit region in which an input/output circuit (I/O circuit) 3 is formed.
  • a monitor pattern QC is formed in the vicinity of a corner portion of the semiconductor chip CHP of the first embodiment.
  • FIG. 2 is a cross-sectional view showing the schematic device structure that includes a transistor and configures the logic circuit 2 .
  • an element isolation region STI is formed within a semiconductor substrate 1 S, and a field-effect transistor is formed within an active region partitioned by this element isolation region STI.
  • FIG. 2 shows a CMOS transistor that is a basic component for configuring the logic circuit 2 . Namely, as shown in FIG. 2 , a p-channel type field-effect transistor Qp and an n-channel type field-effect transistor Qn are formed within the corresponding active region.
  • a silicon nitride film SNF is formed over the semiconductor substrate 1 S so as to cover the p-channel type field-effect transistor Qp and the n-channel type field-effect transistor Qn, and a silicon oxide film OXF is formed over this silicon nitride film SNF.
  • a contact interlayer insulating film CIL is formed by the silicon nitride film SNF and the silicon oxide film OXF.
  • a plug PLG 1 is formed in the contact interlayer insulating film CIL so as to penetrate the contact interlayer insulating film CIL and reach a surface of the semiconductor substrate 1 S.
  • each plug PLG 1 is formed in the contact interlayer insulating film CIL so as to reach a source region and a drain region of the p-channel type field-effect transistor Qp and a source region and a drain region of the n-channel type field-effect transistor Qn.
  • a wiring WL 1 made of, for example, an aluminum film or an aluminum alloy film is formed on the contact interlayer insulating film CIL in which the plug PLG 1 is formed.
  • an interlayer insulating film IL 1 made of, for example, a silicon oxide film is formed so as to cover the wiring WL 1 formed on the contact interlayer insulating film CIL, and a plug PLG 2 is formed in this interlayer insulating film IL 1 so as to penetrate the interlayer insulating film IL 1 and reach the wiring WL 1 .
  • a wiring WL 2 made of, for example, an aluminum film or an aluminum alloy film is formed on the interlayer insulating film IL 1 in which the plug PLG 2 is formed.
  • an interlayer insulating film IL 2 made of, for example, a silicon oxide film is formed over the interlayer insulating film IL 1 so as to cover the wiring WL 2 , and a plug PLG 3 is formed in this interlayer insulating film IL 2 so as to penetrate the interlayer insulating film IL 2 .
  • a wiring WL 3 is formed on the interlayer insulating film IL 2 in which the plug PLG 3 is formed, and an interlayer insulating film IL 3 made of, for example, a silicon oxide film is formed so as to cover this wiring WL 3 . Further, a surface protective film (passivation film) PAS made of, for example, a silicon nitride film is formed over the interlayer insulating film IL 3 . In this manner, the logic circuit 2 having the device structure as shown in FIG. 2 is formed within the semiconductor chip CHP (see FIG. 1 ).
  • the semiconductor substrate 1 S is prepared. Then, a plurality of semiconductor regions are formed within the semiconductor substrate 1 S by using, for example, a photolithography technique and an ion implantation process. Next, as shown in FIG. 3 , after a silicon oxide film is formed over the surface of the semiconductor substrate 1 S, a mask film MSF made of a silicon nitride film is formed over this silicon oxide film. Then, the mask film MSF is patterned by using, for example, the photolithography technique and an etching technique.
  • a portion of the semiconductor substrate 1 S is etched with using the patterned mask film MSF as a hard mask.
  • a trench DIT aligned with the mask film MSF is formed on the surface of the semiconductor substrate 1 S.
  • an insulating film silicon oxide film
  • excessive insulating films formed over this surface are removed, so that the insulating film is left only inside the trench DIT.
  • the element isolation region having a structure in which the trench DIT is filled with the insulating film can be formed. A region of the semiconductor substrate 1 S partitioned by this element isolation region becomes the active region.
  • a gate insulating film GOX made of, for example, a silicon oxide film is formed over the surface of the semiconductor substrate 1 S
  • a polysilicon film PF is formed over the gate insulating film GOX.
  • the polysilicon film PF can be formed by using, for example, a CVD (Chemical Vapor Deposition) process.
  • CVD Chemical Vapor Deposition
  • a dual-gate structure that is a structure capable of reducing a threshold voltage at both the p-channel type field-effect transistor and the n-channel type field-effect transistor is formed.
  • a p-type impurity (acceptor) is implanted into the polysilicon film PF formed within a p-channel type field-effect transistor forming region
  • an n-type impurity (donor) is implanted into the polysilicon film PF formed within an n-channel type field-effect transistor forming region by using, for example, the ion implantation process.
  • the polysilicon film PF is patterned by using the photolithography technique and the etching technique.
  • a gate electrode GE 1 can be formed within the p-channel type field-effect transistor forming region
  • a gate electrode GE 2 can be formed within the n-channel type field-effect transistor forming region.
  • an extension region aligned with the gate electrode GE 1 is formed within the semiconductor substrate 1 S, and an extension region aligned with the gate electrode GE 2 is formed within the semiconductor substrate 15 by using, for example, the photolithography technique and the ion implantation process. Further, sidewall spacers made of, for example, a silicon oxide film are respectively formed on both sidewalls of the gate electrode GE 1 and both sidewalls of the gate electrode GE 2 .
  • semiconductor regions configuring a portion of the source region and a portion of the drain region of the p-channel type field-effect transistor are formed within the semiconductor substrate 1 S so as to be aligned with the sidewall spacers formed on both sidewalls of the gate electrode GE 1 .
  • semiconductor regions configuring a portion of the source region and a portion of the drain region of the n-channel type field-effect transistor are formed within the semiconductor substrate 15 so as to be aligned with the sidewall spacers formed on both sidewalls of the gate electrode GE 2 . Further, as shown in FIG.
  • a silicide film is formed in order to reduce resistance of the gate electrode GE 1 , the gate electrode GE 2 , each source region, and each drain region.
  • the p-channel type field-effect transistor Qp can be formed within the p-channel type field-effect transistor forming region of the semiconductor substrate 1 S
  • the n-channel type field-effect transistor Qn can be formed within the n-channel type field-effect transistor forming region of the semiconductor substrate 1 S.
  • the silicon nitride film SNF is formed so as to cover the p-channel type field-effect transistor Qp and the n-channel type field-effect transistor Qn formed on the semiconductor substrate 1 S, and the silicon oxide film OXF is formed over this silicon nitride film SNF.
  • the silicon nitride film SNF and the silicon oxide film OXF can be formed by using, for example, the CVD process.
  • the contact interlayer insulating film CIL is formed by the silicon nitride film SNF and the silicon oxide film OXF.
  • a contact hole is formed on the contact interlayer insulating film CIL so as to penetrate the contact interlayer insulating film CIL, and a tungsten film is formed over the contact interlayer insulating film CIL including an inside of this contact hole. Further, the excessive tungsten film formed over the contact interlayer insulating film CIL is removed by using, for example, a chemical mechanical polishing process, so that the tungsten film is left only inside the contact hole to form the plug PLG 1 made of the tungsten film filled in the contact hole.
  • a conductive film CF 1 is formed over the contact interlayer insulating film CIL in which the plug PLG 1 is formed.
  • This conductive film CF 1 is made of, for example, an aluminum film or an aluminum alloy film and can be formed by using, for example, a sputtering process.
  • the conductive film CF 1 is patterned by using the photolithography technique and the etching technique to form the wiring WL 1 . Descriptions of subsequent steps will be omitted as appropriate.
  • the device structure that includes the field-effect transistor and the wiring can be manufactured in this manner.
  • FIG. 10 is a flowchart showing a process flow informing the wiring WL 1 .
  • the conductive film conductive film CF 1
  • the interlayer insulating film contact interlayer insulating film CIL
  • This conductive film is made of, for example, an aluminum film or an aluminum alloy film, and can be formed by using, for example, the sputtering process.
  • a resist film is applied over the conductive film by using, for example, a spin-coating process (S 102 ). Then, an exposure process is performed on the resist film applied over the conductive film (S 103 ). Next, a development process is performed on the resist film on which the exposure process was performed (S 104 ). As a result, patterning of the resist film is completed (S 105 ).
  • the conductive film is etched with using the patterned resist film as a mask (S 106 ).
  • a wiring pattern (wiring) and a monitor pattern composed of the patterned conductive film can be formed (S 107 ).
  • the wiring pattern is tested for occurrence of a pattern defect based on an evaluation pattern included in the monitor pattern (S 108 ).
  • FIG. 11 is a flowchart showing a process flow in testing for a pattern defect in the wiring pattern.
  • the evaluation pattern included in the monitor pattern is tested for presence of a pattern defect (S 201 ). For example, if patterns which should be formed apart from each other are formed so as to be bridged, it is considered that a pattern defect corresponding to a short-circuit failure is present.
  • a pattern defect is present in the evaluation pattern, it is determined that a pattern defect is present in the wiring pattern formed in the same step as the evaluation pattern (S 203 ).
  • a pattern defect is not present in the evaluation pattern, it is determined that a pattern defect is not present in the wiring pattern formed in the same step as the evaluation pattern (S 204 ).
  • it is determined in the first embodiment whether a pattern defect is occurring or not occurring in the wiring pattern by testing for presence or non-presence of a pattern defect in the evaluation pattern included in the monitor pattern formed in the same step as the wiring pattern. Therefore, it is clear that the selection of the evaluation pattern included in the monitor pattern is important in testing for a pattern defect in the wiring pattern.
  • the monitor pattern which is not a product pattern is formed in the same step as the wiring pattern partially configuring the product pattern, and the wiring pattern is tested for occurrence of a pattern defect by testing for occurrence or non-occurrence of a pattern defect in the evaluation pattern included in the monitor pattern. Therefore, it is important that the evaluation pattern included in the monitor pattern is a pattern capable of exactly reflecting a pattern defect in the wiring pattern.
  • FIG. 12 is a schematic diagram showing a planar layout configuration of a monitor pattern MP according to the related art.
  • the monitor pattern MP of the related art includes various types of patterns represented by a product random pattern, a logic pattern, and a memory pattern, the actual testing process will use a portion of the evaluation pattern included in the monitor pattern to perform tests for a pattern defect in a portion of the product pattern formed in the same step as the monitor pattern.
  • FIG. 13 shows line-and-space patterns each having a minimal line width and a minimal space width being used as the evaluation pattern.
  • the line-and-space patterns having the minimal line width and the minimal space width are most likely to be bridged and cause a pattern defect, and thus, it is considered that occurrence of a pattern defect in the product pattern can be detected with high accuracy by using the line-and-space patterns having the minimal line width and the minimal space width as the evaluation pattern.
  • FIG. 14 shows fine dot patterns formed at a minimal space interval being used as the evaluation pattern.
  • the fine dot patterns are likely to be bridged and cause a pattern defect, and thus, it is considered that occurrence of a pattern defect in the product pattern can be detected with high accuracy by using the fine dot patterns formed at the minimal space interval as the evaluation pattern.
  • the product pattern is tested for occurrence of a pattern defect by using the line-and-space patterns shown in FIG. 13 or the fine dot patterns shown in FIG. 14 as the evaluation pattern.
  • a testing process is adopted such that when a pattern defect occurs in the line-and-space patterns shown in FIG. 13 or in the fine dot patterns shown in FIG. 14 , it is determined that a pattern defect is occurring in a portion of the product pattern.
  • the present inventors have found that the product pattern includes a portion in which a pattern defect is more likely to occur than the line-and-space patterns shown in FIG. 13 or the fine dot patterns shown in FIG. 14 .
  • the product pattern includes a shape that is more sensitive to focal position deviation than the line-and-space patterns shown in FIG. 13 or the fine dot patterns shown in FIG. 14 .
  • FIG. 13 the line-and-space patterns shown in FIG. 13 or the fine dot patterns shown in FIG. 14 of the related art as the evaluation pattern.
  • FIG. 15A is a photograph showing a portion of a circuit pattern patterned at a best focus point, and it can be seen in FIG. 15A that the patterns are separate from each other at a location indicated by an arrow.
  • FIG. 15B is a photograph showing a portion of another circuit pattern patterned in a state where the focal position is deviated. It can be seen in FIG. 15B that the patterns which should be separate from each other are bridged at a location indicated by an arrow, thereby causing a pattern defect.
  • the correspondence relation between the evaluation pattern included in the monitor pattern and the product pattern is insufficient in regards to detecting a pattern defect, and there is room for improvement in that a pattern defect in the product pattern cannot be detected with high accuracy by using this evaluation pattern. Namely, there is room for improvement in that the related art does not adopt an evaluation pattern that is capable of detecting a pattern defect in the product pattern caused by focal position deviation with high accuracy.
  • the first embodiment is devised such that a pattern defect in the product pattern caused by focal position deviation can be detected with high accuracy.
  • the technical idea of the devised first embodiment will be described below.
  • the “monitor pattern” is defined as a pattern that is separate from the product pattern and has a shape corresponding to a portion of the product pattern. Further, the above-defined “monitor pattern” is formed on the semiconductor chip of the first embodiment in addition to the conventional product pattern. Additionally, the “monitor pattern” includes an “evaluation pattern” that is used to detect a pattern defect in the product pattern.
  • FIG. 16 is a schematic diagram showing a planar layout configuration of a monitor pattern MP 1 according to the first embodiment.
  • the monitor pattern MP 1 of the first embodiment is provided with the evaluation pattern surrounded by a region RA in addition to the monitor pattern MP of the related art shown in FIG. 12 .
  • Other components and features of the monitor pattern MP 1 of the first embodiment shown in FIG. 16 are equivalent to those of the monitor pattern MP of the related art shown in FIG. 12 .
  • FIG. 17 is a schematic diagram showing an enlarged evaluation pattern VP 1 formed within the region RA of FIG. 16 .
  • the evaluation pattern VP 1 of the first embodiment is constituted by a pattern (first pattern) P 1 and another pattern (second pattern) P 2 opposite to each other in an X direction (first direction).
  • the pattern P 1 is composed of a convex shape protruding in a direction away from the pattern P 2 in the X direction.
  • the pattern P 2 is composed of a convex shape protruding in a direction away from the pattern P 1 in the X direction.
  • the product pattern has a first layer wiring pattern (wiring WL 1 of FIG. 2 ) formed above the semiconductor substrate 1 S (see FIG. 2 ), and the monitor pattern is formed in the same layer as, for example, the first layer wiring pattern (wiring WL 1 of FIG. 2 ).
  • FIG. 18 is a schematic diagram showing an enlarged evaluation pattern VP 2 formed within the region RA of FIG. 16 .
  • the evaluation pattern VP 2 of the first embodiment is constituted by a pattern (first pattern) P 1 and another pattern (second pattern) P 2 opposite to each other in the X direction (first direction).
  • the pattern P 1 is composed of a convex shape protruding in a direction away from the pattern P 2 in the X direction.
  • the pattern P 2 is composed of a rectangular shape.
  • FIG. 19A is a photograph showing a portion of the circuit pattern patterned at the best focus point.
  • FIG. 19B is a photograph showing the evaluation pattern VP 1 patterned at the best focus point
  • FIG. 19C is a photograph showing the evaluation pattern VP 2 patterned at the best focus point.
  • a pattern defect does not occur in the portion of the circuit pattern PP as well as in the evaluation pattern VP 1 and the evaluation pattern VP 2 when patterned at the best focus point. Therefore, it can be seen that, when attention is first directed to patterning at the best focus point, the evaluation pattern VP 1 and the evaluation pattern VP 2 can be used to detect a pattern defect in a portion of the circuit pattern PP.
  • FIG. 20A is a photograph showing a portion of another circuit pattern PP patterned in a state where the focal position is deviated.
  • FIG. 20B is a photograph showing the evaluation pattern VP 1 patterned in the state where the focal position is deviated
  • FIG. 20C is a photograph showing the evaluation pattern VP 2 patterned in the state where the focal position is deviated.
  • FIGS. 20A to 20C it can be seen that a pattern defect occurs in the portion of the circuit pattern PP (indicated by an arrow in FIG. 20A ) as well as in the evaluation pattern VP 1 and the evaluation pattern VP 2 (indicated by arrows in FIGS.
  • the evaluation pattern VP 1 and the evaluation pattern VP 2 can be used to detect a pattern defect in a portion of the circuit pattern PP.
  • the feature of the first embodiment is that the presence or non-presence of a pattern defect in a portion of the product pattern is detected by using the monitor pattern MP 1 (see FIG. 16 ) that includes, for example, the evaluation pattern VP 1 shown in FIG. 17 or the evaluation pattern VP 2 shown in FIG. 18 .
  • the feature of the first embodiment is that it is determined that a pattern defect is present in a portion of the product pattern when a pattern defect is present in the evaluation pattern VP 1 or the evaluation pattern VP 2 , whereas it is determined that a pattern defect is not present in the product pattern when a pattern defect is not present in the evaluation pattern VP 1 or the evaluation pattern VP 2 .
  • the presence or non-presence of a pattern defect in a portion of the product pattern patterned in a state where the focal position is deviated can be detected with high accuracy.
  • the presence or non-presence of a pattern defect in, for example, the evaluation pattern VP 1 and the evaluation pattern VP 2 adopted in the first embodiment accurately coincides with the presence or non-presence of a pattern defect in a portion of the product pattern as shown in FIGS. 19A to 19C and FIGS. 20A to 20C .
  • the technical significance of the feature of the first embodiment resides in finding the evaluation pattern that accurately reflects the presence or non-presence of a pattern defect in a portion of the product pattern caused by a slight deviation in the focal position, and accordingly, the presence or non-presence of a pattern defect in a portion of the product pattern can be detected with high accuracy.
  • the first embodiment has a great technical significance in that it specifically provides the evaluation pattern that accurately reflects the presence or non-presence of a pattern defect in a portion of the product pattern caused by a slight deviation in the focal position.
  • the feature of the first embodiment has a great technical significance in that a specific configuration capable of achieving a significant effect not achievable by the related art is provided together with a fundamental concept.
  • the fundamental concept of the first embodiment is to provide the evaluation pattern that accurately reflects the presence or non-presence of a pattern defect in a portion of the product pattern caused by a slight deviation in the focal position.
  • the various specific configurations conforming to this fundamental concept without being limited to the evaluation pattern VP 1 shown in FIG. 17 or the evaluation pattern VP 2 shown in FIG. 18 make it capable to achieve a significant effect in which a pattern defect in a portion of the product pattern is detected with high accuracy.
  • the fundamental concept of the first embodiment was made because it was found that the evaluation pattern VP 1 shown in FIG. 17 and the evaluation pattern VP 2 shown in FIG. 18 sensitively reacted when patterned in a state where the focal position was deviated.
  • a technical significance to use the evaluation pattern VP 1 shown in FIG. 17 and the evaluation pattern VP 2 shown in FIG. 18 resides in finding that a pattern defect appears even with a slight deviation in the focal position because the evaluation pattern VP 1 shown in FIG. 17 and the evaluation pattern VP 2 shown in FIG. 18 react more sensitively than the evaluation patterns of the line-and-space patterns shown in FIG. 13 or the fine dot patterns shown in FIG. 14 when patterned in a state where the focal position is deviated.
  • the evaluation pattern VP 1 and the evaluation pattern VP 2 have more convex portions than the line-and-space patterns or the fine dot patterns, and each convex portion has a tendency to blur while expanding due to focal position deviation.
  • the evaluation pattern VP 1 shown in FIG. 17 and the evaluation pattern VP 2 shown in FIG. 18 are used to detect a pattern defect in a portion of the product pattern with high accuracy because the evaluation pattern VP 1 and the evaluation pattern VP 2 each have the convex portion that is likely to expand, whereby the evaluation pattern VP 1 and the evaluation pattern VP 2 are more likely to be bridged and cause a pattern defect than the line-and-space patterns or the fine dot patterns that do not have the convex portion.
  • An evaluation pattern VP 3 shown in FIG. 21 and an evaluation pattern VP 4 shown in FIG. 22 can be given as examples of other specific configurations capable of achieving the fundamental concept of the first embodiment.
  • the evaluation pattern VP 3 shown in FIG. 21 has a pattern P 1 and a pattern P 2 opposite to each other in the X direction (first direction), and the pattern P 1 is constituted by a convex shape protruding in a direction toward the pattern P 2 in the first direction.
  • an evaluation pattern VP 5 shown in FIG. 23 is an example in which a pattern similar to the evaluation pattern VP 1 shown in FIG.
  • the evaluation pattern VP 5 shown in FIG. 23 has a pattern P 1 and a pattern P 2 opposite to each other in the X direction (first direction). Further, the pattern P 1 is achieved by three fine dot patterns overlapping one another, and the pattern P 2 is also achieved by three fine dot patterns overlapping one another.
  • the evaluation pattern VP 1 shown in FIG. 17 can be used in the wiring process (forming processes for the first layer wiring, a second layer wiring, and a third layer wiring).
  • the evaluation pattern VP 5 shown in FIG. 23 can be used in, for example, the forming processes for an element isolation trench and a gate electrode pattern.
  • each of the chip regions within the semiconductor substrate prepared in the step (a) includes a product region in which the product pattern is formed and a monitor region in which the monitor pattern that is a separate pattern from the product pattern and has a shape corresponding to a portion of the product pattern is formed.
  • a product configuration pattern partially configuring the product pattern is formed within the product region, and the monitor pattern is formed within the monitor region.
  • the monitor pattern has the evaluation pattern constituted by the first pattern and the second pattern opposite to each other in the first direction (X direction), and the first pattern is constituted by a convex shape protruding in the direction away from the second pattern in the first direction.
  • the product configuration pattern formed within the product region is tested for occurrence of a pattern defect based on the evaluation pattern included in the monitor pattern formed within the monitor region.
  • the step (d) includes a step of determining that a pattern defect is occurring in the product configuration pattern when the first pattern and the second pattern of the evaluation pattern are bridged. Additionally, in the step (c), the photolithography technique is used.
  • the step (c) has the steps of: (c1) applying the resist film over the film; (c2) performing the exposure process on the resist film; (c3) after the step (c2), performing the development process on the resist film; and (c4) after the step (c3), etching the film with using the patterned resist film as the mask to pattern the film.
  • the exposure process is performed on the resist film, with a predetermined number of chip regions among the plurality of chip regions being used as a unit for one shot of exposure.
  • the step (b) is a step in which the conductive film is formed over the interlayer insulating film formed above the semiconductor substrate
  • the step (c) is a step in which the wiring pattern is formed on the interlayer insulating film.
  • the fundamental concept of the first embodiment is applicable to, for example, the wiring process shown in FIGS. 8 and 9 .
  • the step (b) is a step in which the insulating film is formed over the semiconductor substrate
  • the step (c) is a step in which a mask pattern for forming the element isolation trench on the semiconductor substrate is formed.
  • the fundamental concept of the first embodiment is applicable to, for example, the forming process for the element isolation trench shown in FIGS. 3 and 4 .
  • the step (b) is a step in which the conductive film is formed over the gate insulating film formed over the semiconductor substrate
  • the step (c) is a step in which the gate electrode pattern is formed on the gate insulating film.
  • the fundamental concept of the first embodiment is applicable to, for example, the forming process for the gate electrode shown in FIGS. 5 and 6 .
  • the product pattern includes the gate electrode pattern formed on the semiconductor substrate with the gate insulating film interposed therebetween, and the monitor pattern is formed in the same layer as the gate electrode pattern.
  • the fundamental concept of the above-described first embodiment is a concept that achieves the object in which a pattern defect in the product pattern caused by focal position deviation is detected with high accuracy.
  • a fundamental concept of a second embodiment of the present invention is a concept that has a different approach than the fundamental concept of the above-described first embodiment and is based on the premise of achieving an object in which a pattern defect in the product pattern caused by location dependency of the focal position is detected with high accuracy.
  • FIG. 25 is a schematic diagram showing a one-shot region SR that indicates a single exposure region corresponding to a unit for one projection in the exposure process of the photolithography technique.
  • a plurality of chip regions CR within the semiconductor substrate (semiconductor wafer) are included in the one-shot region SR. Namely, the exposure process of the photolithography technique is simultaneously performed on a predetermined number of chip regions CR.
  • the one-shot region SR is a spacious region that includes the predetermined number of chip regions CR. Further, in the exposure process, a mask pattern of a mask arranged in an exposure system is projected onto the predetermined number of chip regions CR in the one-shot region SR via a reduction lens system. At this time, lens aberration occurs in the reduction lens system, and this aberration may cause deviation between, for example, the focal position of the chip region CR arranged at a central region of the one-shot region SR and the focal position of the chip region CR arranged at an end region of the one-shot region SR.
  • the monitor pattern is formed at, for example, only one location within the one-shot region SR, location dependency of the focal position due to lens aberration may cause a pattern defect to occur in the product pattern within the chip region CR arranged at a position distant from this monitor pattern, even if a pattern defect does not occur in the evaluation pattern included in the monitor pattern.
  • the monitor pattern were provided at only one location within the one-shot region SR, it would be impossible to detect a pattern defect in all of the product patterns within the predetermined number of chip regions CR in the one-shot region SR by using the evaluation pattern included in this monitor pattern.
  • the monitor pattern QC is formed within, for example, each of the chip regions CR in the one-shot region SR.
  • a pattern defect in the chip region CR arranged at, for example, the central region of the one-shot region SR can be detected based on the evaluation pattern of the monitor pattern QC arranged within this chip region CR.
  • a pattern defect in the chip region CR arranged at the end region of the one-shot region SR can be detected based on the evaluation pattern of the monitor pattern QC arranged within this chip region CR. Namely, as shown in FIG.
  • the pattern in a configuration in which the monitor pattern QC is formed within each chip region CR in the one-shot region SR, the pattern is less likely to be affected by location dependency of the focal position due to lens aberration, and accordingly, all pattern defects in the product pattern within each chip region CR in the one-shot region SR can be detected with high accuracy. Note that, even if the monitor pattern QC is formed within each chip region CR in the one-shot region SR as shown in FIG. 24 , it is considered that there may be a case where this is insufficient in regards to detecting a pattern defect in all of the product patterns formed within an individual chip region CR.
  • each of the chip regions CR in the one-shot region SR of the second embodiment is provided with, for example, a plurality of monitor patterns (QC 1 , QC 2 ) instead of being provided with a single monitor pattern.
  • a feature of the second embodiment is that an individual semiconductor chip (chip region before singulation) has a plurality of monitor regions in which monitor patterns that are separate patterns from the product pattern and have a shape corresponding to a portion of the product pattern are formed.
  • the evaluation pattern included in, for example, the monitor pattern QC 1 within the chip region CR can be used to detect a pattern defect in the product pattern arranged at a region closer to the monitor pattern QC 1 than to the monitor pattern QC 2 .
  • the evaluation pattern included in the monitor pattern QC 2 within the chip region CR can be used to detect a pattern defect in the product pattern arranged at a region closer to the monitor pattern QC 2 than to the monitor pattern QC 1 .
  • the second embodiment it is possible to further suppress a mismatch between the presence or non-presence of a pattern defect in the evaluation pattern and the presence or non-presence of a pattern defect in the product pattern caused by location dependency of the focal position.
  • an object of the second embodiment in which a pattern defect in the product pattern caused by location dependency of the focal position is detected with high accuracy is sufficiently achieved by an approach that differs from the approach of the above-described first embodiment.
  • the fundamental concept of the second embodiment is not limited to a configuration in which, for example, the plurality of monitor regions are respectively formed at corner portions of each rectangular semiconductor chip (chip region CR before singulation) as shown in FIG. 25 .
  • the monitor pattern QC 1 can be arranged in, for example, the vicinity of a corner portion of the semiconductor chip CHP, whereas the monitor pattern QC 2 can be arranged closer to the vicinity of the logic circuit region in which the logic circuit 2 composed of a high density pattern is formed than to a circuit other than the logic circuit 2 .
  • the evaluation pattern included in the monitor pattern QC 2 arranged in the vicinity of the logic circuit 2 is used, whereby a pattern defect in the product pattern caused by location dependency of the focal position can be detected with high accuracy.
  • a semiconductor device including a semiconductor chip on which a monitor pattern that is a separate pattern from a product pattern is formed
  • the monitor pattern has an evaluation pattern constituted by a first pattern and a second pattern opposite to each other in a first direction, and
  • the first pattern is constituted by a convex shape protruding in a direction toward the second pattern in the first direction.
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Citations (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4758863A (en) * 1987-02-17 1988-07-19 Hewlett-Packard Company Multi-image reticle
US5434026A (en) * 1989-11-13 1995-07-18 Nikon Corporation Exposure condition measurement method
US5674650A (en) * 1994-08-02 1997-10-07 U.S. Philips Corporation Method of repetitively imaging a mask pattern on a substrate, and apparatus for performing the method
US20010053489A1 (en) * 1998-11-23 2001-12-20 Philips Corporation And Asm Lithography B.V. Method of detecting aberrations of an optical imaging system
US20010055720A1 (en) * 2000-06-08 2001-12-27 Kabushiki Kaisha Toshiba Alignment method, overlay deviation inspection method and photomask
US20020022184A1 (en) * 2000-08-15 2002-02-21 Hitachi, Ltd. Method of manufacturing a photomask
US6639677B1 (en) * 1999-09-21 2003-10-28 Canon Kabushiki Kaisha Position measuring method and position measuring system using the same
US20030206027A1 (en) * 1999-04-28 2003-11-06 Hitachi, Ltd. Method of inspecting circuit pattern and inspecting instrument
US20040130690A1 (en) * 2002-09-20 2004-07-08 Asml Netherlands B.V. Alignment system and methods for lithographic systems using at least two wavelengths
US20050030537A1 (en) * 2003-08-07 2005-02-10 Canon Kabushiki Kaisha Mark position measuring method and apparatus
US20050095509A1 (en) * 2003-11-05 2005-05-05 Mosel Vitelic, Inc. Method for providing representative features for use in inspection of photolithography mask and for use in inspection photo-lithographically developed and/or patterned wafer layers, and products of same
US20050184362A1 (en) * 2004-01-26 2005-08-25 Harumitsu Fujita Semiconductor substrate
US20060093963A1 (en) * 2004-11-02 2006-05-04 Fujitsu Limited Manufacturing method of semiconductor device
US20070023915A1 (en) * 2005-07-29 2007-02-01 Jui-Meng Jao On-chip test circuit for assessing chip integrity
US20070133861A1 (en) * 2005-12-09 2007-06-14 Byung-Hun Do Apparatus and method for inspecting overlay patterns in semiconductor device
US20090312981A1 (en) * 2008-06-13 2009-12-17 Elpida Memory, Inc. Alignment mark and alignment method using the alignment mark
US7667842B2 (en) * 2005-09-30 2010-02-23 GlobalFoundries, Inc. Structure and method for simultaneously determining an overlay accuracy and pattern placement error
US20100092882A1 (en) * 2008-10-14 2010-04-15 Canon Kabushiki Kaisha Exposure apparatus and device fabrication method
US20100123887A1 (en) * 2008-11-17 2010-05-20 Asml Netherlands B.V. Method for a lithographic apparatus
US7804994B2 (en) * 2002-02-15 2010-09-28 Kla-Tencor Technologies Corporation Overlay metrology and control method
US7998826B2 (en) * 2007-09-07 2011-08-16 Macronix International Co., Ltd. Method of forming mark in IC-fabricating process
US20110248387A1 (en) * 2010-04-13 2011-10-13 Renesas Electronics Corporation Semiconductor integrated circuit and pattern layouting method for the same
US20120322169A1 (en) * 2011-06-16 2012-12-20 Renesas Electronics Corporation Method of manufacturing semiconductor device
US20130075938A1 (en) * 2011-09-23 2013-03-28 Semiconductor Manufacturing International (Beijing) Corporation Photolithography alignment mark, mask and semiconductor wafer containing the same mark
US20130147066A1 (en) * 2011-12-08 2013-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for e-beam in-chip overlay mark
US20130234019A1 (en) * 2010-11-24 2013-09-12 Atsushi Miyamoto Global alignment using multiple alignment pattern candidates
US20150186581A1 (en) * 2013-12-30 2015-07-02 Asml Netherlands B.V. Method and apparatus for design of a metrology target
US20150332452A1 (en) * 2014-05-14 2015-11-19 Nuflare Technology, Inc. Inspection method, template substrate, and focus offset method
US20160179017A1 (en) * 2014-06-21 2016-06-23 Kla-Tencor Corporation Compound imaging metrology targets
US20160266505A1 (en) * 2015-01-30 2016-09-15 Kla-Tencor Corporation Device metrology targets and methods
US9470987B1 (en) * 2015-10-22 2016-10-18 United Microelectronics Corp. Overlay mask
US20170329217A1 (en) * 2016-05-10 2017-11-16 Canon Kabushiki Kaisha Position detector, position detection method, imprint apparatus, and product manufacturing method
US10079185B1 (en) * 2017-06-23 2018-09-18 United Microelectronics Corp. Semiconductor pattern for monitoring overlay and critical dimension at post-etching stage and metrology method of the same
US20190310554A1 (en) * 2016-12-16 2019-10-10 Asml Netherlands B.V. Method and apparatus for image analysis

Patent Citations (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4758863A (en) * 1987-02-17 1988-07-19 Hewlett-Packard Company Multi-image reticle
US5434026A (en) * 1989-11-13 1995-07-18 Nikon Corporation Exposure condition measurement method
US5674650A (en) * 1994-08-02 1997-10-07 U.S. Philips Corporation Method of repetitively imaging a mask pattern on a substrate, and apparatus for performing the method
US20010053489A1 (en) * 1998-11-23 2001-12-20 Philips Corporation And Asm Lithography B.V. Method of detecting aberrations of an optical imaging system
US20030206027A1 (en) * 1999-04-28 2003-11-06 Hitachi, Ltd. Method of inspecting circuit pattern and inspecting instrument
US6639677B1 (en) * 1999-09-21 2003-10-28 Canon Kabushiki Kaisha Position measuring method and position measuring system using the same
US20010055720A1 (en) * 2000-06-08 2001-12-27 Kabushiki Kaisha Toshiba Alignment method, overlay deviation inspection method and photomask
US20020022184A1 (en) * 2000-08-15 2002-02-21 Hitachi, Ltd. Method of manufacturing a photomask
US7804994B2 (en) * 2002-02-15 2010-09-28 Kla-Tencor Technologies Corporation Overlay metrology and control method
US20040130690A1 (en) * 2002-09-20 2004-07-08 Asml Netherlands B.V. Alignment system and methods for lithographic systems using at least two wavelengths
US20050030537A1 (en) * 2003-08-07 2005-02-10 Canon Kabushiki Kaisha Mark position measuring method and apparatus
US20050095509A1 (en) * 2003-11-05 2005-05-05 Mosel Vitelic, Inc. Method for providing representative features for use in inspection of photolithography mask and for use in inspection photo-lithographically developed and/or patterned wafer layers, and products of same
US20050184362A1 (en) * 2004-01-26 2005-08-25 Harumitsu Fujita Semiconductor substrate
US20060093963A1 (en) * 2004-11-02 2006-05-04 Fujitsu Limited Manufacturing method of semiconductor device
US20070023915A1 (en) * 2005-07-29 2007-02-01 Jui-Meng Jao On-chip test circuit for assessing chip integrity
US7667842B2 (en) * 2005-09-30 2010-02-23 GlobalFoundries, Inc. Structure and method for simultaneously determining an overlay accuracy and pattern placement error
US20070133861A1 (en) * 2005-12-09 2007-06-14 Byung-Hun Do Apparatus and method for inspecting overlay patterns in semiconductor device
US7998826B2 (en) * 2007-09-07 2011-08-16 Macronix International Co., Ltd. Method of forming mark in IC-fabricating process
US20090312981A1 (en) * 2008-06-13 2009-12-17 Elpida Memory, Inc. Alignment mark and alignment method using the alignment mark
US20100092882A1 (en) * 2008-10-14 2010-04-15 Canon Kabushiki Kaisha Exposure apparatus and device fabrication method
US20100123887A1 (en) * 2008-11-17 2010-05-20 Asml Netherlands B.V. Method for a lithographic apparatus
US20110248387A1 (en) * 2010-04-13 2011-10-13 Renesas Electronics Corporation Semiconductor integrated circuit and pattern layouting method for the same
US20130234019A1 (en) * 2010-11-24 2013-09-12 Atsushi Miyamoto Global alignment using multiple alignment pattern candidates
US20120322169A1 (en) * 2011-06-16 2012-12-20 Renesas Electronics Corporation Method of manufacturing semiconductor device
US20130075938A1 (en) * 2011-09-23 2013-03-28 Semiconductor Manufacturing International (Beijing) Corporation Photolithography alignment mark, mask and semiconductor wafer containing the same mark
US20130147066A1 (en) * 2011-12-08 2013-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for e-beam in-chip overlay mark
US9230867B2 (en) * 2011-12-08 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for E-beam in-chip overlay mark
US20150186581A1 (en) * 2013-12-30 2015-07-02 Asml Netherlands B.V. Method and apparatus for design of a metrology target
US20150332452A1 (en) * 2014-05-14 2015-11-19 Nuflare Technology, Inc. Inspection method, template substrate, and focus offset method
US20160179017A1 (en) * 2014-06-21 2016-06-23 Kla-Tencor Corporation Compound imaging metrology targets
US20160266505A1 (en) * 2015-01-30 2016-09-15 Kla-Tencor Corporation Device metrology targets and methods
US9470987B1 (en) * 2015-10-22 2016-10-18 United Microelectronics Corp. Overlay mask
US20170329217A1 (en) * 2016-05-10 2017-11-16 Canon Kabushiki Kaisha Position detector, position detection method, imprint apparatus, and product manufacturing method
US20190310554A1 (en) * 2016-12-16 2019-10-10 Asml Netherlands B.V. Method and apparatus for image analysis
US10079185B1 (en) * 2017-06-23 2018-09-18 United Microelectronics Corp. Semiconductor pattern for monitoring overlay and critical dimension at post-etching stage and metrology method of the same

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