US20160372411A1 - Semiconductor package and method of manufacturing the same - Google Patents

Semiconductor package and method of manufacturing the same Download PDF

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Publication number
US20160372411A1
US20160372411A1 US15/079,074 US201615079074A US2016372411A1 US 20160372411 A1 US20160372411 A1 US 20160372411A1 US 201615079074 A US201615079074 A US 201615079074A US 2016372411 A1 US2016372411 A1 US 2016372411A1
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United States
Prior art keywords
cavity
cavity mold
substrate
electronic component
semiconductor package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US15/079,074
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English (en)
Inventor
Yong-Ho Baek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electro Mechanics Co Ltd
Original Assignee
Samsung Electro Mechanics Co Ltd
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Filing date
Publication date
Application filed by Samsung Electro Mechanics Co Ltd filed Critical Samsung Electro Mechanics Co Ltd
Assigned to SAMSUNG ELECTRO-MECHANICS CO., LTD. reassignment SAMSUNG ELECTRO-MECHANICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: BAEK, YONG-HO
Publication of US20160372411A1 publication Critical patent/US20160372411A1/en
Priority to US16/272,484 priority Critical patent/US10699982B2/en
Abandoned legal-status Critical Current

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Definitions

  • the following description relates to a semiconductor package and a method of manufacturing a semiconductor package.
  • SIP system in package
  • CSP chip sized package
  • FCP flip chip package
  • the package board is required to have a fine pitch, thereby increasing the manufacturing cost of the package board.
  • an interposer has been conventionally formed between the electronic component and the package board.
  • a package board and a method of manufacturing a package board having a high-conformity, high-density circuit layer are provided.
  • a semiconductor package including a first substrate including a first cavity, a cavity mold configured to be inserted into the first cavity and including a second cavity, an electronic component inserted in the second cavity, and a second substrate formed on a surface of the first substrate, a surface of the cavity mold and a surface of the electronic component.
  • a plurality of electronic components may be disposed above the second substrate.
  • the cavity mold may include a plurality of first cavities configured to receive the plurality of electronic components.
  • the cavity mold may be made of an insulating material.
  • the cavity mold may be made of a prepreg.
  • the cavity mold may be made at least one of a prepreg, a metal, or a ceramic.
  • Another surface of the cavity mold and another surface of the electronic component may be placed on a same plane.
  • the second substrate includes an insulating layer and a circuit layer, and the insulating layer may be made of a photosensitive insulating material.
  • the first substrate includes an insulating layer and a circuit layer.
  • the cavity mold may be configured to prevent the insulating layer from flowing into the electronic component.
  • a surface of the cavity mold in which the electronic component may be inserted is flat.
  • a method of manufacturing a semiconductor package including including preparing a first substrate including a first cavity formed, preparing a cavity mold including a second cavity, inserting an electronic component in the second cavity, inserting the cavity mold in the first cavity, and forming a second substrate on a surface of the first substrate, a surface of the cavity mold, and a surface of the electronic component.
  • the cavity mold may be made of an insulating material.
  • the cavity mold may be made of a prepreg.
  • the cavity mold may be made of a metal or a ceramic.
  • the second cavity may include a plurality of cavities formed thereon.
  • the inserting of the electronic component may include inserting a plurality of electronic components in the plurality of second cavities.
  • Another surface of the cavity mold and another surface of the electronic component may be placed on a same plane.
  • the second substrate may include an insulating layer and a circuit layer, and the insulating layer may be made of a photosensitive insulating material.
  • FIG. 1 is a diagram illustrating an example of a semiconductor package.
  • FIG. 2 is a diagram illustrating an example of a semiconductor package.
  • FIG. 3 is a diagram illustrating an example of a method of forming the package board.
  • FIG. 4 through FIG. 12 are diagrams illustrating examples of a method of forming the semiconductor package.
  • FIG. 1 illustrates an example of a semiconductor package in accordance with a first embodiment.
  • a semiconductor package 100 includes a first substrate 110 , a cavity mold 120 , an electronic component 130 and a second substrate 140 .
  • the first substrate 110 includes at least one layer of first insulating layer 111 and first circuit layer 112 .
  • the first insulating layer 111 is made of a composite polymer resin that is commonly used for an interlayer insulating material.
  • the first insulating layer 111 is made of an epoxy resin, such as, for example, a prepreg, an ajinomoto build-up film (ABF), flame retardant 4 (FR-4), or bismaleimide triazine (BT).
  • ABS ajinomoto build-up film
  • FR-4 flame retardant 4
  • BT bismaleimide triazine
  • the first circuit layer 112 is made of a conductive material.
  • the first circuit layer 112 is made of copper.
  • the material for the first circuit layer 112 is not limited to copper only, and it is possible that the first circuit layer 112 is made of any circuit-forming conductive material known in the field of circuit board.
  • a first cavity 115 is formed in the first substrate 110 .
  • the first cavity 115 is formed on one surface of the first substrate 110 .
  • the surface of the first substrate 110 on which the first cavity 115 is formed is in contact with or electrically connected with the second substrate 140 .
  • a size and a shape of the first cavity 115 is such that it is adequate for the cavity mold 120 to be fixed to the first substrate 110 when the cavity mold 120 is inserted in the first cavity 115 .
  • the cavity mold 120 is inserted into and fixed to the first cavity 115 of the first substrate 110 .
  • a second cavity 125 is formed in the cavity mold 120 .
  • the second cavity 125 is formed on one surface of the cavity mold 120 .
  • the surface of the cavity mold 120 on which the second cavity 120 is formed is in contact with the second substrate 140 .
  • a size and a shape of the second cavity 125 is such that it is adequate for the electronic component 130 to be fixed to the cavity mold 120 when the electronic component 130 is inserted in the second cavity 125 .
  • the cavity mold 120 is made of an insulating material.
  • the cavity mold 120 is made of a prepreg.
  • the cavity mold 120 is made of a metal or a ceramic.
  • a heat generated by the electronic component 130 may be transferred outside. Accordingly, a heat dissipating property of the semiconductor package 100 may be improved by forming the cavity mold 120 with metal or ceramic.
  • the cavity mold 120 protects the electronic component 130 when the cavity mold 120 is inserted in the first substrate 110 or when the second substrate 140 is formed.
  • the cavity mold 120 functions as a protective wall such that the first insulating layer 111 of the first substrate 110 does not flow to the electronic component 130 . Since the cavity mold 120 prevents the first insulating layer 111 from flowing, it is possible to form the semiconductor package 100 to be designed precisely.
  • the electronic component 130 is inserted in the second cavity 125 of the cavity mold 120 .
  • the electronic component 130 remains inserted in the cavity mold 120 when the electronic component 130 is arranged above the second substrate 140 .
  • the electronic component 10 may be any kind of component that can be installed in the semiconductor package 100 .
  • the cavity mold 120 and the electronic component 130 may be aligned in such a way that one surface of the cavity mold 120 and one surface of the electronic component 130 are on a same plane.
  • the cavity mold 120 Since the cavity mold 120 is inserted in and fixed to the first cavity 115 of the first substrate 110 , the electronic component 130 is prevented from being tilted. Accordingly, the electronic component 130 is affixed at its intended position. Therefore, it is possible to have a high conformity among the first substrate 110 , the electronic component 130 , and the second substrate 140 .
  • the second substrate 140 includes at least one layer of second insulating layer 141 and second circuit layer 142 .
  • the second insulating layer 141 is made of a photosensitive material, among interlayer insulating materials commonly used in the field of circuit board.
  • the second circuit layer 142 is made of a conductive material.
  • the second circuit layer 142 is made of copper.
  • the material for the second circuit layer 142 is not limited to copper, and it is possible that the second circuit layer 142 is made of any circuit-forming conductive material known in the field of circuit board.
  • the second substrate 140 since the second substrate 140 has a circuit layer formed on a photosensitive insulating material, it is possible to realize a fine pitch in the second circuit layer 142 . Accordingly, it is possible to omit an additional redistribution layer and interposer.
  • FIG. 2 illustrates another example of a semiconductor package.
  • a semiconductor package 200 in includes a first substrate 110 , a cavity mold 220 , an electronic component 130 and a second substrate 140 .
  • the first substrate 110 and the second substrate 140 shown in FIG. 2 are similar to the first substrate 110 (shown in FIG. 1 ) and the second substrate 140 (shown in FIG. 1 ).
  • the above description of FIG. 1 is also applicable to FIG. 2 , and is incorporated herein by reference. Thus, the above description may not be repeated here.
  • the cavity mold 220 and the electronic component 130 as shown in FIG. 2 are similar to the cavity mold 120 (shown in FIG. 1 ) and the electronic component 130 (shown in FIG. 1 ).
  • the above description of FIG. 1 is also applicable to FIG. 2 , and is incorporated herein by reference. Thus, the above description may not be repeated here. But, some differences between the cavity mold 220 and the electronic component 130 of FIG. 2 and the cavity mold 120 and the electronic component 130 of FIG. 1 will be described herein.
  • a plurality of second cavities 225 are formed in the cavity mold 220 .
  • a plurality of electronic components 130 are provided in the plurality of second cavities 225 .
  • the second cavities 225 are each formed to have a size and a shape that is sufficient for the electronic component 130 to be inserted into and fixed to the second cavity 225 .
  • the plurality of electronic components 130 are each inserted into and fixed to the corresponding second cavity 225 . Accordingly, one surfaces of the plurality of electronic components 130 and one surface of the cavity mold 220 may be aligned on a same plane. The plurality of electronic components 130 may be prevented from being tilted. Accordingly, it is possible to have a high conformity among the first substrate 110 , the plurality of electronic components 130 and the second substrate 140 .
  • the cavity mold 220 having the plurality of electronic components 130 inserted therein, is inserted in a first cavity 115 of the first substrate 110 .
  • the second substrate 140 is placed below the first substrate 110 , the cavity mold 220 , and the plurality of electronic components 130 .
  • FIG. 3 is a diagram illustrating an example of a method of forming the package board.
  • FIG. 4 through FIG. 12 illustrate examples of a method of forming the semiconductor package. The method shown in FIG. 3 will be described with reference to FIG. 4 through FIG. 12 .
  • the operations in FIG. 3 may be performed in the sequence and manner as shown, although the order of some operations may be changed or some of the operations omitted without departing from the spirit and scope of the illustrative examples described. Many of the operations shown in FIG. 3 may be performed in parallel or concurrently.
  • FIGS. 1-2 is also applicable to FIG. 3 , and is incorporated herein by reference. Thus, the above description may not be repeated here.
  • a first substrate 110 having a first cavity 115 formed therein is prepared.
  • the first substrate 110 includes at least one layer of first insulating layer 111 and first circuit layer 112 .
  • the first insulating layer 111 is made of a composite polymer resin that is commonly used for an interlayer insulating material.
  • the first insulating layer 111 is made of an epoxy resin, for example, a prepreg, an ajinomoto build-up film (ABF), flame retardant 4 (FR-4), or bismaleimide triazine (BT).
  • ABS ajinomoto build-up film
  • FR-4 flame retardant 4
  • BT bismaleimide triazine
  • the first circuit layer 112 is made of a conductive material.
  • the first circuit layer 112 is made of copper.
  • the material for the first circuit layer 112 is not limited to copper only, and it is possible that the first circuit layer 112 is made of any circuit-forming conductive material known in the field of circuit board.
  • the first cavity 115 is formed in the first substrate 110 .
  • the first cavity 115 is formed on one surface of the first substrate 110 .
  • the surface of the first substrate 110 on which the first cavity 115 is formed is in contact with or electrically connected with a second substrate 140 .
  • the first cavity 115 has a size and a shape that is adequate for a cavity mold 120 to be fixed to the first substrate 110 when the cavity mold 120 is inserted in the first cavity 115 .
  • the first substrate 110 may be formed using any method of forming an insulating layer, a circuit layer and a cavity that is known in the field of circuit board.
  • the cavity mold 120 having a second cavity 125 formed therein is prepared.
  • FIG. 5 illustrates an example of the cavity mold 120 in accordance with the example disclosed in FIG. 1
  • FIG. 6 illustrates an example of the cavity mold 120 in accordance with the example disclosed in FIG. 2 .
  • the cavity mold 120 as shown in FIGS. 5 and 6 are made of an insulating material.
  • the cavity mold 120 is made of a prepreg.
  • the cavity mold 120 is made of metal or ceramic.
  • heat generated by an electronic component (not shown), which is to be inserted later, may be transferred outside the electronic component. Accordingly, a heat dissipating property of a semiconductor package may be improved by forming the cavity mold 120 with metal or ceramic.
  • the cavity mold 120 may have the second cavity 125 , as shown in FIG. 5 .
  • the cavity mold 220 may have the second cavity 225 , as shown in FIG. 6 .
  • the second cavity 125 and 225 may be formed on one surface of the cavity mold 120 and 220 , respectively.
  • the cavity mold 120 has one second cavity 125 formed therein.
  • the second cavity 125 is formed to have a size and a shape sufficient for one electronic component (not shown), which is to be inserted in and fixed to the second cavity 125 .
  • a cavity mold 220 in accordance with the second embodiment has a plurality of second cavities 225 formed therein.
  • an electronic component 130 is inserted in the second cavity 125 , 225 of the cavity mold 120 , 220 , respectively.
  • the electronic component 130 is inserted in the cavity mold 120 . As shown in FIG. 7 , a single electronic component 130 is inserted into the second cavity 125 of the cavity mold 120 . Since the second cavity 125 has the same size and shape as those of the electronic component 130 , the electronic component 130 is fixed in the cavity mold 120 .
  • the one surface of the cavity mold 120 and one surface of the electronic component 130 are placed on a same plane. Accordingly, the one surface of the cavity mold 120 in which the electronic component 130 is inserted is flat.
  • a plurality of electronic components 130 are inserted in the cavity mold 220 .
  • 3 electronic components 130 are inserted into the three second cavities 225 of the cavity mold 220 .
  • the 3 electronic components 130 are fixed in the cavity mold 220 .
  • the one surface of the cavity mold 220 and one surfaces of the plurality of electronic components 130 are placed on a same plane. Accordingly, the one surface of the cavity mold 220 in which the plurality of electronic components 130 are inserted is flat.
  • the electronic component 130 Since the electronic component 130 is inserted in and fixed to the cavity mold 120 and 220 , the electronic component 130 is prevented from being tilted. Accordingly, the electronic component 130 is prevented from slipping out or escaping when the electronic component 130 is to be arranged.
  • the cavity mold 120 , 220 in which the electronic component 130 is inserted is inserted in the first cavity 115 of the first substrate 110 .
  • the cavity mold 120 is inserted in the first cavity 115 of the first substrate 110 .
  • the cavity mold 120 is fixed when it is inserted in the first substrate 110 .
  • one surface of the first substrate 110 and one surface of the cavity mold 120 and 220 are placed on a same plane. Accordingly, one surface of the first substrate 110 in which the cavity mold 120 and 220 is inserted is flat.
  • the cavity mold 120 and 220 prevents the first insulating layer 111 from flowing toward the electronic component 130 . Since the cavity mold 120 and 220 prevents the first insulating layer 111 from flowing, it is possible to form and dispose the first substrate 110 , the cavity mold 120 and 220 , the electronic component 130 , and the second substrate (not shown), which is to be formed later, precisely as designed.
  • the second substrate 140 is formed on the first substrate 110 in which the cavity mold 120 and 220 is inserted.
  • the second substrate 140 is formed on a surface of the first substrate 110 , a surface of the cavity mold 120 and 220 and a surface of the electronic component 130 .
  • the second substrate 140 includes at least one layer of second insulating layer 141 and second circuit layer 142 .
  • the second insulating layer 141 is made of a photosensitive material from interlayer insulating materials commonly used in the field of circuit board.
  • the second circuit layer 142 is made of a conductive material such as, for example, copper.
  • the material for the second circuit layer 142 is not limited to copper only, and the second circuit layer 142 may be made of any circuit-forming conductive material known in the field of circuit board.
  • one surface of the first substrate 110 , one surface of the cavity mold 120 and 220 and one surface of the electronic component 130 are placed on a same plane.
  • the first substrate 110 , the cavity mold 120 and 220 and the electronic component 130 have one common flat surface.
  • the second substrate 140 is formed on this common flat surface.
  • the second substrate 140 is formed with the electronic component 130 remaining fixed to the cavity mold 120 and 220 . Accordingly, it is possible to have a high conformity between the second substrate 140 and the electronic component 130 and between the second substrate 140 and the first substrate 110 .
  • the second substrate 140 includes the second insulating layer 141 made of a photosensitive material, it is possible to realize the second substrate 140 with a fine pitch.
  • the second substrate 140 may serve as a redistribution layer or an interposer.
  • the semiconductor package 100 and 200 may omit the redistribution layer or the interposer.
  • the redistribution layer or the interposer may be omitted, it is possible to reduce a thickness of the semiconductor package 100 and 200 .

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CN106257654B (zh) 2021-05-04
US10699982B2 (en) 2020-06-30

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