US20160359005A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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US20160359005A1
US20160359005A1 US15/077,932 US201615077932A US2016359005A1 US 20160359005 A1 US20160359005 A1 US 20160359005A1 US 201615077932 A US201615077932 A US 201615077932A US 2016359005 A1 US2016359005 A1 US 2016359005A1
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layer
films
semiconductor device
base
doped
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Ming-Shien Hu
Chien-Jen Sun
I-Ching Li
Wen-Ching Hsu
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GlobalWafers Co Ltd
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GlobalWafers Co Ltd
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Assigned to GLOBALWAFERS CO., LTD. reassignment GLOBALWAFERS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HSU, WEN-CHING, LI, I-CHING, SUN, CHIEN-JEN, HU, MING-SHIEN
Publication of US20160359005A1 publication Critical patent/US20160359005A1/en
Priority to US17/027,712 priority Critical patent/US11923422B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/15—Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices
    • H01L29/157—Doping structures, e.g. doping superlattices, nipi superlattices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H01L29/365—Planar doping, e.g. atomic-plane doping, delta-doping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Definitions

  • the disclosure relates to a semiconductor device. More particularly, the disclosure relates to a semiconductor device with a superlattice stack.
  • Nitride semiconductors are characterized by high electron saturation velocity and wide band gap and thus can be applied not only to light emitting semiconductor devices but also to compound semiconductor devices with high breakdown voltage and large power output.
  • GaN gallium nitride
  • AlGaN aluminum gallium nitride
  • the GaN layer serves as an electron transport layer
  • the AlGaN layer acts as an electron supply layer. Since the lattice constant of AlGaN is different from that of GaN, strain may be generated in the AlGaN layer. Due to piezoelectric polarization, two-dimensional electronic gas (2DEG) with high concentration is generated.
  • 2DEG two-dimensional electronic gas
  • a semiconductor device that includes a substrate, an initial layer located on the substrate, and a superlattice stack located on the initial layer.
  • the initial layer includes aluminum nitride (AlN), and the superlattice stack includes a plurality of first films and a plurality of second films.
  • the first films and the second films are alternately stacked on the initial layer.
  • At least one of the first films and the second films is a doped layer having dopants selected from a group consisting of carbon, iron, and the combination thereof, and the other films do not comprise dopants substantially.
  • a semiconductor device that includes a substrate, an initial layer located on the substrate, and a superlattice stack located on the initial layer.
  • the initial layer includes aluminum nitride (AlN), and the superlattice stack includes a plurality of first films, a plurality of second films, and at least one doped layer.
  • the first films and the second films are alternately stacked on the initial layer.
  • the at least one doped layer is arranged in one of the first films and the second films, and dopants of the at least one doped layer are selected from a group consisting of carbon, iron, and the combination thereof.
  • dopants are implanted into at least one film in the superlattice stack, so as to form the doped layer.
  • conductivity of the superlattice stack can be reduced (i.e., the degree of insulation of the superlattice stack can be enhanced), and the breakdown voltage of the semiconductor device can be raised effectively.
  • the films with the dopants have unfavorable crystallinity and roughness.
  • the films having no dopants are grown in an epitaxial manner above the film layers with the dopants in the semiconductor device. Since the films having no dopants can have satisfactory crystallinity and roughness, crystallinity and roughness of the epitaxy layer can also be recovered.
  • the films having no dopants are grown in an epitaxial manner above the doped layer with dopants and unfavorable crystallinity and roughness, so as to recover and enhance crystallinity and roughness of the epitaxy layer; thereafter, another doped layer with the dopant is grown in an epitaxial manner.
  • the films (having no dopant) and the doped layers (having dopants) are alternately grown in an epitaxial manner according to the disclosure, such that the breakdown voltage of the semiconductor device can be raised (due to the arrangement of the films with the dopants), and that the resultant semiconductor device can have favorable crystallinity and roughness (due to the arrangement of the films having no dopant).
  • the dopants are implanted into the films of the superlattice stack of the semiconductor device, which results in the issue of bowing of the entire semiconductor device. Accordingly, wafers applied for making the semiconductor device may be cracked.
  • the films with no dopant are inserted between the doped layers having the dopants, so as to prevent the superlattice stack from being completely composed of the doped layers with the dopants. Thereby, the issue of bowing of the entire semiconductor device can be resolved to a greater extent.
  • the concentration of gallium (Ga) in the superlattice stack also leads to the issue of the bowing of the entire semiconductor device.
  • the increase in the concentration of aluminum (Al) i.e., the decrease in the concentration of Ga
  • the films having Al with high concentration can be inserted between the films having Ga with high concentration, so as to resolve the issue of bowing caused by the gallium in the films and further resolve the issue of bowing of the entire semiconductor device to a greater extent.
  • the first and second films in the superlattice stack are alternately grown in an epitaxial manner, such that the breakdown voltage of the semiconductor device can be raised, and that the issue of the bowing of the entire semiconductor device can be resolved.
  • the wafers for manufacturing the semiconductor device are neither cracked nor broken due to the issue of bowing.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the disclosure.
  • FIG. 2 is a schematic cross-sectional view of a superlattice stack according to an embodiment of the disclosure.
  • FIG. 3 schematically illustrates variations in concentrations of dopants in a semiconductor device according to an embodiment of the disclosure.
  • FIG. 4 is a schematic cross-sectional view of a superlattice stack according to an embodiment of the disclosure.
  • FIG. 5 is a schematic cross-sectional view of a superlattice stack according to an embodiment of the disclosure.
  • FIG. 6 is a schematic cross-sectional view of a superlattice stack according to an embodiment of the disclosure.
  • FIG. 7 is a schematic cross-sectional view of a superlattice stack according to an embodiment of the disclosure.
  • FIG. 8 is a schematic cross-sectional view of a buffer stack according to an embodiment of the disclosure.
  • FIG. 9 is a schematic cross-sectional view of a buffer stack according to an embodiment of the disclosure.
  • FIG. 10 is a schematic cross-sectional view of a buffer stack according to an embodiment of the disclosure.
  • FIG. 1 is a schematic cross-sectional view of a semiconductor device 10 according to an embodiment of the disclosure.
  • the semiconductor device 10 includes a substrate 11 , an initial layer 13 arranged on the substrate 11 , and a superlattice stack 100 arranged on the initial layer 13 .
  • the semiconductor device 10 further includes a buffer stack 200 , an electron transport layer 31 , and an electron supply layer 33 .
  • the buffer stack 200 is located between the initial layer 13 and the superlattice stack 100 , and the electron transport layer 31 and the electron supply layer 33 are arranged on the superlattice stack 100 .
  • the substrate 11 is a silicon substrate or a substrate having a silicon surface, such as Si(111), Si(100), Si(110), a textured Si surface, silicon on insulation (SOI), silicon on sapphire (SOS), and a silicon wafer bonded to other materials (AlN, diamond, or any other polycrystalline material).
  • a substrate that can be applied to replace the Si substrate includes a SiC substrate, a sapphire substrate, a GaN substrate, and a gallium arsenide (GaAs) substrate.
  • the substrate 11 may be a half-insulating substrate or a conductive substrate.
  • the initial layer 13 is arranged on the substrate 11 , and the initial layer 13 includes AlN.
  • the initial layer 13 is grown on the Si substrate having an upper surface of (111) plane in an epitaxial manner, and the thickness of the initial layer 13 is about 200 nm.
  • a mixture having trimethyl amine (TMA) and ammonia (NH 3 ) is applied as a reactive gas to form the initial layer 13 on the Si substrate.
  • a concentration of carbon in the initial layer 13 is substantially lower than 1E16/cm 3 .
  • 2DEG is generated around the boundary between the electron transport layer 31 and the electron supply layer 33 .
  • 2DEG is generated in the semiconductor device 10 due to spontaneous polarization and piezoelectric polarization, which results from the fact that the compound semiconductor (GaN) of the electron transport layer 31 and the compound semiconductor (AlGaN) of the electron supply layer 33 are made of hetero materials.
  • FIG. 2 is a schematic cross-sectional view of a superlattice stack 100 A according to an embodiment of the disclosure.
  • the superlattice stack 100 A may act as the superlattice stack 100 shown in FIG. 1 .
  • the superlattice stack 100 A includes a plurality of first films 121 and a plurality of second films 123 .
  • the first films 121 and the second films 123 are alternately stacked on the buffer stack 200 .
  • the first films 121 are doped layers having dopants selected from a group consisting of carbon, iron and the combination thereof, and the second films 123 do not include dopants (carbon or iron) substantially.
  • the first films 121 include Al x Ga 1-x N
  • the second films 123 include Al y Ga 1-y N
  • the concentrations of Al in the first films 121 are different from the concentrations of Al in the second films 123 (i.e., X is not equal to Y).
  • X and Y are between 0 and 1 and are neither equal to 0 nor equal to 1.
  • the first films 121 include AlN
  • the second films 123 include Al y Ga 1-y N, i.e., X is equal to 1, and Y is between 0 and 0.35 and is neither equal to 0 nor equal to 0.35.
  • the first films 121 include AlN
  • the second films 123 include GaN, i.e., X is equal to 1, and Y is equal to 0.
  • FIG. 3 schematically illustrates variations in concentrations of dopants in a superlattice stack according to an embodiment of the disclosure.
  • a concentration of the dopants in the superlattice stack 100 A varies in a non-continuous manner, e.g., in a ⁇ -like manner, as shown in FIG. 3 .
  • the concentration of dopants in two doped layers in the superlattice stack 100 A may remain unchanged substantially (as shown in FIG. 3 ), gradually increase, or gradually decrease.
  • the concentrations of dopants in the first films 121 are higher than concentrations of dopants in other regions (e.g., the second films 123 ).
  • the concentrations of the dopants increase from the second films 123 to the first films 121 and decrease from the first films 121 to the second films 123 .
  • the concentrations of the dopants in the first films 121 is between 1E17/cm 3 and 1E20/cm 3
  • the concentrations of dopants in regions other than the first films 121 is lower than 1E17/cm 3 .
  • dopants are implanted into at least one film in the superlattice stack 100 A, so as to form the doped layer.
  • conductivity of the superlattice stack 100 A can be reduced (i.e., the degree of insulation of the superlattice stack 100 A can be enhanced), and the breakdown voltage of the semiconductor device can be raised effectively.
  • the doped layers (i.e., the first films 121 ) with the dopants have unfavorable crystallinity and roughness.
  • the second films 123 having no dopants are grown in an epitaxial manner above the doped layers 121 (the first films 121 ) with the dopants. Since the second films 123 have no dopants, the crystallinity and roughness of the second films 123 are relatively satisfactory; thereby, crystallinity and roughness of the epitaxy layer can be recovered.
  • the second films 123 having no dopants are grown in an epitaxial manner above the doped layers (the first films 121 with dopants and unfavorable crystallinity and roughness), so as to recover and enhance crystallinity and roughness of the epitaxy layer; thereafter, another doped layer (the first film 121 ) with the dopant is grown in an epitaxial manner.
  • the second films 123 (having no dopant) and the first films 121 (having dopants) are alternately grown in an epitaxial manner according to the disclosure, such that the breakdown voltage of the semiconductor device can be raised (due to the arrangement of the first films 121 with the dopants), and that the resultant semiconductor device can have favorable crystallinity and roughness (due to the arrangement of the second films 123 having no dopant).
  • the dopants are implanted into the films of the superlattice stack 100 A of the semiconductor device, which results in the issue of bowing of the entire semiconductor device. Accordingly, wafers applied for making the semiconductor device may be cracked.
  • the second films 123 with no dopants are inserted between the doped layers (the first films 121 ) having the dopants , so as to prevent the superlattice stack 100 A from being completely composed of the doped layers (the first films 121 ) with the dopants.
  • the concentration of Ga in the superlattice stack 100 A also leads to the issue of the bowing of the entire semiconductor device.
  • the increase in the concentration of Al i.e., the decrease in the concentration of Ga
  • the films having Al with high concentration can be inserted between the films having Ga with high concentration, so as to resolve the issue of bowing caused by the gallium in the films and further resolve the issue of bowing of the entire semiconductor device to a greater extent.
  • the first and second films 121 and 123 in the superlattice stack 100 A of the semiconductor device are alternately grown in an epitaxial manner, such that the breakdown voltage of the semiconductor device can be raised, and that the issue of the bowing of the entire semiconductor device can be resolved.
  • the wafers for manufacturing the semiconductor device are neither cracked nor broken due to the issue of bowing.
  • FIG. 4 is a schematic cross-sectional view of a superlattice stack 100 B according to an embodiment of the disclosure.
  • the superlattice stack 100 B may act as the superlattice stack 100 shown in FIG. 1 .
  • the same technical contents in the embodiment shown in FIG. 4 and in the superlattice stack 100 A shown in FIG. 2 will not be further explained hereinafter.
  • the superlattice stack 100 B includes a plurality of first films 131 and a plurality of second films 133 .
  • the first films 131 and the second films 133 are alternately stacked on the buffer stack 200 .
  • the second films 133 are doped layers having dopants selected from a group consisting of carbon, iron and the combination thereof, and the first films 131 do not include dopants (carbon or iron) substantially.
  • FIG. 2 which shows that the dopants are implanted into the first films 121 of the superlattice stack 100 A
  • FIG. 4 shows that the dopants are implanted into the second films 133 of the superlattice stack 100 B.
  • FIG. 5 is a schematic cross-sectional view of a superlattice stack 100 C according to an embodiment of the disclosure.
  • the superlattice stack 100 C may act as the superlattice stack 100 shown in FIG. 1 .
  • the same technical contents in the embodiment shown in FIG. 5 and in the superlattice stack 100 A shown in FIG. 2 will not be further explained hereinafter.
  • the superlattice stack 100 C includes a plurality of first films 141 , a plurality of second films 143 , and at least one doped layer 145 .
  • the first films 141 and the second films 143 are alternately stacked on the buffer stack 200 .
  • the doped layer 145 is located in the second films 143 , and dopants in the doped layer 145 are selected from a group consisting of carbon, iron and the combination thereof.
  • the first films 141 do not include dopants (carbon or iron) substantially.
  • FIG. 5 shows that the dopants are implanted into some regions of the second films 143 of the superlattice stack 100 C, so as to form the doped layer 145 .
  • FIG. 6 is a schematic cross-sectional view of a superlattice stack 100 D according to an embodiment of the disclosure.
  • the superlattice stack 100 D may act as the superlattice stack 100 shown in FIG. 1 .
  • the same technical contents in the embodiment shown in FIG. 6 and in the superlattice stack 100 A shown in FIG. 2 will not be further explained hereinafter.
  • the superlattice stack 100 D includes a plurality of first films 151 , a plurality of second films 153 , and at least one doped layer 155 .
  • the first films 151 and the second films 153 are alternately stacked on the buffer stack 200 .
  • the doped layer 155 is located in the first films 151 , and dopants in the doped layer 155 are selected from a group consisting of carbon, iron and the combination thereof
  • the second films 153 do not include dopants (carbon or iron) substantially.
  • FIG. 6 shows that the dopants are implanted into some regions of the first films 151 of the superlattice stack 100 D, so as to form the doped layer 155 .
  • FIG. 7 is a schematic cross-sectional view of a superlattice stack 100 E according to an embodiment of the disclosure.
  • the superlattice stack 100 E may act as the superlattice stack 100 shown in FIG. 1 .
  • the same technical contents in the embodiment shown in FIG. 7 and in the superlattice stack 100 A shown in FIG. 2 will not be further explained hereinafter.
  • the superlattice stack 100 E includes a plurality of first films 161 , a plurality of second films 163 , and at least one doped layer 165 .
  • the first films 161 and the second films 163 are alternately stacked on the buffer stack 200 .
  • the doped layer 165 is located in the first films 161 and the second films 163 , and dopants in the doped layer 165 are selected from a group consisting of carbon, iron and the combination thereof Compared to FIG. 5 (which shows that a doped layer is formed in the second films of the superlattice stack 100 C) and FIG. 6 (which shows that a doped layer is formed in the first films of the superlattice stack 100 D), FIG. 7 shows that at least one doped layer 165 is formed in both of the first and second film layers 161 and 163 of the superlattice stack 100 E.
  • FIG. 8 is a schematic cross-sectional view of a buffer stack 200 A according to an embodiment of the disclosure.
  • the buffer stack 200 A may act as the buffer stack 200 shown in FIG. 1 .
  • the buffer stack 200 A includes at least one doped layer 23 positioned between two adjacent base layers 21 .
  • the buffer stack 200 A includes a plurality of base layers 21 and a plurality of doped layers 23 , and the doped layers 23 and the base layers 21 are alternately stacked on the initial layer 13 .
  • the base layers 21 include AlGaN
  • the doped layers 23 include AlGaN or BAlGaN.
  • Dopants in the doped layers 23 include carbon or iron, and the base layers 21 do not contain dopants (carbon or iron) substantially.
  • the doped layers 23 may be C—AlGaN, C—BAlGaN, Fe—AlGaN, or Fe—BAlGaN.
  • a thickness of the doped layer 23 is between 10 angstroms and 1 micrometer, and a ratio of the thickness of the doped layer 23 to a thickness of each base layer 21 is between 0.001 and 1.0.
  • a concentration of the dopants in the doped layer 23 is between 1E17/cm 3 and 1E20/cm 3 , and a concentration of dopants in each base layer 21 is lower than 1E17/cm 3 .
  • the buffer stack 200 A includes four base layers 21 .
  • Concentrations of Al in the base layers 21 from bottom to top are x1, x2, x3, and x4, respectively, concentrations of Ga in the base layers 21 from bottom to top are 1-x 1 , 1-x2, 1-x3, and 1-x4, respectively, and x1>x2>x3>x4. That is, the concentrations of Al in the base layers 21 of the buffer stack 200 A gradually decrease from bottom to top, and the concentrations of Ga in the base layers 21 gradually increase from bottom to top.
  • concentrations of Al in the doped layers 23 are y1, y2, and y3 from bottom to top.
  • Thicknesses of the three doped layers 23 from bottom to top are dc1, dc2, and dc3, respectively,
  • the base layer 21 (having no dopants) at the bottom of the buffer stack 200 A is in contact with the initial layer 13
  • the base layer 21 (having no dopants) at the top of the buffer stack 200 A is in contact with the electron transport layer 31 . That is, the doped layers 23 having the dopants in the buffer stack 200 A of the semiconductor device are neither in contact with the initial layer 13 nor in contact with the electron transport layer 31 .
  • a concentration of the dopants in the buffer stack 200 A varies in a non-continuous manner, e.g., in a ⁇ -like manner, as shown in FIG. 3 .
  • the concentration of dopants in three doped layers 23 in the buffer stack 200 A may remain unchanged substantially (as shown in FIG. 3 ), gradually increase, or gradually decrease.
  • the concentration of dopants in the doped layer 23 is higher than a concentration of dopant in regions other than the doped layer 23 , i.e., the concentration of the dopants increases from the base layer 21 to the doped layer 23 and decreases from the doped layer 23 to the base layer 21 .
  • the doped layer 23 with the dopants is inserted into the buffer stack 200 A of the semiconductor device, so as to reduce the conductivity of the buffer stack 200 A (i.e., enhance the degree of insulation of the buffer stack 200 A) and further raise the breakdown voltage of the semiconductor device effectively.
  • the doped layer 23 with the dopants has unfavorable crystallinity and roughness.
  • the base layers 21 having no dopants are grown in an epitaxial mariner above the doped layer 23 with the dopants in the semiconductor device, so as to recover crystallinity and roughness of the epitaxy layer (the base layers 21 have no dopants and thus can have satisfactory crystallinity and roughness). More specifically, the base layers 21 having no dopants are grown in an epitaxial manner above the doped layer 23 with dopants and unfavorable crystallinity and roughness, so as to recover and enhance crystallinity and roughness of the epitaxy layer; thereafter, another doped layer 23 with the dopant is grown in an epitaxial manner.
  • the base layers 21 (having no dopant) and the doped layer 23 (having dopants) are alternately grown in an epitaxial manner according to the disclosure, such that the breakdown voltage of the semiconductor device can be raised (due to the arrangement of the doped layer 23 with the dopants), and that the resultant semiconductor device can have favorable crystallinity and roughness (due to the arrangement of the based layers 21 having no dopant).
  • the dopants are implanted into the films of the buffer stack 200 A of the semiconductor device, which results in the issue of bowing of the entire semiconductor device. Accordingly, wafers applied for making the semiconductor device may be cracked.
  • the base layers 21 with no dopants are inserted between the doped layers 23 having the dopants, so as to prevent the buffer stack 200 A from being completely composed of the doped layers 23 with the dopants. Thereby, the issue of bowing of the entire semiconductor device can be resolved to a greater extent.
  • the base layers 21 (having no dopant) and the doped layers 23 (having dopants) are alternately grown in an epitaxial manner, such that the breakdown voltage of the semiconductor device can be raised, and that the issue of bowing of the entire semiconductor device can be resolved.
  • the semiconductor device is neither cracked nor broken due to the issue of bowing.
  • FIG. 9 is a schematic cross-sectional view of a buffer stack 200 B according to an embodiment of the disclosure.
  • the buffer stack 200 B may act as the buffer stack 200 shown in FIG. 1 .
  • the buffer stack 200 B includes at least one stack unit 50 .
  • at least one stack unit 50 includes a first base layer 51 A, a first doped layer 53 A, and a second base layer 51 B.
  • the first doped layer 53 A is positioned between the first base layer 51 A and the second base layer 51 B, i.e., the first doped layer 53 A is located inside the stack unit 50 .
  • each stack unit 50 includes a first base layer 51 A, a first doped layer 53 A, and a second base layer 51 B.
  • the first base layer 51 A and the second base layer 51 B include AlGaN
  • the first doped layer 53 A includes AlGaN or BAlGaN.
  • the first doped layer 53 A is positioned between the first base layer 51 A and the second base layer 51 B.
  • a concentration of Al of the first base layer 51 A and a concentration of Al of the second base layer 51 B are substantially the same.
  • Dopants in the first doped layer 53 A include carbon or iron, and the first base layer 51 A and the second base layer 51 B do not contain dopants (carbon or iron) substantially.
  • the first doped layer 53 A may be C-AlGaN, C-BAlGaN, Fe-AlGaN, or Fe-BAlGaN.
  • a thickness of the first doped layer 53 A of the stack unit 50 is between 10 angstroms and 1 micrometer, and a ratio of the thickness of the first doped layer 53 A to a thickness of the first base layer 51 A (or the second base layer 51 B) is between 0.001 and 1.0.
  • a concentration of the dopant in the first doped layer 53 A is between 1E17/cm 3 and 1E20/cm 3
  • a concentration of dopant in the first base layer 51 A (or the second base layer 51 B) is less than 1E17/cm 3 .
  • the buffer stack 200 B includes four stack units 50 .
  • the compositions of the first base layer 51 A and the second base layer 51 B are substantially the same.
  • Concentrations of Al in the stack units 50 from bottom to top are x1, x2, x3, and x4, respectively, concentrations of Ga in the stack units 50 from bottom to top are 1-x1, 1-x2, 1-x3, and 1-x4, respectively, and x1>x2>x3>x4. That is, the concentrations of Al in the first base layers 51 A (or the second base layers 51 B) of the four stack units 50 gradually decrease from bottom to top, and the concentrations of Ga in the first base layers 51 A (or the second base layers 51 B) of the four stack units 50 gradually increase from bottom to top.
  • concentrations of Al in the four first doped layers 53 A from bottom to top are y1, y2, y3, and y4, respectively.
  • the buffer stack 200 B includes four stack units 50 . Thicknesses of the first and second base layers 51 A and 51 B are substantially the same. The thicknesses of the first base layers 51 A (or the second base layers 51 B) from bottom to top are da1, da2, da3, and da4, respectively.
  • Thicknesses of the four first doped layers 53 A from bottom to top are dc1, dc2, dc3, and dc4, respectively.
  • FIG. 10 is a schematic cross-sectional view of a buffer stack 200 C according to an embodiment of the disclosure.
  • the buffer stack 200 C may act as the buffer stack 200 shown in FIG. 1 .
  • the same technical contents in the embodiment shown in FIG. 10 and in the buffer stacks shown in FIG. 8 and FIG. 9 will not be further explained hereinafter.
  • the buffer stack 200 C shown in FIG. 10 has a plurality of stack units 70 having five-layer structure.
  • the stack unit 70 of the semiconductor device further includes a second doped layer 53 B and a third base layer 51 C besides a first base layer 51 A, a first doped layer 53 A, and a second base layer 51 B,.
  • the second doped layer 53 B is positioned between the second base layer 51 B and the third base layer 51 C.
  • the third base layer 51 C includes AlGaN
  • the second doped layer 53 B includes AlGaN or BAlGaN
  • the dopants in the second doped layer 53 B include carbon or iron
  • the second doped layer 51 B may be C—AlGaN, C—BAlGaN, Fe—AlGaN, or Fe—BAlGaN.
  • concentrations of Al in the first base layer 51 A, the second base layer 51 B, and the third base layer 51 C are substantially the same and do not contain dopants (carbon or iron) substantially.
  • the buffer stack depicted in FIG. 10 two doped layers are inserted between the base layers composed of AlGaN, so as to form the buffer stack.
  • the concentrations of dopants in the two doped layers may the same or different.
  • one doped layer is inserted between the base layers composed of AlGaN, so as to form the buffer stack 200 B.
  • three or more doped layers may be inserted between the base layers composed of AlGaN, so as to form the buffer stack.
  • dopants are implanted into at least on film (or a partial region) in the superlattice stack, so as to form the doped layer.
  • conductivity of the superlattice stack can be reduced (i.e., the degree of insulation of the superlattice stack can be enhanced), and the breakdown voltage of the semiconductor device can be raised effectively.
  • the films with the dopants have unfavorable crystallinity and roughness.
  • the films having no dopants are grown in an epitaxial manner above the films with the dopants.
  • the films with no dopants can have favorable crystallinity and roughness, crystallinity and roughness of the epitaxy layer can also be recovered. More specifically, the films having no dopants are grown in an epitaxial manner above the doped layers with dopants and unfavorable crystallinity and roughness, so as to recover and enhance crystallinity and roughness of the epitaxy layer; thereafter, another doped layer with the dopant is grown in an epitaxial manner.
  • the films (having no dopant) and the doped layers (having dopants) are alternately grown in an epitaxial manner according to the disclosure, such that the breakdown voltage of the semiconductor device can be raised (due to the arrangement of the doped layers with the dopants), and that the resultant semiconductor device can have favorable crystallinity and roughness (due to the arrangement of the films having no dopant).
  • the dopants are implanted into the films of the superlattice stack of the semiconductor device, which results in the issue of bowing of the entire semiconductor device. Accordingly, wafers applied for making the semiconductor device may be cracked.
  • the films with no dopants are inserted between the doped layers having the dopants, so as to prevent the superlattice stack from being completely composed of the doped layers with the dopants. Thereby, the issue of bowing of the entire semiconductor device can be resolved to a greater extent.
  • the concentration of Ga in the superlattice stack also leads to the issue of the bowing of the entire semiconductor device.
  • the increase in the concentration of Al lessens the issue of the bowing of the entire semiconductor device.
  • the films having Al with high concentration can be inserted between the films having Ga with high concentration, so as to resolve the issue of bowing caused by Ga in the films and further resolve the issue of bowing of the entire semiconductor device to a greater extent.
  • the first and second films in the superlattice stack are alternately grown in an epitaxial manner, such that the breakdown voltage of the semiconductor device can be raised, and that the issue of the bowing of the entire semiconductor device can be resolved.
  • the wafers for manufacturing the semiconductor device are neither cracked nor broken due to the issue of bowing.

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