US20150333068A1 - Thyristor random access memory - Google Patents

Thyristor random access memory Download PDF

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Publication number
US20150333068A1
US20150333068A1 US14/277,068 US201414277068A US2015333068A1 US 20150333068 A1 US20150333068 A1 US 20150333068A1 US 201414277068 A US201414277068 A US 201414277068A US 2015333068 A1 US2015333068 A1 US 2015333068A1
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Prior art keywords
polarity type
region
forming
layer
gate
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US14/277,068
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English (en)
Inventor
Eng Huat Toh
Shyue Seng Tan
Elgin Kiok Boone Quek
Danny Pak-Chum Shum
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GlobalFoundries Singapore Pte Ltd
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GlobalFoundries Singapore Pte Ltd
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Assigned to GLOBALFOUNDRIES SINGAPORE PTE. LTD. reassignment GLOBALFOUNDRIES SINGAPORE PTE. LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: QUEK, ELGIN KIOK BOONE, SHUM, DANNY PAK-CHUM, TAN, SHYUE SENG, TOH, ENG HUAT
Priority to US14/277,068 priority Critical patent/US20150333068A1/en
Application filed by GlobalFoundries Singapore Pte Ltd filed Critical GlobalFoundries Singapore Pte Ltd
Priority to SG10201500456WA priority patent/SG10201500456WA/en
Priority to TW104106203A priority patent/TWI580008B/zh
Priority to DE102015206391.7A priority patent/DE102015206391B4/de
Priority to CN201510240836.3A priority patent/CN105097808B/zh
Priority to KR1020150067641A priority patent/KR20150130945A/ko
Publication of US20150333068A1 publication Critical patent/US20150333068A1/en
Assigned to WILMINGTON TRUST, NATIONAL ASSOCIATION reassignment WILMINGTON TRUST, NATIONAL ASSOCIATION SECURITY AGREEMENT Assignors: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
Priority to US16/217,064 priority patent/US11094696B2/en
Assigned to GLOBALFOUNDRIES SINGAPORE PTE. LTD. reassignment GLOBALFOUNDRIES SINGAPORE PTE. LTD. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: WILMINGTON TRUST, NATIONAL ASSOCIATION
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/102—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
    • H01L27/1027—Thyristors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/39—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using thyristors or the avalanche or negative resistance type, e.g. PNPN, SCR, SCS, UJT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66363—Thyristors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • Embodiments generally relate to memory devices and manufacturing methods thereof.
  • a device in one embodiment, includes a substrate having a well of a first polarity type and a thyristor-based memory cell.
  • the thyristor-based memory cell includes at least a first region of a second polarity type adjacent to the well, a gate which serves as a second word line disposed on the substrate, at least a first layer of the first polarity type disposed adjacent to the first region of the second polarity type and adjacent to the gate, and at least a heavily doped first layer of the second polarity type disposed on the first layer of the first polarity type and adjacent to the gate.
  • At least the heavily doped first layer of the second polarity type is self-aligned with side of the gate.
  • a method of forming a device in another embodiment, is disclosed.
  • a substrate having a well of a first polarity type is provided.
  • the method includes forming a thyristor-based memory cell.
  • the thyristor-based memory cell is formed by forming at least a first region of a second polarity type adjacent to the well, forming a gate on the substrate, forming at least a first layer of the first polarity type adjacent to the first region of the second polarity type and adjacent to the gate, and forming at least a heavily doped first layer of the second polarity type on the first layer of the first polarity type and adjacent to the gate.
  • the gate serves as a second word line and at least the heavily doped first layer of the second polarity type is self-aligned with side of the gate.
  • FIGS. 1 a - 1 b show cross-sectional views of various embodiments of a device.
  • FIGS. 3 a - 3 b show cross-sectional views of various embodiments of a device.
  • FIGS. 4 a - 4 d show cross-sectional views of other various embodiments of a device.
  • FIGS. 5 a - 5 j show cross-sectional views of an embodiment of a process for forming a device in accordance with one embodiment of the present disclosure.
  • FIGS. 6 a - 6 d show cross-sectional views of an embodiment of a process for forming a device in accordance with another embodiment of the present disclosure.
  • FIGS. 8 a - 8 e show cross-sectional views of an embodiment of a process for forming a device in accordance with yet another embodiment of the present disclosure.
  • FIGS. 10 a - 10 d show cross-sectional views of an embodiment of a process for forming a device in accordance with yet another embodiment of the present disclosure.
  • FIGS. 11 a - 11 f show cross-sectional views of an embodiment of a process for forming a device in accordance with yet another embodiment of the present disclosure.
  • FIGS. 13 a - 13 e show cross-sectional views of an embodiment of a process for forming a device in accordance with yet another embodiment of the present disclosure.
  • FIGS. 14 a - 14 b show cross-sectional views of an embodiment of a process for forming a device in accordance with yet another embodiment of the present disclosure.
  • Embodiments generally relate to memory devices and manufacturing methods thereof.
  • a memory device includes a T-RAM having a thyristor structure built on or integrated with complementary metal oxide semiconductor (CMOS) processing, with at least self-aligned first polarity type base and self-aligned elevated heavily doped second polarity type emitter layer of the anode portion of the thyristor structure.
  • CMOS complementary metal oxide semiconductor
  • the first polarity type for example, may be referred to as n-type while the second polarity type, for example, may be referred to as p-type.
  • the first polarity type for example, may be referred to as p-type while the second polarity type, for example, may be referred to as n-type.
  • the memory device according to the present disclosure offers a number of novel features vis-à-vis existing designs of memory devices. Firstly, a memory device according to the present disclosure is compact in size. Secondly, several features of a memory device according to the present disclosure are self-aligned. Thirdly, a memory device according to the present disclosure achieves better performance in terms of lower operating voltage, faster read/write operation, and better retention. Fourthly, a symmetrical two-bits-per-cell structure may be achieved. Moreover, the process of manufacturing the memory device according to the present disclosure is compatible with logic technology.
  • FIG. 1 a shows a cross-sectional view of a device 100 in accordance with one embodiment of the present disclosure.
  • the device 100 includes a 2 T-RAM structure or two-bits-per-cell structure.
  • the device 100 includes first and second thyristor structures built on or integrated with features formed by CMOS processing.
  • the device 100 includes a substrate 102 .
  • the substrate for example, is a semiconductor substrate, such as a silicon substrate.
  • the substrate is a p-type doped substrate.
  • the p-type doped substrate is a lightly doped p-type substrate.
  • Other types of semiconductor substrates may also be useful.
  • semiconductor substrates such as silicon germanium, gallium or gallium arsenide may also be useful.
  • the substrate includes a device region.
  • the device region for example, is surrounded by an isolation region (not shown).
  • the isolation region may be used to separate the device region from other device regions on the substrate (not shown).
  • the isolation region for example, is a shallow trench isolation (STI) region. Other types of isolation regions may also be employed.
  • STI shallow trench isolation
  • a well 104 of a first polarity type is disposed in the substrate 102 .
  • the dopant concentration of the well 104 may be about, for example, 10 16 cm ⁇ 3 to 10 18 cm ⁇ 3 . Other suitable dopant concentrations may also be useful.
  • the first polarity type is n-type and the second polarity type is p-type.
  • the well 104 is an n-type well or a deep n-type well (DNW), and the substrate 102 is a p-type substrate.
  • the device includes a first region 106 a of the second polarity type formed in the substrate 102 and over the well 104 , a second region 106 b of the second polarity type formed in the substrate 102 and over the well 104 , and a gate of disposed on the substrate 102 and disposed between the first and second regions of the second polarity type 106 a / 106 b .
  • the dopant concentration of the first and second regions of the second polarity type 106 a / 106 b may be about, for example, 10 16 cm ⁇ 3 to 10 18 cm ⁇ 3 . Other suitable dopant concentrations may also be useful.
  • the first and second regions of the second polarity type 106 a / 106 b include band-engineered (BE) regions.
  • BE band-engineered
  • either or both of the first and second regions of the second polarity type 106 a / 106 b include silicon germanium (SiGe), Si:C or Ge BE regions. Other suitable types of BE materials may also be useful.
  • the BE region in one embodiment, is an epitaxial BE layer.
  • the gate includes a gate electrode 114 and a gate dielectric 116 . Spacers 118 are disposed on first and second sides of the gate.
  • the gate is a high-k metal gate.
  • the gate electrode 114 may be a metal gate electrode, such as TaN or TiN.
  • the gate dielectric layer 116 it may be a high-k gate dielectric, such as HfSiON, SiON or HfO 2 .
  • HfSiON, SiON or HfO 2 a high-k gate dielectric, such as HfSiON, SiON or HfO 2 .
  • the gate electrode 114 may include polysilicon while the gate dielectric may include SiO 2 .
  • the gate dielectric may further include a work function tuning layer.
  • La 2 O 3 may be provided for an n-type device while TiN/Al/TiN may be provided for a p-type device in addition to HfSiON and/or HfO 2 .
  • Other suitable configurations of gates may also be useful.
  • the device is a 2 T-RAM or two-bits-per-cell structure having thyristor structures built on or integrated with CMOS processing.
  • the device includes a first thyristor structure having a first layer of the first polarity type 108 a disposed on the first region of the second polarity type 106 a and adjacent a first side of the gate.
  • the first thyristor structure also includes a heavily doped first layer of the second polarity type 110 a disposed on the first layer of the first polarity type 108 a and adjacent the first side of the gate.
  • the device in one embodiment, includes a second thyristor structure having a second layer of the first polarity type 108 b disposed on the second region of the second polarity type 106 b and adjacent a second side of the gate which is opposite the first side of the gate.
  • the second thyristor structure also includes a heavily doped second layer of the second polarity type 110 b disposed on the second layer of the first polarity type 108 b adjacent to the second side of the gate.
  • the dopant concentration of the heavily doped first and second layers of the second polarity type 110 a and 110 b for example, is about 10 18 cm ⁇ 3 to 10 20 cm ⁇ 3 .
  • the dopant concentration of the first and second layers of the first polarity type 108 a and 108 b for example, is about 10 17 cm ⁇ 3 to 10 19 cm ⁇ 3 .
  • Other suitable dopant concentrations may also be useful.
  • the first and second layers of the first polarity type 108 a / 108 b serve as the base while the heavily doped first and second layers of the second polarity type 110 a / 110 b serve as the emitter of the anode portion of the respective first and second thyristor structures.
  • the adjacent layer of the first polarity type and the layer of the heavily doped second polarity type form a p-n junction of the anode portion of the thyristor structure.
  • the first and second regions of the second polarity type 106 a / 106 b also serve as the base while the well 104 also serves as the emitter of the cathode portion of the respective first and second thyristor structures.
  • the adjacent layer of the second polarity type and the well form a p-n junction of the cathode portion of the thyristor structure.
  • the well also functions as the first word line of the device while the gate 114 is configured to function as a second word line of the device and is capacitively coupled to the layers of the second polarity type 106 a / 106 b through the gate dielectric 116 .
  • the device 100 further includes an interlevel dielectric (ILD) layer 120 disposed over the first and second thyristor structures and the gate.
  • the ILD layer for example, includes an oxide layer. Other suitable types of dielectric material may also be used.
  • Silicide contacts 112 may be formed between the ILD layer 120 and the heavily doped first and second layers of the second polarity type 110 a / 110 b .
  • the ILD layer 120 includes a first contact opening that is coupled to the heavily doped first layer of the second polarity type 110 a of the first thyristor structure.
  • a first electrically-conductive material is filled in the first opening of the ILD layer 120 to form the first contact 122 a and configured to couple to a first bit line of the device 100 .
  • the ILD layer 120 also includes a second contact opening that is coupled to the heavily doped second layer of the second polarity type 110 b of the second thyristor structure.
  • a second electrically-conductive material is filled in the second opening of ILD layer 120 to form the second contact 122 b and is coupled to a second bit line of the device 100 .
  • the gate is a recessed gate such that a portion of the gate is extended vertically with respect to a horizontal plane toward the well 104 to be parallel with the first and second regions of the second polarity type 106 a / 106 b with respect to the horizontal plane.
  • the first and second regions of the second polarity type 106 a / 106 b include band-engineered (BE) regions.
  • the device 100 includes first and second thyristor structures which enable a symmetrical two-bits-per-cell design to be achieved.
  • the embodiment as shown in FIG. 1 a , includes two different bits in a single cell structure. Further, the device also features self-aligned and compact first polarity type layer 108 a / 108 b and heavily doped second polarity type layer 110 a / 110 b . This helps improve variation and achieve smaller cell size.
  • the operation of the device 100 for example, is similar to the operation of a conventional T-RAM structure.
  • T-RAM structure The operation of a T-RAM structure is described in, for example, “32 nm High-density High-speed T-RAM Embedded Memory Technology”, Gupta et al., Electron Devices Meeting (IEDM), 2010 IEEE International, 2010, pp. 12.1.1-12.1.4, which is incorporated herein by reference for all purposes.
  • IEDM Electron Devices Meeting
  • FIG. 1 b shows a cross-sectional view of a memory device 150 which varies from the memory device 100 of FIG. 1 a in accordance with another embodiment of the present disclosure.
  • the description below focuses on the differences between the memory device 150 and the memory device 100 .
  • the gate of the memory device 150 does not extend below the top surface of the substrate 102 as does the gate of the memory device 100 .
  • gate electrode 164 and gate dielectric 166 of the memory device 150 do not extend below the top surface of the substrate 102 to be parallel with the first and second regions of the second polarity type 106 a / 106 b.
  • FIG. 2 a shows a cross-sectional view of a device 200 in accordance with one embodiment of the present disclosure.
  • the device 200 includes a T-RAM similar to the device shown in FIGS. 1 a - 1 b . Thus, similar features will not be described in detail.
  • the device 200 includes a well 204 of a first polarity type formed in a substrate 202 of a second polarity type, a region 206 of the second polarity type disposed over the well 204 , and a gate disposed on the substrate 202 .
  • the gate includes a gate electrode 214 and a gate dielectric 216 . Spacers 218 are disposed on first and second sides of the gate.
  • the device includes a thyristor structure having a layer of the first polarity type 208 disposed on the region of the second polarity type 206 adjacent to a first side of the gate.
  • the thyristor structure also includes a heavily doped layer of the second polarity type 210 disposed on the first layer of the first polarity type 208 adjacent to the first side of the gate.
  • the layer of the first polarity type 208 serves as the base while the heavily doped layer of the second polarity type 210 serves as the emitter of the anode portion of the thyristor structure.
  • the adjacent layer of the first polarity type and the layer of the heavily doped second polarity type form a p-n junction of the anode portion of the thyristor structure.
  • the region of the second polarity type 206 also serves as the base while the well 204 serves as the emitter of the cathode portion of the thyristor structure.
  • the adjacent layer of the second polarity type 206 and the well 204 form a p-n junction of the cathode portion of the thyristor structure.
  • the well also functions as the first word line of the device while the gate 114 is configured to function as a second word line of the device and is capacitively coupled to the layer of the second polarity type 206 through the gate dielectric 216 .
  • the device 200 further includes an ILD layer 220 disposed over the heavily doped layer of the second polarity type 210 and the gate.
  • a silicide contact 212 may be formed between the ILD layer 220 and the heavily doped layer of the second polarity type 210 .
  • the ILD layer 220 includes a contact opening that is coupled to the heavily doped layer of the second polarity type 210 .
  • An electrically-conductive material is filled in the opening of the ILD layer 220 to form the contact 222 and is coupled to a bit line of the memory device 200 .
  • the memory device 200 further includes a shallow trench isolation (STI) region 224 disposed in the well 204 .
  • STI shallow trench isolation
  • the dielectric layer 220 extends toward the substrate 202 , to be adjacent to a second side of the gate opposite the first side of the gate, and in contact with the STI region 224 .
  • the gate as shown, lands on the edge of the STI region. This may reduce the interference of one cell from another cell.
  • the region of the second polarity type 206 includes a BE region.
  • the region of the second polarity type 206 includes SiGe, Si:C or Ge BE region. Other suitable types of BE materials may also be useful.
  • the BE region in one embodiment is an epitaxial layer.
  • the gate is a recessed gate such that a portion of the gate is extended vertically with respect to a horizontal plane toward the well 204 to be parallel with the region of the second polarity type 206 with respect to the horizontal plane.
  • the embodiment features a 1-bit-per-cell structure.
  • the structure of the memory device 200 has self-aligned and compact first polarity type layer 208 and heavily doped second polarity type layer 210 . This helps improve variation and achieve smaller cell size.
  • the operation of the device 200 is similar to the operation of a conventional T-RAM structure as mentioned above.
  • FIG. 2 b shows a cross-sectional view of a device 250 which varies from the device 200 of FIG. 2 a in accordance with another embodiment of the present disclosure.
  • the description below focuses on the differences between the device 250 and the device 200 .
  • the gate of the device 250 does not extend below the top surface of the substrate 202 as does the gate of the device 200 .
  • gate electrode 264 , gate dielectric 266 and spacers 268 of the device 250 do not extend below the top surface of the substrate 202 to be parallel with the region of the second polarity type 256 .
  • FIG. 3 a shows a cross-sectional view of a device 300 in accordance with one embodiment of the present disclosure.
  • the device 300 may include similar features as already described in FIGS. 1 a - 1 b and FIGS. 2 a - 2 b . Thus, similar features will not be described in detail.
  • the device 300 includes a 2 T-RAM structure or two-bits-per-cell structure having a well 304 of a first polarity type formed in a substrate 302 of a second polarity type.
  • the device includes a first fin structure correspond to a first region 306 a of the second polarity type disposed over the well 304 , a second fin structure corresponds to a second region 306 b of the second polarity type formed over the well 304 , and a gate disposed on the substrate 302 and in between the first and second regions of the second polarity type 306 a / 306 b .
  • the first and second regions of the second polarity type 306 a / 306 b include band-engineered (BE) regions.
  • the gate includes a gate electrode 314 and a gate dielectric 316 . Spacers 318 are disposed on first and second sides of the gate.
  • the device 300 further includes a STI region 324 formed in the well 304 . As shown in FIG. 3 a , the STI region 324 is directly below the gate.
  • the device 300 includes thyristor structures built on or integrated with fin-type CMOS processing.
  • the device includes a first thyristor structure having a first layer of the first polarity type 308 a disposed on the first region of the second polarity type 306 a of the first fin structure and adjacent a first side of the gate.
  • the first thyristor structure also includes a heavily doped first layer of the second polarity type 310 a disposed on the first layer of the first polarity type 308 a and adjacent the first side of the gate.
  • the device in one embodiment, includes a second thyristor structure having a second layer of the first polarity type 308 b disposed on the second region of the second polarity type 306 b of the second fin structure and adjacent a second side of the gate which is opposite the first side of the gate.
  • the second thyristor structure also includes a heavily doped second layer of the second polarity type 310 b disposed on the second layer of the first polarity type 308 b adjacent to the second side of the gate.
  • the materials and the dopant concentrations of the respective regions or layers are the same as that already described in FIGS. 1 a - 1 b above.
  • the first and second layers of the first polarity type 308 a / 308 b serve as the base while the heavily doped first and second layers of the second polarity type 310 a / 310 b serve as the emitter of the anode portion of the respective first and second thyristor structures.
  • the adjacent layer of the first polarity type and the layer of the heavily doped second polarity type form a p-n junction of the anode portion of the thyristor structure.
  • the first and second regions of the second polarity type 306 a / 306 b also serve as the base while the well 304 also serves as the emitter of the cathode portion of the respective first and second thyristor structures.
  • the adjacent layer of the second polarity type and the well form a p-n junction of the cathode portion of the thyristor structure.
  • the well also functions as the first word line of the device while the gate 314 is configured to function as a second word line of the device and is capacitively coupled to the layers of the second polarity type 306 a / 306 b through the gate dielectric 316 .
  • the device 300 further includes an ILD layer 320 disposed over the heavily doped layers of the second polarity type 310 a / 310 b of the first and second thyristor structures and the gate. Silicide contacts 312 may be formed between the ILD layer 320 and the heavily doped layers of the second polarity type 310 a / 310 b .
  • the ILD layer 320 includes a first contact opening that is coupled to the heavily doped first layer of the second polarity type 310 a of the first thyristor structure.
  • a first electrically-conductive material is filled in the first opening of the ILD layer 320 to form the first contact 322 a and configured to couple to a first bit line of the device 300 .
  • the ILD layer 320 also includes a second contact opening that is coupled to the heavily doped second layer of the second polarity type 310 b of the second thyristor structure.
  • a second electrically-conductive material is filled in the second opening of ILD layer 320 to form the second contact 322 b and is coupled to a second bit line of the device 300 .
  • the gate of the MOS structure is a recessed gate such that a portion of the gate is extended vertically with respect to a horizontal plane toward the well 304 to be parallel with the first and second regions of the second polarity type 306 a / 306 b with respect to the horizontal plane.
  • the first and second regions of the second polarity type 306 a / 306 b include BE region.
  • the device 100 includes first and second thyristor structures which enable a symmetrical two-bits-per-cell design to be achieved.
  • the embodiment as shown in FIG. 3 a , includes two different bits in a single cell structure. Further, the device also features self-aligned and compact first polarity type layer 308 a / 308 b and heavily doped second polarity type layer 310 a / 310 b . This helps improve variation and achieve smaller cell size.
  • FIG. 3 b shows a cross-sectional view of a device 350 which varies from the device 300 of FIG. 3 a in accordance with another embodiment of the present disclosure.
  • the device 350 includes a T-RAM or a 1-bit-per-cell structure having a well 304 of a first polarity type formed in a substrate 302 of a second polarity type, a fin structure correspond to a region 306 of the second polarity type defined on the substrate 302 and over the well 304 , and a gate disposed on the substrate 302 .
  • the region 306 of the second polarity type includes a BE region.
  • the gate includes a gate electrode 314 and a gate dielectric 316 . Spacers 368 are disposed on first and second sides of the gate.
  • the device 350 includes a thyristor structure having a layer of the first polarity type 308 disposed on the region of the second polarity type 306 of the fin structure and adjacent to a first side of the gate.
  • the thyristor structure also includes a heavily doped layer of the second polarity type 310 disposed on the first layer of the first polarity type 308 and adjacent to the first side of the gate.
  • the layer of the first polarity type 308 serves as the base while the heavily doped layer of the second polarity type 310 serves as the emitter of the anode portion of the thyristor structure.
  • the adjacent layer of the first polarity type and the layer of the heavily doped second polarity type form a p-n junction of the anode portion of the thyristor structure.
  • the region of the second polarity type 306 also serves as the base while the well 304 also serves as the emitter of the cathode portion of the thyristor structure.
  • the adjacent layer of the second polarity type and the well form a p-n junction of the cathode portion of the thyristor structure.
  • the well also functions as the first word line of the device while the gate 314 is configured to function as a second word line of the device and is capacitively coupled to the layer of the second polarity type 306 through the gate dielectric 316 .
  • the device 350 further includes an ILD layer 370 disposed over the thyristor structure and the gate.
  • a silicide contact may be formed between the ILD layer 370 and the thyristor structure.
  • the ILD layer 370 includes an opening that is coupled to the heavily doped layer of the second polarity type 310 .
  • An electrically-conductive material 322 is filled in the opening of the ILD layer 370 and is coupled to a bit line of the memory device 350 .
  • the device 350 further includes a STI region 374 formed in the well 304 below the gate. As shown in FIG. 3 b , the dielectric layer 370 extends toward the substrate 302 , to be adjacent a second side of the gate which is opposite to the first side of the gate, and in contact with the STI region 374 .
  • the gate of the MOS structure is a recessed gate such that a portion of the gate is extended vertically with respect to a horizontal plane toward the well 304 to be parallel with the region of the second polarity type 306 with respect to the horizontal plane.
  • the region of the second polarity type 306 includes a BE region.
  • FIG. 4 a shows a cross-sectional view of a device 400 in accordance with one embodiment of the present disclosure.
  • the device 400 includes a T-RAM having a well 404 of a first polarity type (or, alternatively, a region of isolation buffer which includes amorphous silicon) formed in a substrate 402 of a second polarity type, a body region 406 of the second polarity type formed in the substrate 402 and over the well 404 (or the region of isolation buffer), a lightly or intermediately doped region of the first polarity type 408 a and a heavily doped region of the first polarity type 408 b formed in the body region 406 , and a gate disposed on the substrate 402 and over the body region 406 .
  • a first polarity type or, alternatively, a region of isolation buffer which includes amorphous silicon
  • the gate includes a gate electrode 414 and a gate dielectric 416 . Spacers 418 are disposed on first and second sides of the gate.
  • the first polarity type is n-type and the second polarity type is p-type.
  • the well 404 is an n-type well or a deep n-type well (DNW)
  • the substrate 402 is a p-type substrate.
  • the substrate 402 includes a region of isolation buffer having amorphous-silicon instead of a well of the first polarity type, the region of amorphous silicon replaces the need for a buried oxide layer in the substrate 402 . This helps achieve floating body second polarity type base and eliminate high cost associated with producing silicon-on-insulator.
  • the device 400 further includes first and second electrically-conductive materials filled in the first and second openings of the ILD layer 420 to form first and second contacts 422 a / 422 b .
  • the first contact 422 a is configured to be coupled to a bit line while the second contact 422 b is coupled to a first word line of the memory device 400 .
  • the gate is configured to function as a second word line of the memory device 400 and is capacitively coupled to the body region of the second polarity type 406 through the gate dielectric 416 .
  • FIG. 4 b shows a cross-sectional view of a device 430 which varies from the device 400 of FIG. 4 a in accordance with another embodiment of the present disclosure.
  • the description below focuses on the differences between the device 430 and the device 400 .
  • FIG. 4 c shows a cross-sectional view of a device 450 in accordance with one embodiment of the present disclosure.
  • the device 450 includes a T-RAM having a well 404 of a first polarity type (or, alternatively, an isolation buffer having amorphous silicon) formed in a substrate 402 of a second polarity type, a body region 406 of the second polarity type formed in the substrate 402 and over the well 404 (or the isolation buffer), a lightly or intermediately doped region of the first polarity type 408 a and a heavily doped region of the first polarity type 408 b formed in the body region 406 adjacent to the first and second sidewalls of the gate, and a gate disposed on the substrate 402 and over the body region 406 .
  • a T-RAM having a well 404 of a first polarity type (or, alternatively, an isolation buffer having amorphous silicon) formed in a substrate 402 of a second polarity type, a body region
  • the gate includes a gate electrode 414 and a gate dielectric 416 . Spacers 418 are disposed on first and second sides of the gate.
  • the first polarity type is n-type and the second polarity type is p-type.
  • the well 404 is an n-type well or a deep n-type well (DNW)
  • the substrate 402 is a p-type substrate.
  • the substrate 402 includes an isolation buffer which includes amorphous silicon instead of a well of the first polarity type
  • the region of isolation buffer replaces the need for a buried oxide layer in the substrate 402 . This helps achieve floating body second polarity type base and eliminate high cost associated with producing silicon-on-insulator.
  • the device 450 includes a thyristor structure having an elevated self-aligned heavily doped layer of the second polarity type 410 disposed on the region of the first polarity type 408 a disposed in the substrate and adjacent to the first side of the gate.
  • the region of the first polarity type 408 a serves as the base while the heavily doped layer of the second polarity type 410 serves as the emitter of the anode portion of the thyristor structure.
  • the adjacent region of the first polarity type and the elevated layer of the heavily doped second polarity type form a p-n junction of the anode portion of the thyristor structure.
  • the body region of the second polarity type 406 also serves as the base while the heavily doped region of the first polarity type 408 b disposed in the substrate adjacent to the second side of the gate also serves as the emitter of the cathode portion of the thyristor structure.
  • the adjacent body region of the second polarity type and the heavily doped region of the first polarity type form a p-n junction of the cathode portion of the thyristor structure.
  • the device 450 also includes an ILD layer 420 disposed over the thyristor structure and the substrate. Silicide contacts 412 a / 412 b may be formed between the ILD layer 420 and the heavily doped layer of the first polarity type 410 and heavily doped region of the first polarity type 408 b .
  • the ILD layer 420 includes first and second contact openings. The first contact opening is coupled to the heavily doped layer of the second polarity type 410 of the thyristor structure. The second opening is coupled to the heavily doped region of the first polarity type 408 b .
  • the device 400 further includes first and second electrically-conductive materials filled in the first and second openings of the ILD layer 420 to form first and second contacts 422 a / 422 b .
  • the first contact 422 a is configured to be coupled to a bit line while the second contact 422 b is coupled to a first word line of the memory device 450 .
  • the gate is configured to function as a second word line of the memory device 450 .
  • a portion in the body region 406 of the second polarity type below the gate includes a BE portion 455 .
  • the BE portion 455 includes SiGe BE portion. Other suitable types of BE material may also be useful.
  • the gate is capacitively coupled to the BE portion 455 through the gate dielectric 416 .
  • the device 450 has self-aligned and compact first polarity type region 408 a and heavily doped second polarity type layer 410 . This avoids the need of silicide block layer and helps improve variation and achieve smaller cell size.
  • FIG. 4 d shows a cross-sectional view of a device 470 which varies from the device 450 of FIG. 4 c in accordance with another embodiment of the present disclosure.
  • the description below focuses on the differences between the device 470 and the device 450 .
  • the thyristor structure of the device 470 includes a self-aligned elevated layer of the first polarity type 438 disposed on the substrate 402 and over the body region 406 of the second polarity type.
  • the thyristor structure also includes a self-aligned heavily doped layer of the second polarity type 410 disposed on the layer of the first polarity type 438 .
  • FIGS. 5 a - 5 j show cross-sectional views of an embodiment of a process 500 for forming a device in accordance with one embodiment of the present disclosure.
  • the process 500 forms the device 150 of FIG. 1 b .
  • the device 150 includes a 2 T-RAM structure or 2-bits-per-cell structure.
  • the process 500 forms first and second thyristor structures integrated with CMOS processing.
  • a substrate 102 is provided.
  • the substrate is a semiconductor substrate, such as a silicon substrate.
  • the substrate is a second polarity type doped substrate.
  • the substrate is lightly doped with second polarity type dopants.
  • the second polarity type dopants for example, include p-type dopants.
  • Other suitable types of semiconductor substrates may also be useful.
  • the substrate includes a device region.
  • the device region in one embodiment, serves as a cell region for a memory cell. It is, however, understood that the substrate may include a plurality of device regions.
  • the cell region serves as a device region of a 2 T-RAM. Numerous cell regions may be provided in an array region to form a plurality of memory devices. Isolation regions (not shown) are formed in the substrate 102 .
  • the isolation region serves to isolate the cell region from other device regions (not shown) for other types of devices.
  • the isolation region for example, is a shallow trench isolation (STI) region. Other types of isolation regions may also be useful.
  • the STI regions may be formed using various suitable techniques.
  • the process continues to form a well 104 .
  • the well in one embodiment, includes first polarity type dopants.
  • the first polarity type dopants for example, are n-type dopants.
  • the dopant concentration is, for example, 10 16 cm ⁇ 3 to 10 18 cm ⁇ 3 .
  • Other suitable types of dopants and dopant concentrations may also be useful.
  • the well 104 extends to a depth below the isolation regions (not shown). Other suitable depths may also be useful.
  • the well 104 for example, may be part of the substrate. For example, dopants are implanted into the substrate to form the well. Providing any suitable implant energies and doses may also be useful.
  • the implant parameters are tailored to produce the well at the desired location and have the desired effect.
  • the location and thickness of the well can be controlled.
  • Other techniques for providing the well may also be useful.
  • the well may be an epitaxial isolation well.
  • the epitaxial well may be formed prior to forming the isolation regions.
  • the epitaxial well may be in-situ doped. Implanting the epitaxial isolation well may also be useful.
  • the process continues to form a gate or a dummy gate structure.
  • a gate dielectric layer and a gate electrode layer over the top surface of the substrate includes silicon oxide (SiO 2 ).
  • the dielectric layer is formed by, for example, thermal oxidation, chemical vapor deposition (CVD) or atomic layer deposition (ALD).
  • the thickness of the gate dielectric layer may be about 1-5 nm.
  • the gate electrode layer for example, includes polysilicon. Other suitable types of gate electrode materials may also be useful.
  • the thickness of the gate electrode can be about 20-200 nm.
  • the gate electrode layer for example, can be formed by CVD. Other suitable techniques for forming and other suitable thickness dimensions for the gate dielectric and electrode layers may also be useful.
  • the gate layers are processed to form a gate or dummy gate having a patterned gate dielectric 566 and gate electrode 564 .
  • the patterning of the gate layers can be achieved, for example, by mask and etch techniques.
  • a patterned photoresist mask may be used as an etch mask for an anisotropic etch, such as a reactive ion etch (RIE).
  • RIE reactive ion etch
  • an ARC can be provided beneath the photoresist.
  • Other techniques for patterning the gate layers to form the dummy gate may also be useful.
  • the mask, including the ARC layer may be removed.
  • the process continues to form regions of second polarity type 106 a / 106 b in the substrate adjacent to first and second sides of the dummy gate as shown in FIG. 5 c .
  • the regions 106 a / 106 b include lightly doped second polarity type dopants.
  • second polarity type dopants such as p-type dopants, are implanted into the substrate.
  • the implant may be self-aligned with respect to the dummy gate.
  • the implant may dope the substrate unprotected by the dummy gate and isolation region.
  • the depth of the lightly doped regions for example, is about 5-100 nm. Other suitable depth dimensions may also be useful, depending on technology node.
  • the dopant concentration of the regions 106 a / 106 b may be about 10 16 cm ⁇ 3 to 10 18 cm ⁇ 3 . Other suitable dopant concentrations may also be useful.
  • An implant mask which exposes the device region may be provided to perform the implant.
  • the implant mask for example, may be a photoresist layer. Other suitable types of implant masks may also be useful.
  • the regions 106 a / 106 b in the substrate adjacent to first and second sides of the dummy gate as shown in FIG. 5 c include BE regions.
  • either or both of the first and second regions of the second polarity type 106 a / 106 b include BE region.
  • the BE regions may be formed by recessing portions of the substrate unprotected by the gate using various suitable techniques. The depth of the recesses, for example, may be about the same as the depth of lightly doped diffusion regions of other device regions.
  • the BE regions may be formed by, for example, selective epitaxial growth (SEG) process with in situ doping, filling the spaces or recesses.
  • SEG selective epitaxial growth
  • the top of the BE regions is about coplanar with the top of the substrate surface. Forming the BE regions which are slightly recessed or over the substrate surface may also be useful.
  • the BE regions in one embodiment, are SiGe BE regions. In one embodiment, the BE regions include second polarity type dopants. Other suitable types of BE regions may also be useful.
  • Spacers 118 may be formed over the first and second gate sidewalls.
  • a spacer layer is deposited on the substrate.
  • the spacer layer may be silicon nitride. Other suitable types of dielectric material, such as silicon oxide or silicon oxynitride may also be used.
  • the spacer layer may be formed by CVD.
  • the spacer layer may also be formed using other techniques.
  • the thickness of the spacer layer may be about, for example, 10-50 nm. Other suitable thickness ranges may also be useful. The thickness, for example, may depend on the desired width of the spacers.
  • An anisotropic etch, such as RIE may be performed to remove horizontal portions of the spacer layer, leaving spacers 118 on the sidewalls of the dummy gate as shown in FIG. 5 c.
  • the steps illustrated with respect to FIGS. 5 a - 5 c above are general steps performed for forming, for example, second polarity type MOS structure, such as PMOS structure.
  • the process continues to integrate first and second thyristor structures in CMOS processing.
  • the process continues to form elevated first and second layers of the first polarity type 108 a / 108 b over the first and second regions of the second polarity type 106 a / 106 b as shown in FIG. 5 d .
  • the first and second layers of the first polarity type 108 a / 108 b are formed by, for example, SEG process.
  • the epitaxial layers are in-situ doped with first polarity type dopants, such as n-type dopants. Doping the epitaxial layers with first polarity type dopants by ion implantation may also be useful.
  • the first and second layers of the first polarity type 108 a / 108 b of the first and second thyristor structures may be formed as part of the process for forming first polarity type epitaxial raised source/drain (RSD) regions of other devices on the same substrate.
  • RSD raised source/drain
  • the thickness of the first and second layers of the first polarity type 108 a / 108 b is about 10-50 nm and the dopant concentration of the first polarity type is about 10 17 cm ⁇ 3 to 10 19 cm ⁇ 3 .
  • Other suitable thickness dimensions and concentrations may also be useful.
  • first and second heavily doped second polarity type layers 110 a / 110 b are formed on the first and second layers of the first polarity type 108 a / 108 b .
  • the first and second heavily doped second polarity type layers 110 a / 110 b are formed by, for example, SEG process.
  • the epitaxial layers are heavily in-situ doped with second polarity type dopants, such as p-type dopants. Heavily doping the epitaxial layers with second polarity type dopants by ion implantation may also be useful.
  • the first and second heavily doped second polarity type layers 110 a / 110 b of the first and second thyristor structures may be formed as part of the process for forming second polarity type epitaxial raised source/drain (RSD) regions of other devices on the same substrate.
  • the thickness of the first and second heavily doped second polarity type layers 110 a / 110 b is about 10-50 nm and the dopant concentration of the second polarity type is about 10 18 cm ⁇ 3 to 10 20 cm ⁇ 3 . Other suitable thickness dimensions and concentrations may also be useful.
  • silicide contacts 112 may be formed on the first and second heavily doped second polarity type layers 110 a / 110 b .
  • the silicide contacts may be nickel-based metal silicide layers. Other suitable types of silicide contacts may also be useful.
  • the silicide contacts facilitate reduced contact resistance.
  • a metal layer may be deposited over the substrate and annealed to cause a reaction with silicon. Unreacted metal is removed by, for example, a wet etch, leaving the silicide contacts on the heavily doped first and second layers of the second polarity type 110 a / 110 b as shown in FIG. 5 f.
  • an interlevel dielectric (ILD) layer is formed over the substrate.
  • the ILD layer for example, is a silicon oxide layer.
  • the ILD layer may be a high aspect ratio process (HARP) dielectric layer.
  • HTP high aspect ratio process
  • Other suitable types of dielectric materials including BPSG, PSG, USG, TEOS oxide, PEOX, HDP oxide, etc., may also be useful.
  • the ILD layer for example, may be formed by CVD. Other suitable techniques may also be useful. Excess dielectric material of the ILD layer is removed by planarization process, such as CMP. Other types of planarization processes may also be useful.
  • the CMP for example, may use the dummy gate as a CMP stop. For example, the CMP forms a substantially coplanar surface between the top surfaces of the dummy gate, sidewall spacers and ILD layer 120 as shown in FIG. 5 g.
  • the process may continue to form additional dielectric layer to form a pre-metal dielectric (PMD) layer in which contacts are formed to contact regions of the substrate, followed by BEOL process.
  • the dummy gate is removed as shown in FIG. 5 h .
  • a dual etch process using different chemistries, for example, may be employed to remove the dummy gate electrode and gate dielectric.
  • a dry etch followed by a wet etch/clean process are performed to remove the dummy gate electrode 564 by etch selectivity control of the dummy gate to the ILD layer 120 and spacers 118 .
  • the removal of the gate dielectric layer 566 in one embodiment, it is removed by reactive ion etch (RIE).
  • RIE reactive ion etch
  • Other suitable techniques for removing the dummy gate may also be useful.
  • the removal of the dummy gate forms a gate opening 582 which exposes sides of the spacers 118 which are away from the ILD 120 as shown.
  • the process continues by forming a high-k metal gate structure.
  • the high-k metal gate structure includes a gate dielectric 166 and a gate electrode 164 .
  • the gate dielectric for example, includes high-k dielectric material, such as HfSiON, SiON or HfO 2 . Other suitable types of dielectric materials may be useful.
  • the thickness of the gate dielectric layer for example, may be about 1-10 nm.
  • the gate electrode layer for example, includes metal or metal nitride. Various suitable types of metal, such as Ru, W, Pt, TiN, Ti, Zr, TaN, Si or Al, can be used. Other suitable types of metals may also be useful.
  • the thickness of the gate electrode can be about 10-200 nm. Other suitable thickness dimensions for the gate dielectric and electrode layers may also be useful.
  • a work function tuning layer may be formed in between the gate dielectric and the metal gate electrode layer.
  • La 2 O 3 may be formed for an n-type device while TiN/Al/TiN may be formed for a p-type device in addition to HfSiON and/or HfO2.
  • Other configurations of gates may also be useful.
  • the gate dielectric and gate electrode layers are conformally formed on the substrate.
  • the gate dielectric layer lines the ILD 120 , exposed sides of the sidewall spacers 118 and the exposed portion of the substrate while the gate electrode layer covers the gate dielectric layer and fills the gate opening 582 .
  • the gate dielectric layer may be formed by, for example, atomic layer deposition technique while the gate electrode layer is formed by sputtering or CVD. Forming the gate dielectric and gate electrode layers by other techniques may also be useful.
  • the substrate is planarized to remove excess gate dielectric and electrode materials.
  • the planarization process removes excess materials over the ILD layer 120 .
  • the planarization process is CMP.
  • Other types of planarization processes may also be useful.
  • the CMP for example, may use the ILD layer 120 as a CMP stop.
  • the planarization process forms a substantially coplanar surface with the ILD layer 120 , the sidewalls spacers 118 , the gate dielectric and gate electrode layers 166 and 164 .
  • the planarization process forms high-k metal gate structure in the gate opening.
  • a planarizing process such as CMP, removes excess conductive layer, forming contacts 122 a / 122 b having a substantially coplanar surface with the top surface of the ILD layer 120 .
  • Other techniques for forming contacts may also be useful.
  • the first contact 122 a is configured to function as a first bit line of the memory device 150 while the second contact 122 b is configured to function as a second bit line of the memory device 150 .
  • the first and second contacts 122 a / 122 b are coupled to the respective heavily doped first and second layers of the second polarity type 110 a / 110 b of the first and second thyristor structures. Contacts to the gate (not shown) are formed at the end of the gate.
  • the embodiment as described in FIGS. 5 a - 5 j result in advantages.
  • the embodiment as described in FIGS. 5 a - 5 j enables the formation of a 2 T-RAM, allowing two different bits to be formed in a single cell area.
  • the first and second regions of the second polarity type 106 a / 106 b may include band-engineered (BE) regions. This helps lowering the operating voltage, improve read/write speed, and further improve retention time of the memory device 150 .
  • BE band-engineered
  • the SEG processes enable self-aligned and compact first polarity type layers 108 a / 108 b and heavily doped second polarity type layer 110 a / 110 b to be formed vertically over the substrate and adjacent to sidewalls of the gate. This helps improve variation and achieve smaller cell size.
  • the process may continue to form additional dielectric layer to form a pre-metal dielectric (PMD) layer in which contacts are formed to contact regions of the substrate, followed by BEOL process.
  • PMD pre-metal dielectric
  • the dummy gate is removed as shown in FIG. 6 b using techniques as described in FIG. 5 h . Other suitable techniques may also be employed to remove the dummy gate. The removal of the dummy gate exposes a portion of the top surface of the substrate.
  • the process continues to form a trench 663 which extends to within a portion of the well 104 and portions of the regions of second polarity type 106 a / 106 b under the dummy gate. A mask and etch process is employed to remove portions of the substrate within the well to form the trench 663 .
  • the trench is formed by RIE.
  • the sides of the trench for example, are self-aligned to the inner sides of the spacers 118 .
  • the depth of the trench is about equal to the depth of the regions of second polarity type 106 a / 106 b . Providing other depths or configurations may also be useful.
  • the process continues to form a high-k metal gate structure.
  • the materials and techniques for forming the high-k metal gate structure is the same as that described in FIG. 5 i .
  • the process may continue to complete the memory cell. For example, the process continues to form PMD layer, contacts, etc., until a device shown in FIG. 6 d is formed. Additional processes may be performed, including forming one or more interconnect levels, final passivation, dicing, assembly and packaging. Techniques and materials of these features are the same as that already described in FIG. 5 j . As such, details of these steps will not be described.
  • a partially processed substrate is provided.
  • the partially processed substrate shows an isolation region 224 formed in the substrate.
  • the isolation region includes STI region which serves to isolate the cell region from other device regions (not shown) for other types of devices.
  • the partially processed substrate also includes a well 204 having first polarity type dopants.
  • the well 204 extends to a depth below the isolation region 224 . Other suitable depths may also be useful.
  • the STI region and the well may include the same material and formed using various suitable techniques already described in FIG. 5 a.
  • the process continues to form a gate or dummy gate having dummy gate electrode 764 and gate dielectric 766 and spacers 268 .
  • the materials and techniques for forming the dummy gate and spacers 268 are the same as that described in FIG. 5 c , except that the dummy gate is patterned such that one side of the dummy gate and its adjacent spacer are formed over a portion of the isolation region 224 as shown in FIG. 7 c .
  • the second side of the dummy gate is substantially aligned with the edge of the STI region adjacent to the region of the second polarity type 256 . Providing the second side of the dummy gate which partially overlaps the STI region 224 may also be useful.
  • the process 700 continues to form silicide contact 212 over the heavily doped layer of the second polarity type 210 and an ILD layer 270 over the substrate, covering the dummy gate and top of the isolation region 224 as shown in FIG. 7 e .
  • the materials and techniques for forming the silicide contact 212 and the ILD 270 are the same as that described in FIGS. 5 f - 5 g .
  • the ILD layer is processed such that its top surface is substantially coplanar with the top surfaces of the dummy gate and spacers.
  • the process may continue to form additional dielectric layer to form a pre-metal dielectric (PMD) layer in which contacts are formed to contact region of the substrate, followed by BEOL process.
  • PMD pre-metal dielectric
  • the dummy gate is removed using techniques as described in FIG. 5 h . The removal of the dummy gate exposes a portion of the top surface of the region of the second polarity type 256 and a portion of the isolation region 224 under the dummy gate.
  • the process continues to form high-k metal gate structure having high k dielectric 266 and metal gate electrode 264 as illustrated in FIG. 7 g .
  • the materials and techniques for forming the high-k metal gate structure is the same as that described in FIG. 5 i .
  • the process may continue to complete the memory cell. For example, the process continues to form PMD layer, contact 222 , etc., until a device shown in FIG. 7 h is formed. As shown, the ILD layer 270 includes contact 222 that is coupled to the heavily doped layer of the second polarity type 210 of the T-RAM. Additional processes may be performed, including forming one or more interconnect levels, final passivation, dicing, assembly and packaging. Techniques and materials of these features are the same as that already described in FIG. 5 j . As such, details of these steps will not be described.
  • the process 800 forms a region of the second polarity type 206 over the substrate as shown in FIG. 8 a .
  • the region of the second polarity type 206 in one embodiment, is formed by SEG process.
  • the epitaxial layer 206 in one embodiment, is in-situ doped with second polarity type dopants, such as p-type dopants. Doping the epitaxial layer with second polarity type dopants by ion implantation may also be useful.
  • the region of the second polarity type may also include a BE region.
  • the process 800 continues to form the dummy gate and sidewall spacers 218 may be formed over the first and second gate sidewalls.
  • the sidewall spacers are formed using the same material and technique as already described in FIG. 5 c . As shown in FIG. 8 a , the first sidewall spacer adjacent to the first gate sidewall extends to the top surface of the region of the second polarity type 206 while the second sidewall spacer adjacent to the second gate sidewall and sidewall of the second polarity type 206 extends to the top of the STI region 224 .
  • the process 800 continues to form elevated layers of the first polarity type 208 and the heavily doped layer of the second polarity type 210 on the region of the second polarity type 206 and adjacent to a first side of the dummy gate as shown in FIG. 8 a .
  • Silicide contact 212 is formed over the heavily doped layer of the second polarity type 210 and an ILD layer 270 is formed over the substrate and is processed as shown in FIG. 8 b . Materials and techniques for forming these layers are the same as that described in FIGS. 7 d - 7 e.
  • the dummy gate structure is removed using techniques as described in FIG. 5 h .
  • Other suitable techniques may also be employed to remove the dummy gate.
  • the removal of the dummy gate exposes a portion of the top surface of the region of the second polarity type 206 .
  • the process continues to form a trench 863 within a portion of the region of the second polarity type 206 under the dummy gate.
  • a mask and etch process is employed to remove a portion of the region of the second polarity type 206 to form the trench 863 .
  • the trench is formed by RIE.
  • the sides of the trench for example, are self-aligned to the inner sides of the spacers 218 .
  • the depth of the trench is about equal to the depth of the region of second polarity type 206 . Providing other depths or configurations may also be useful.
  • the process continues to form a high-k metal gate structure.
  • the materials and techniques for forming the high-k metal gate structure is the same as that described in FIG. 5 i .
  • the process may continue to complete the memory cell. For example, the process continues to form PMD layer, contact 222 , etc., until a device shown in FIG. 8 e is formed. Additional processes may be performed, including forming one or more interconnect levels, final passivation, dicing, assembly and packaging. Techniques and materials of these features are the same as that already described in FIG. 5 j . As such, details of these steps will not be described.
  • FIGS. 9 a - 9 h show cross-sectional views of an embodiment of a process 900 for forming a device in accordance with yet another embodiment of the present disclosure.
  • the process 900 forms the device 300 of FIG. 3 a .
  • the process 900 forms first and second thyristor structures integrated with fin-type MOS processing.
  • the process 900 may contain similar steps as that described in FIGS. 5 a - 5 j . In the interest of brevity, common elements may not be described or described in detail.
  • the substrate may be a silicon substrate.
  • the substrate may be lightly doped with second polarity type dopants, for example, p-type dopants.
  • second polarity type dopants for example, p-type dopants.
  • substrates including SiGe, Ge and group III-V semiconductors such as GaAs, InP and InAs, including substrates doped with other types of dopants or undoped substrates, are also useful.
  • the substrate may be prepared with a device region. In one embodiment, the device region serves as a region for fin-type transistors.
  • the substrate is described with one device region, it is understood that the substrate may include numerous device regions (not shown). The numerous device regions may include different types of device regions.
  • the substrate is processed to form a plurality of fin structures.
  • the substrate is processed to form first and second fin structures 320 a / 320 b .
  • the substrate may be processed to form more than two fin structures.
  • the height of the fin for example, may be about 10-200 nm.
  • As for the width it may be about 3-500 nm. Other suitable fin dimensions may also be useful.
  • Forming the fin structures 320 a / 320 b may be achieved using various methods.
  • the fin structures may be formed by patterning the substrate. For example, a patterned hard mask (not shown) is formed over the substrate.
  • a hard mask layer (not shown), such as silicon oxide or silicon nitride, is formed on the substrate 302 .
  • Other suitable types of materials which are selective to the isolation layer as will be described later may also be used as the hard mask layer.
  • the hard mask layer may be formed by chemical vapor deposition (CVD). Other suitable types of hard mask or techniques for forming the hard mask may also be useful.
  • the hard mask layer is patterned to correspond to the shape of the fin structures.
  • the patterning of the hard mask layer can be achieved by mask and etch techniques.
  • a patterned soft mask such as photoresist
  • the soft mask may be patterned by photolithography.
  • an ARC (not shown) may be provided beneath the photoresist.
  • the pattern of the photoresist mask is transferred to the hard mask by, for example, an anisotropic etch, such as a reactive ion etch (RIE).
  • RIE reactive ion etch
  • An anisotropic etch such as a RIE, is performed to remove portions of the substrate surface unprotected by the hard mask, leaving fin structures 320 a / 320 b as described above disposed on the top surface of the substrate.
  • Other suitable methods may also be employed to form the fin structure.
  • the hard mask (not shown), remains on the top surface of the fin.
  • the process continues to form the isolation layer or region 324 .
  • An isolation layer such as a dielectric layer which includes a silicon oxide layer, is formed over the substrate covering the fin structure.
  • the isolation layer may be formed over the substrate using chemical vapor deposition (CVD) or high aspect ratio process (HARP). Other techniques for forming the isolation layer may also be useful.
  • CVD chemical vapor deposition
  • HTP high aspect ratio process
  • a polishing process such as a chemical mechanical polishing process (CMP) is performed to planarize the isolation layer to the top surface of the hard mask over the fin structures.
  • CMP chemical mechanical polishing process
  • a removal process such as selective to the isolation layer which includes oxide material, is performed to remove or recess portions of the oxide to form the isolation region 324 and a gap or opening 982 between the fin structures as shown in FIG. 9 a .
  • the removal process may include dry etch, wet etch or a combination thereof.
  • the isolation layer for example, has a height or thickness sufficient to provide isolation from the substrate below.
  • the thickness of the isolation layer for example, may be about 10-500 nm. Other suitable thickness ranges may also be useful.
  • a well 304 is formed in the substrate as shown in FIG. 9 b .
  • the well in one embodiment, includes first polarity type dopants.
  • first polarity type dopants are implanted into the substrate.
  • a well implant mask may be used.
  • the well implant mask may be the same mask used to form first polarity type wells in fin-type MOS processes.
  • the well may be lightly or intermediately doped with first polarity type dopants.
  • the well may be formed by ion implantation with dopant concentration of about 10 16 cm ⁇ 3 to 10 18 cm ⁇ 3 and includes a depth below the bottom of the isolation region 324 .
  • the process continues to form regions of second polarity type 306 a / 306 b in the fin structures 320 a / 320 b .
  • the regions 306 a / 306 b include lightly doped second polarity type dopants.
  • second polarity type dopants such as p-type dopants, are implanted into the fin structures.
  • the depth of the lightly doped regions may be about the height of the fin structures. Other suitable depth dimensions may also be useful, depending on technology node.
  • the dopant concentration may be about 10 16 cm ⁇ 3 to 10 18 cm ⁇ 3 . Other suitable dopant concentrations may also be useful.
  • An implant mask which exposes the fin structures may be provided to perform the implant.
  • the implant mask for example, may be a photoresist layer. Other suitable types of implant masks may also be useful.
  • the process continues to form a gate or dummy gate having dummy gate dielectric 916 and dummy gate electrode layer 914 .
  • the materials and techniques for forming the dummy gate structure is the same as that described in FIG. 5 b .
  • the dummy gate structure is formed in the opening 982 between the fin structures.
  • the dummy gate dielectric and dummy gate electrode layers are formed over the substrate as well as in the opening 982 and are patterned as shown in FIG. 9 c.
  • the regions of second polarity type 306 a / 306 b are BE regions.
  • the fin structures may not be lightly doped with second polarity type dopants as described earlier in FIG. 9 b .
  • the fin structures may be removed via suitable etch techniques and followed by, for example, selective epitaxial growth (SEG) process, filling the spaces or recesses.
  • SEG selective epitaxial growth
  • the BE regions 306 a / 306 b are SiGe BE regions as shown in FIG. 9 c .
  • the BE regions are lightly doped with second polarity type dopants. Other suitable types of BE regions may also be useful.
  • the BE regions 306 a / 306 b may be formed by epitaxially growing an epitaxial layer on a blanket or planar substrate and then etch the epitaxial layer to form the fin structures.
  • sidewall spacers 318 are formed over the first and second sidewalls of the dummy gate.
  • the materials and technique for forming the spacers 318 are the same as that described in FIG. 5 c.
  • the process continues to form the first and second thyristor structures.
  • the process continues to form elevated first and second layers of the first polarity type 308 a / 308 b over the first and second regions of the second polarity type 306 a / 306 b as shown in FIG. 9 e .
  • the materials and techniques for forming the elevated self-aligned first and second layers of the first polarity type 308 a / 308 b are the same as that described in FIG. 5 d .
  • Self-aligned first and second heavily doped second polarity type layers 310 a / 310 b are formed on the first and second layers of the first polarity type 308 a / 308 b .
  • the materials and techniques for forming the heavily doped second polarity type layers 310 a / 310 b are the same as that described in FIG. 5 e.
  • silicide contacts 312 may be formed on the heavily doped first and second layers of the second polarity type 310 a / 310 b .
  • An ILD layer 320 is formed over the substrate.
  • the silicide contacts 312 and ILD layer 320 and the techniques for forming these layers are the same as that described in FIGS. 5 f - 5 g .
  • a substantially coplanar surface between the top surface of the dummy gate, sidewall spacers 318 and ILD layer 320 is achieved.
  • the process may continue to form additional dielectric layer to form a pre-metal dielectric (PMD) layer in which contacts are formed to contact region of the substrate, followed by BEOL process.
  • PMD pre-metal dielectric
  • the dummy gate is removed.
  • the dummy gate is removed using techniques as described in FIG. 5 h .
  • the removal of the dummy gate forms an opening 987 which exposes top surface of the isolation region 324 as well as inner sides of the spacers 318 away from the ILD layer 320 and inner sides of the first and second regions of the second polarity type 306 a / 306 b.
  • the process continues by forming a high-k metal gate structure as shown in FIG. 9 g .
  • the high-k metal gate structure includes a gate dielectric 316 and a gate electrode 314 .
  • the materials and techniques for forming the high-k metal gate structure are the same as that described in FIG. 5 i.
  • the process may continue to complete the memory cell. For example, the process continues to form PMD layer, contacts 322 a / 322 b , etc., until a device shown in FIG. 9 h is formed.
  • the first contact 322 a is configured to be coupled to a first bit line of the device while the second contact 322 b is configured to be coupled to a second bit line of the device 300 .
  • Additional processes may be performed, including forming one or more interconnect levels, final passivation, dicing, assembly and packaging. Techniques and materials of these features are the same as that already described in FIG. 5 j . As such, details of these steps will not be described.
  • FIGS. 10 a - 10 d show cross-sectional views of an embodiment of a process 1000 for forming a device in accordance with another embodiment of the present disclosure.
  • the process 1000 forms the device 350 of FIG. 3 b .
  • the process 1000 of forming the device 350 is similar to the process 900 of forming the device 300 and may include similar steps described in FIGS. 5 a - 5 j , in the interest of brevity, the description below focuses on the differences between process 1000 and process 900 .
  • the process 1000 forms a fin structure or a region of the second polarity type 306 while the gate dielectric and electrode layers 1016 and 1014 of the dummy gate are patterned in such a way such that the dummy gate overlaps the STI region 374 and partially overlaps the region of the second polarity type over the substrate as shown in FIG. 10 a .
  • the region of the second polarity type 306 may include a BE region.
  • the process 1000 continues to form sidewall spacers 368 over the first and second gate sidewalls.
  • the sidewall spacers are formed using the same material and technique as already described in FIG. 5 c .
  • the first sidewall spacer adjacent to the first gate sidewall extends to the top surface of the region of the second polarity type 306 while the second sidewall spacer adjacent to the second gate sidewall extends to the top of the STI region 374 .
  • the process 1000 continues to form elevated layers of the first polarity type 308 and the heavily doped layer of the second polarity type 310 on the region of the second polarity type 306 and adjacent to a first side of the dummy gate as shown in FIG. 10 a .
  • Silicide contact 312 is formed over the heavily doped layer of the second polarity type 310 and an ILD layer 370 is formed over the substrate and is processed as shown in FIG. 10 b . Materials and techniques for forming these layers are the same as that described in FIGS. 9 e - 9 f.
  • the dummy gate structure is removed using techniques as described in FIG. 5 h .
  • Other suitable techniques may also be employed to remove the dummy gate.
  • the removal of the dummy gate forms an opening 1087 , exposing a portion of the top surface of the region of the second polarity type 306 and a portion of the top surface of the STI region 374 .
  • the process continues to form a high-k metal gate structure.
  • the high-k metal gate structure includes a gate dielectric 316 and a gate electrode 314 .
  • the materials and techniques for forming the high-k metal gate structure are the same as that described in FIG. 5 i .
  • the process may continue to complete the memory cell. For example, the process continues to form PMD layer, contact 322 , etc., until a device shown in FIG. 10 d is formed. Additional processes may be performed, including forming one or more interconnect levels, final passivation, dicing, assembly and packaging. Techniques and materials of these features are the same as that already described in FIG. 5 j . As such, details of these steps will not be described.
  • FIGS. 11 a - 11 f show cross-sectional views of an embodiment of a process 1100 for forming a device in accordance with yet another embodiment of the present disclosure.
  • the process 1100 forms the device 400 of FIG. 4 a .
  • the process 1100 may contain similar steps as that described in FIGS. 5 a - 5 j . In the interest of brevity, common elements may not be described or described in detail.
  • a substrate 402 is provided.
  • the substrate 402 is the same as the substrate as described in FIG. 5 a .
  • the substrate is lightly doped with second polarity type dopants.
  • the second polarity type dopants for example, include p-type dopants.
  • the substrate may include a plurality of device regions. Isolation regions (not shown) are formed in the substrate 402 .
  • the isolation region serves to isolate the cell region from other device regions (not shown) for other types of devices.
  • the isolation region for example, is a shallow trench isolation (STI) region. Other types of isolation regions may also be useful.
  • the STI regions may be formed using various suitable techniques.
  • the process continues to form a well 404 .
  • the well in one embodiment, includes first polarity type dopants. Dopant concentrations and techniques for forming the first polarity type well 404 are the same as that described in FIG. 5 a.
  • the process continues to form a buried isolation buffer layer 404 .
  • the isolation buffer is an amorphized portion of the substrate 402 .
  • the isolation buffer is an amorphized silicon ( ⁇ -Si) layer.
  • amorphizing dopants are implanted into the substrate.
  • the amorphizing dopants include silicon ions (Si+), germanium (Ge) or carbon (C) or a combination thereof.
  • amorphizing dopants such as Ar or O and dopants such as B, P or As implanted by molecular or cluster implants may also be used.
  • amorphizing dopants are implanted by, for example, high energy implantation (HEI).
  • HEI high energy implantation
  • the HEI implant is performed at, for example, 160 KeV with a dose of about 5e14-9e14 atom/cm 2 .
  • Providing other suitable implant energies and doses may also be useful.
  • Implanting the amorphizing ions by cold, molecular, or cluster implantation may also be useful. For example, lower energy requirements of molecular or cluster implantations may also be useful.
  • the implant parameters, such as energy and dose are tailored to produce isolation buffer layer at the desired location and have the desired effect. By adjusting the energy and dose of the implant, the location and thickness of the isolation buffer can be controlled. This also controls the thickness or height of the substrate surface.
  • an anneal may be performed after implanting the amorphizing dopants.
  • the anneal for example, includes laser anneal, rapid thermal anneal (RTA) or furnace anneal. Other suitable types of anneal technique may also be useful.
  • RTA rapid thermal anneal
  • amorphizing dopants may be activated during well or S/D region anneal process.
  • the top of the isolation buffer should have a depth sufficient to accommodate a body region of the transistor.
  • the top of the isolation buffer should be about 5-100 nm deep from the top surface of the substrate 402 .
  • the thickness of the isolation buffer should be sufficient to reduce substrate leakage. The thickness, for example, may be about 5-100 nm. Providing other suitable depths and thicknesses may also be useful.
  • the area of the substrate between the top surface of the isolation buffer layer or first polarity type well 404 , the isolation regions (not shown) and substrate top surface serves as a body region or floating body of a second polarity type 406 of the T-RAM.
  • the body region may be part of the substrate and thus having the same doping as the substrate.
  • the body region is a lightly doped second polarity type region 406 .
  • An implantation process may optionally be performed to introduce the second polarity type dopants into the body region.
  • the dopant concentration of the second polarity type for example, is about 10 16 cm ⁇ 3 to 10 18 cm ⁇ 3 . Other suitable dopant concentration may also be useful.
  • the body region 406 may not be part of the substrate. In such case, the process continues to form a BE body region 406 over the first polarity well or isolation buffer layer 404 .
  • the BE body region 406 in one embodiment, is a SiGe, Si:C or Ge BE body region. Other suitable types of BE materials may also be useful.
  • the BE body region 406 is formed by an epitaxial process.
  • the epitaxial BE body for example, is lightly doped with second polarity type dopants.
  • the epitaxial BE body for example, may be in-situ doped with second polarity type dopants. Other suitable techniques for forming the BE body may also be useful.
  • the process continues to form a gate or dummy gate having a dummy gate dielectric 1116 and dummy gate electrode 1114 as shown in FIG. 11 b .
  • the materials and techniques for forming the dummy gate are the same as that described in FIG. 5 b.
  • the process continues to form regions of first polarity type 408 a in the substrate adjacent to first and second sides of the dummy gate as shown in FIG. 11 c .
  • the regions 408 a includes lightly doped first polarity type dopants.
  • An implant mask which exposes the device region may be provided to perform the implant. Dopant concentrations of the regions of first polarity type 408 a adjacent to the first and second sides of the dummy gate are the same as that described in FIG. 5 d.
  • the process continues to form a self-aligned elevated heavily doped second polarity type layer 410 on the region of the first polarity type 408 a adjacent to the first side of the gate.
  • the material and technique for forming the elevated heavily doped second polarity type layer 410 are the same as that described in FIG. 5 e.
  • silicide contacts 412 a / 412 b may be formed on the heavily doped layer and region of the first and second polarity types 408 b and 410 .
  • An ILD layer (not shown) may be formed over the substrate.
  • the silicide contacts 412 a / 412 b and ILD layer and the techniques for forming these layers are the same as that described in FIGS. 5 f - 5 g .
  • a substantially coplanar surface between the top surface of the dummy gate, sidewall spacers 418 and ILD layer is achieved.
  • the process may continue to form additional dielectric layer to form a pre-metal dielectric (PMD) layer in which contacts are formed to contact regions of the substrate, followed by BEOL process.
  • the process proceeds to remove the dummy gate.
  • the dummy gate is removed using techniques as described in FIG. 5 h .
  • the removal of the dummy gate forms an opening (not shown) which exposes top surface of the body region of first polarity type 406 under the dummy gate as well as inner sides of the spacers 418 away from the ILD layer (not shown).
  • the process may continue to complete the memory cell. For example, the process continues to form PMD layer 420 , contacts 422 a / 422 b , etc., until a device shown in FIG. 11 f is formed.
  • the first contact 422 a is configured to be coupled to a bit line of the device while the second contact 422 b is configured to be coupled to a first word line of the device and the gate is configured to function as a second word line of the device.
  • Additional processes may be performed, including forming one or more interconnect levels, final passivation, dicing, assembly and packaging. Techniques and materials of these features are the same as that already described in FIG. 5 j . As such, details of these steps will not be described.
  • FIGS. 11 a - 11 f results in similar advantages as that described in FIGS. 5 a - 5 j .
  • the substrate 402 includes a region of amorphous silicon instead of a well of the first polarity type
  • the region of amorphous silicon replaces the need for a buried oxide layer in the substrate 402 .
  • This helps achieve floating body second polarity type base, such as p-type base, and eliminates high cost associated with producing silicon-on-insulator.
  • self-aligned heavily doped second polarity layer removes the need for silicide block layer.
  • FIGS. 12 a - 12 c show cross-sectional views of an embodiment of a process 1200 for forming a device in accordance with yet another embodiment of the present disclosure.
  • the process 1200 forms the device 430 of FIG. 4 b .
  • the process of forming the memory device 430 is similar to that of forming the device 400 , in the interest of brevity, the description below focuses on the differences between process 1200 and process 1100 .
  • the partially processed substrate is processed up to the body region 406 having second polarity type dopants.
  • the body region 406 is part of the substrate 402 and includes lightly doped second polarity type dopants.
  • the body region 406 includes BE region.
  • the process continues to form a gate or dummy gate having a dummy gate dielectric 1216 and dummy gate electrode 1214 as shown in FIG. 12 a .
  • the materials and techniques for forming the dummy gate are the same as that described in FIG. 5 b.
  • the process continues to form heavily doped region of the first polarity type 408 adjacent to the second side of the gate as shown in FIG. 12 a .
  • An implant mask which exposes the region adjacent to the second side of the gate may be provided to perform the implant.
  • the dopant concentration of the heavily doped region of the first polarity type 408 and the technique for forming thereof are the same as the heavily doped region of the first polarity type 408 b described in FIG. 11 c.
  • sidewall spacers 418 are formed over the first and second sidewalls of the dummy gate.
  • the materials and technique for forming the spacers 418 are the same as that described in FIG. 5 c.
  • the process 1200 forms an elevated layer of the first polarity type 438 over the body region 406 of the second polarity type adjacent to the first side of the gate.
  • the material and technique for forming the elevated layer of the first polarity type 438 is the same as the elevated layer of the first polarity type 108 a described in FIG. 5 d .
  • the process 1200 also forms an elevated heavily doped layer of the second polarity type 410 on the layer of the first polarity type 438 adjacent to the first side of the gate using technique as described in FIG. 5 e.
  • silicide contacts 412 a / 412 b may be formed on the heavily doped layer and region of the first and second polarity types 408 and 410 .
  • An ILD layer (not shown) may be formed over the substrate.
  • the silicide contacts 412 a / 412 b and ILD layer and the techniques for forming these layers are the same as that described in FIGS. 5 f - 5 g .
  • a substantially coplanar surface between the top surface of the dummy gate, sidewall spacers 418 and ILD layer is achieved.
  • the high-k metal gate structure includes a gate dielectric 416 and a gate electrode 414 .
  • the materials and techniques for forming the high-k metal gate structure are the same as that described in FIG. 5 i.
  • the process may continue to complete the memory cell. For example, the process continues to form PMD layer 420 , contacts 422 a / 422 b , etc., until a device shown in FIG. 12 c is formed.
  • the first contact 422 a is configured to be coupled to a bit line of the device while the second contact 422 b is configured to be coupled to a first word line of the device and the gate is configured to function as a second word line of the device.
  • Additional processes may be performed, including forming one or more interconnect levels, final passivation, dicing, assembly and packaging. Techniques and materials of these features are the same as that already described in FIG. 5 j . As such, details of these steps will not be described.
  • FIGS. 13 a - 13 e show cross-sectional views of an embodiment of a process 1300 for forming a device in accordance with yet another embodiment of the present disclosure.
  • the process 1300 forms the device 450 of FIG. 4 c .
  • the process of forming the device 450 is similar to that of forming the device 400 , in the interest of brevity, the description below focuses on the differences between process 1300 and process 1100 .
  • a partially processed substrate similar to that described in FIG. 11 e is provided.
  • the partially processed substrate is processed up to forming an ILD layer 420 covering the dummy gate and silicide contacts 412 a / 412 b and is processed such that a substantially coplanar surface between the top surface of the dummy gate, sidewall spacers 418 and ILD layer is achieved.
  • the dummy gate is removed using techniques as described in FIG. 5 h .
  • Other suitable techniques may also be employed to remove the dummy gate.
  • the removal of the dummy gate exposes a portion of top surface of the body region of the second polarity type 406 under the dummy gate.
  • the process continues to form a trench or recessed channel 1263 within a portion of the body region 406 in between the region of first polarity type 408 a and the heavily doped region of first polarity type 408 b .
  • a mask and etch process is employed to remove portions of the body region 406 to form the trench 1263 .
  • the trench is formed by RIE.
  • the sides of the trench are self-aligned to the inner sides of the spacers 418 .
  • the depth of the trench is about equal to the depth of the regions of first polarity type 408 a / 408 b . Providing other depths or configurations may also be useful.
  • a band engineered (BE) portion 455 is formed within the trench 1263 .
  • the BE portion is formed by, for example, selective epitaxial growth (SEG) process, filling the spaces within the recessed channel.
  • the top of the BE portion is about coplanar with the top of the substrate surface.
  • the top of BE portion is also substantially coplanar with the top surface of the regions of first polarity type 408 a / 408 b .
  • Forming the BE portion which is slightly recessed or over the substrate surface or the top surface of the regions of first polarity type may also be useful.
  • the BE portion in one embodiment, is a silicon germanium (SiGe) BE portion. Other suitable types of BE portion may also be useful.
  • the process continues to form a high-k metal gate structure.
  • the materials and techniques for forming the high-k metal gate structure is the same as that described in FIG. 5 i .
  • the process may continue to complete the memory cell. For example, the process continues to form PMD layer, contacts 422 a / 422 b , etc., until a device shown in FIG. 13 e is formed. Additional processes may be performed, including forming one or more interconnect levels, final passivation, dicing, assembly and packaging. Techniques and materials of these features are the same as that already described in FIG. 5 j . As such, details of these steps will not be described.
  • FIGS. 14 a - 14 b show cross-sectional views of an embodiment of a process 1400 for forming a device in accordance with yet another embodiment of the present disclosure.
  • the process 1400 forms the device 470 of FIG. 4 d .
  • the process of forming the device 470 is similar to that of forming the device 430 , in the interest of brevity, the description below focuses on the differences between process 1400 and process 1200 .
  • a partially processed substrate similar to that described in FIG. 12 b is provided.
  • the partially processed substrate is processed up to forming an ILD layer 420 covering the dummy gate and silicide contacts 412 a / 412 b and is processed such that a substantially coplanar surface between the top surface of the dummy gate, sidewall spacers 418 and ILD layer is achieved.
  • the dummy gate structure is removed using techniques as described in FIG. 5 h .
  • Other suitable techniques may also be employed to remove the dummy gate.
  • the removal of the dummy gate exposes a portion of top surface of the body region of the second polarity type 406 under the dummy gate.
  • the process continues to form a trench or recessed channel 1463 within a portion of the body region 406 adjacent to the heavily doped region of first polarity type 408 and below the dummy gate.
  • a mask and etch process is employed to remove portions of the body region 406 to form the trench 1463 .
  • the trench is formed by RIE.
  • the sides of the trench for example, are self-aligned to the inner sides of the spacers 418 .
  • the depth of the trench is about equal to the depth of the heavily doped region of first polarity type 408 . Providing other depths or configurations may also be useful.
  • the process continues to form BE portion 455 within the trench 1463 , a high-k metal gate structure and proceed to complete the memory cell.
  • the process steps include those described from FIG. 13 c and onwards and continue until the device 470 shown in FIG. 4 d is formed. Additional processes may be performed, including forming one or more interconnect levels, final passivation, dicing, assembly and packaging. Techniques and materials of these features are the same as that already described in FIG. 5 j . As such, details of these steps will not be described.

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DE102015206391A1 (de) 2015-12-03
KR20150130945A (ko) 2015-11-24
CN105097808A (zh) 2015-11-25
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DE102015206391B4 (de) 2016-09-22
TW201606989A (zh) 2016-02-16

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