US20140242766A1 - Method for manufacturing semiconductor device and semiconductor device - Google Patents

Method for manufacturing semiconductor device and semiconductor device Download PDF

Info

Publication number
US20140242766A1
US20140242766A1 US14/272,944 US201414272944A US2014242766A1 US 20140242766 A1 US20140242766 A1 US 20140242766A1 US 201414272944 A US201414272944 A US 201414272944A US 2014242766 A1 US2014242766 A1 US 2014242766A1
Authority
US
United States
Prior art keywords
silicon layer
shaped silicon
fin
insulating film
polysilicon gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US14/272,944
Inventor
Fujio Masuoka
Hiroki Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisantis Electronics Singapore Pte Ltd
Original Assignee
Unisantis Electronics Singapore Pte Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Unisantis Electronics Singapore Pte Ltd filed Critical Unisantis Electronics Singapore Pte Ltd
Priority to US14/272,944 priority Critical patent/US20140242766A1/en
Publication of US20140242766A1 publication Critical patent/US20140242766A1/en
Priority to US15/221,077 priority patent/US10438836B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a method for manufacturing a semiconductor device and to a semiconductor device.
  • SGT surrounding gate transistors
  • a metal for a gate electrode instead of using polysilicon, depletion can be suppressed, and the resistance of the gate electrode can be decreased.
  • a manufacturing process after a metal gate is formed must be one in which metal contamination by the metal gate is always taken into consideration.
  • a metal gate last process is used for actual products, in which a metal gate is formed after a high-temperature process (IEDM 2007 K. Mistry, et. al., pp. 247-250).
  • the gate is formed using polysilicon, and then an interlayer insulating film is deposited. Then, the polysilicon gate is exposed by chemical mechanical polishing and etched, followed by deposition of a metal. Therefore, in order to satisfy both the metal gate process and the high-temperature process, the metal gate last process must be used for SGT, in which a metal gate is formed after the high-temperature process. Since, in the SGT, the upper surface of the pillar-shaped silicon layer is higher than the gate, some consideration is required for using the metal gate last process.
  • MOS transistors use a first insulating film in order to decrease a parasitic capacitance between gate wiring and a substrate.
  • a first insulating film is formed around a fin-shaped semiconductor layer and then etched back to expose the fin-shaped semiconductor layer, thereby decreasing the parasitic capacitance between the gate wiring and the substrate.
  • the first insulating film must be used for decreasing the parasitic capacitance between the gate wiring and the substrate.
  • the SGT includes the pillar-shaped semiconductor layer in addition to the fin-shaped semiconductor layer, and thus some consideration is required for forming the pillar-shaped semiconductor layer.
  • an object is to decrease a parasitic capacitance between a gate wiring and a substrate, provide a SGT manufacturing method using a gate last process, and provide a resulting SGT structure.
  • a method for manufacturing a semiconductor device of the present invention includes:
  • the manufacturing method is also characterized in that a first resist is formed for forming the fin-shaped silicon layer on the silicon substrate; the silicon substrate is etched to form the fin-shaped silicon layer and the first resist is removed; the first insulating film is deposited around the fin-shaped silicon layer and then etched back to expose an upper portion of the fin-shaped silicon layer; a second resist is formed to be perpendicular to the fin-shaped silicon layer; the fin-shaped silicon layer is etched; and then the second resist is removed to form the pillar-shaped silicon layer so that a portion where the fin-shaped silicon layer and the second resist intersect at right angles becomes the pillar-shaped silicon layer.
  • the manufacturing method is further characterized in that in a structure including the fin-shaped silicon layer formed on the silicon substrate, the first insulating film formed around the fin-shaped silicon layer, and the pillar-shaped silicon layer formed on the fin-shaped silicon layer, a second oxide film is deposited, a first nitride film is formed on the second oxide film, the first nitride film is etched to be left as a side wall, the diffusion layers are formed by impurity implantation in an upper portion of the pillar-shaped silicon layer and an upper portion of the fin-shaped silicon layer, and the first nitride film and the second oxide film are removed, followed by heat treatment.
  • the manufacturing method is further characterized in that in a structure including the fin-shaped silicon layer formed on the silicon substrate, the first insulating film formed around the fin-shaped silicon layer, the pillar-shaped silicon layer formed on the fin-shaped silicon layer, the diffusion layer formed in the upper portion of the fin-shaped silicon layer and in the lower portion of the pillar-shaped silicon layer, and the diffusion layer formed in the upper portion of the pillar-shaped silicon layer, the gate insulating film is formed, polysilicon is deposited and then planarized so that after planarization, the upper surface of the polysilicon is higher than the gate insulating film on the diffusion layer formed in the upper portion of the pillar-shaped silicon layer, a second nitride film is deposited, a third resist is formed for forming the polysilicon gate electrode and the polysilicon gate wiring, the second nitride film is etched, the polysilicon is etched to form the polysilicon gate electrode and the polysilicon gate wiring, the gate insulating film is etched, and the third resist is removed.
  • the manufacturing method is further characterized in that a third nitride film is deposited and then etched to be left as a side wall, and a metal is deposited to form a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer.
  • the manufacturing method is further characterized in that a fourth nitride film is deposited, the interlayer insulating film is deposited and then planarized, the polysilicon gate electrode and the polysilicon gate wiring are exposed, the polysilicon gate electrode and the polysilicon gate wiring are removed, a metal is filled in a portion from which the polysilicon gate electrode and the polysilicon gate wiring have been removed, and the metal is etched to expose the gate insulating film on the diffusion layer in the upper portion of the pillar-shaped silicon layer, thereby forming the metal gate electrode and the metal gate wiring.
  • a semiconductor device of the present invention includes: a fin-shaped silicon layer formed on a silicon substrate; a first insulating film formed around the fin-shaped silicon layer; a pillar-shaped silicon layer formed on the fin-shaped silicon layer, the width of the pillar-shaped silicon layer being equal to the width of the fin-shaped silicon layer; a diffusion layer formed in an upper portion of the fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer; a diffusion layer formed in an upper portion of the pillar-shaped silicon layer; a silicide formed in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; a gate insulating film formed around the pillar-shaped silicon layer; a metal gate electrode formed around the gate insulating film: a metal gate wiring connected to the metal gate electrode and extending in a direction perpendicular to the fin-shaped silicon layer; and a contact formed on the diffusion layer formed in the upper portion of the pillar-shaped silicon layer so as to make direct contact between the contact and the diffusion layer formed in the upper portion
  • the present invention it is possible to decrease a parasitic capacitance between a gate wiring and a substrate, provide a SGT manufacturing method using a gate last process, and provide a resulting SGT structure.
  • the fin-shaped silicon layer, the first insulating film, and the pillar-shaped silicon layer are formed based on a conventional FINFET manufacturing method and thus can be easily formed.
  • a silicide is generally formed in an upper portion of the pillar-shaped silicon layer, but the silicide must be formed after a polysilicon gate is formed because the deposition temperature of polysilicon is higher than the silicide formation temperature.
  • the silicide when the silicide is formed in an upper portion of a silicon column, a hole is formed on a polysilicon gate electrode after the polysilicon gate is formed, the silicide is formed after a side wall composed of an insulating film is formed on the side wall of the hole, and then the hole is filled with an insulating film, thereby causing the problem of increasing the number of manufacturing steps. Therefore, the diffusion layers are formed before the polysilicon gate electrode and the polysilicon gate wiring are formed, the pillar-shaped silicon layer is covered with the polysilicon gate electrode, and the silicide is formed only in an upper portion of the fin-shaped silicon layer.
  • a usual metal gate last manufacturing method in which a gate is formed using polysilicon, the interlayer insulating film is deposited, the polysilicon gate is exposed by chemical mechanical polishing and then etched, and then a metal is deposited, thereby facilitating the formation of metal gate SGT.
  • FIG. 1( a ) is a plan view of a semiconductor device according to the present invention
  • FIG. 1( b ) is a sectional view taken along line X-X′ in FIG. 1( a )
  • FIG. 1( c ) is a sectional view taken along line Y-Y′ in FIG. 1( a ).
  • FIG. 2( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 2( b ) is a sectional view taken along line X-X′ in FIG. 2( a )
  • FIG. 2( c ) is a sectional view taken along line Y-Y′ in FIG. 2( a ).
  • FIG. 3( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 3( b ) is a sectional view taken along line X-X′ in FIG. 3( a )
  • FIG. 3( c ) is a sectional view taken along line Y-Y′ in FIG. 3( a ).
  • FIG. 4( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 4( b ) is a sectional view taken along line X-X′ in FIG. 4( a )
  • FIG. 4( c ) is a sectional view taken along line Y-Y′ in FIG. 4( a ).
  • FIG. 5( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 5( b ) is a sectional view taken along line X-X′ in FIG. 5( a )
  • FIG. 5( c ) is a sectional view taken along line Y-Y′ in FIG. 5( a ).
  • FIG. 6( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 6( b ) is a sectional view taken along line X-X′ in FIG. 6( a )
  • FIG. 6( c ) is a sectional view taken along line Y-Y′ in FIG. 6( a ).
  • FIG. 7( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 7( b ) is a sectional view taken along line X-X′ in FIG. 7( a )
  • FIG. 7( c ) is a sectional view taken along line Y-Y′ in FIG. 7( a ).
  • FIG. 8( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 8( b ) is a sectional view taken along line X-X′ in FIG. 8( a )
  • FIG. 8( c ) is a sectional view taken along line Y-Y′ in FIG. 8( a ).
  • FIG. 9( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 9( b ) is a sectional view taken along line X-X′ in FIG. 9( a )
  • FIG. 9( c ) is a sectional view taken along line Y-Y′ in FIG. 9( a ).
  • FIG. 10( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 10( b ) is a sectional view taken along line X-X′ in FIG. 10( a )
  • FIG. 10( c ) is a sectional view taken along line Y-Y′ in FIG. 10( a ).
  • FIG. 11( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 11( b ) is a sectional view taken along line X-X′ in FIG. 11( a )
  • FIG. 11( c ) is a sectional view taken along line Y-Y′ in FIG. 11( a ).
  • FIG. 12( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 12( b ) is a sectional view taken along line X-X′ in FIG. 12( a )
  • FIG. 12( c ) is a sectional view taken along line Y-Y′ in FIG. 12( a ).
  • FIG. 13( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 13( b ) is a sectional view taken along line X-X′ in FIG. 13( a )
  • FIG. 13( c ) is a sectional view taken along line Y-Y′ in FIG. 13( a ).
  • FIG. 14( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 14( b ) is a sectional view taken along line X-X′ in FIG. 14( a )
  • FIG. 14( c ) is a sectional view taken along line Y-Y′ in FIG. 14( a ).
  • FIG. 15( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 15( b ) is a sectional view taken along line X-X′ in FIG. 15( a )
  • FIG. 15( c ) is a sectional view taken along line Y-Y′ in FIG. 15( a ).
  • FIG. 16( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 16( b ) is a sectional view taken along line X-X′ in FIG. 16( a )
  • FIG. 16( c ) is a sectional view taken along line Y-Y′ in FIG. 16( a ).
  • FIG. 17( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 17( b ) is a sectional view taken along line X-X′ in FIG. 17( a )
  • FIG. 17( c ) is a sectional view taken along line Y-Y′ in FIG. 17( a ).
  • FIG. 18( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 18( b ) is a sectional view taken along line X-X′ in FIG. 18( a )
  • FIG. 18( c ) is a sectional view taken along line Y-Y′ in FIG. 18( a ).
  • FIG. 19( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 19( b ) is a sectional view taken along line X-X′ in FIG. 19( a )
  • FIG. 19( c ) is a sectional view taken along line Y-Y′ in FIG. 19( a ).
  • FIG. 20( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 20( b ) is a sectional view taken along line X-X′ in FIG. 20( a )
  • FIG. 20( c ) is a sectional view taken along line Y-Y′ in FIG. 20( a ).
  • FIG. 21( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 21( b ) is a sectional view taken along line X-X′ in FIG. 21( a )
  • FIG. 21( c ) is a sectional view taken along line Y-Y′ in FIG. 21( a ).
  • FIG. 22( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 22( b ) is a sectional view taken along line X-X′ in FIG. 22( a )
  • FIG. 22( c ) is a sectional view taken along line Y-Y′ in FIG. 22( a ).
  • FIG. 23( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 23( b ) is a sectional view taken along line X-X′ in FIG. 23( a )
  • FIG. 23( c ) is a sectional view taken along line Y-Y′ in FIG. 23( a ).
  • FIG. 24( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 24( b ) is a sectional view taken along line X-X′ in FIG. 24( a )
  • FIG. 24( c ) is a sectional view taken along line Y-Y′ in FIG. 24( a ).
  • FIG. 25( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 25( b ) is a sectional view taken along line X-X′ in FIG. 25( a )
  • FIG. 25( c ) is a sectional view taken along line Y-Y′ in FIG. 25( a ).
  • FIG. 26( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 26( b ) is a sectional view taken along line X-X′ in FIG. 26( a )
  • FIG. 26( c ) is a sectional view taken along line Y-Y′ in FIG. 26( a ).
  • FIG. 27( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 27( b ) is a sectional view taken along line X-X′ in FIG. 27( a )
  • FIG. 27( c ) is a sectional view taken along line Y-Y′ in FIG. 27( a ).
  • FIG. 28( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 28( b ) is a sectional view taken along line X-X′ in FIG. 28( a )
  • FIG. 28( c ) is a sectional view taken along line Y-Y′ in FIG. 28( a ).
  • FIG. 29( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 29( b ) is a sectional view taken along line X-X′ in FIG. 29( a )
  • FIG. 29( c ) is a sectional view taken along line Y-Y′ in FIG. 29( a ).
  • FIG. 30( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 30( b ) is a sectional view taken along line X-X′ in FIG. 30( a )
  • FIG. 30( c ) is a sectional view taken along line Y-Y′ in FIG. 30( a ).
  • FIG. 31( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 31( b ) is a sectional view taken along line X-X′ in FIG. 31( a )
  • FIG. 31( c ) is a sectional view taken along line Y-Y′ in FIG. 31( a ).
  • FIG. 32( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 32( b ) is a sectional view taken along line X-X′ in FIG. 32( a )
  • FIG. 32( c ) is a sectional view taken along line Y-Y′ in FIG. 32( a ).
  • FIG. 33( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 33( b ) is a sectional view taken along line X-X′ in FIG. 33( a )
  • FIG. 33( c ) is a sectional view taken along line Y-Y′ in FIG. 33( a ).
  • FIG. 34( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 34( b ) is a sectional view taken along line X-X′ in FIG. 34( a )
  • FIG. 34( c ) is a sectional view taken along line Y-Y′ in FIG. 34( a ).
  • FIG. 35( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 35( b ) is a sectional view taken along line X-X′ in FIG. 35( a )
  • FIG. 35( c ) is a sectional view taken along line Y-Y′ in FIG. 35( a ).
  • FIG. 36( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 36( b ) is a sectional view taken along line X-X′ in FIG. 36( a )
  • FIG. 36( c ) is a sectional view taken along line Y-Y′ in FIG. 36( a ).
  • FIG. 37( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 37( b ) is a sectional view taken along line X-X′ in FIG. 37( a )
  • FIG. 37( c ) is a sectional view taken along line Y-Y′ in FIG. 37( a ).
  • FIG. 38( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 38( b ) is a sectional view taken along line X-X′ in FIG. 38( a )
  • FIG. 38( c ) is a sectional view taken along line Y-Y′ in FIG. 38( a ).
  • FIG. 39( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 39( b ) is a sectional view taken along line X-X′ in FIG. 39( a )
  • FIG. 39( c ) is a sectional view taken along line Y-Y′ in FIG. 39( a ).
  • FIG. 40( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 40( b ) is a sectional view taken along line X-X′ in FIG. 40( a )
  • FIG. 40( c ) is a sectional view taken along line Y-Y′ in FIG. 40( a ).
  • FIG. 41( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 41( b ) is a sectional view taken along line X-X′ in FIG. 41( a )
  • FIG. 41( c ) is a sectional view taken along line Y-Y′ in FIG. 41( a ).
  • FIG. 42( a ) is a plan view of a method for manufacturing a semiconductor device according to the present invention
  • FIG. 42( b ) is a sectional view taken along line X-X′ in FIG. 42( a )
  • FIG. 42( c ) is a sectional view taken along line Y-Y′ in FIG. 42( a ).
  • a manufacturing process for forming a SGT structure according to an embodiment of the present invention is described below with reference to FIGS. 2 to 42 .
  • a manufacturing method for forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer is described.
  • a first resist 102 is formed for forming a fin-shaped silicon layer on a silicon substrate 101 .
  • the silicon substrate 101 is etched to form a fin-shaped silicon layer 103 .
  • the fin-shaped silicon layer is formed using the resist as a mask, a hard mask such as an oxide film or a nitride film may be used.
  • the first resist 102 is removed.
  • a first insulating film 104 is deposited around the fin-shaped silicon layer 103 .
  • an oxide film formed by high-density plasma, or an oxide film formed by low-pressure chemical vapor deposition may be used.
  • the first insulating film 104 is etched back to expose an upper portion of the fin-shaped silicon layer 103 .
  • the steps up to this step are the same as in the method for forming a fin-shaped silicon layer of Japanese Unexamined Patent Application Publication No. 2-188966.
  • a second resist 105 is formed so as to be perpendicular to the fin-shaped silicon layer 103 .
  • the fin-shaped silicon layer 103 is etched. A portion where the fin-shaped silicon layer 103 and the second resist 105 intersect at right angles becomes the pillar-shaped silicon layer 106 . Therefore, the width of the pillar-shaped silicon layer 106 is equal to the width of the fin-shaped silicon layer. As a result, a structure is formed, in which the pillar-shaped silicon layer 106 is formed in an upper portion of the fin-shaped silicon layer 103 , and the first insulating film 104 is formed around the fin-shaped silicon layer 103 .
  • the second resist 105 is removed.
  • a second oxide film 107 is deposited, and a first nitride film 108 is formed. Since an upper portion of the pillar-shaped silicon layer is subsequently covered with a gate insulating film and a polysilicon gate electrode, a diffusion layer is formed in an upper portion of the pillar-shaped silicon layer before covering of the pillar-shaped silicon layer.
  • the first nitride film 108 is etched to be left as a wide wall.
  • impurities such as arsenic, phosphorus, or boron are implanted to form a diffusion layer 110 in an upper portion of the pillar-shaped silicon layer, and diffusion layers 109 and 111 in an upper portion of the fin-shaped silicon layer 103 .
  • the first nitride film 108 and the second oxide film 107 are removed.
  • heat treatment is performed.
  • the diffusion layers 109 and 111 in an upper portion of the fin-shaped silicon layer 103 are brought into contact with each other to form a diffusion layer 112 .
  • the diffusion layers 110 and 112 are formed by impurity implantation in an upper portion of the pillar-shaped silicon layer and in an upper portion of the fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer.
  • an interlayer insulating film is deposited, and then the polysilicon gate electrode and the polysilicon gate wiring are exposed by chemical mechanical polishing. Therefore, it is necessary to prevent an upper portion of the pillar-shaped silicon layer from being exposed by chemical mechanical polishing.
  • a gate insulating film 113 is formed, and polysilicon 114 is deposited and then planarized. After planarization, the upper surface of the polysilicon is higher than the gate insulating film 113 disposed on the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106 .
  • the polysilicon gate electrode and the polysilicon gate wiring are exposed by chemical mechanical polishing after the interlayer insulating film is deposited, the upper portion of the pillar-shaped silicon layer is not exposed by chemical mechanical polishing.
  • a second nitride film 115 is deposited.
  • the second nitride film is one which inhibits the formation of silicide in upper portions of the polysilicon gate electrode and the polysilicon gate wiring when the silicide is formed in an upper portion of the fin-shaped silicon layer.
  • a third resist 116 is formed for forming the polysilicon gate electrode and the polysilicon gate wiring.
  • a portion corresponding to gate wiring is preferably perpendicular to the fin-shaped silicon layer 103 . This is because a parasitic capacitance between the gate wiring and the substrate is decreased.
  • the second nitride film 115 is etched.
  • the polysilicon 114 is etched to form a polysilicon gate electrode 114 a and a polysilicon gate wiring 114 b.
  • the gate insulating film 113 is etched.
  • the third resist 116 is removed.
  • the manufacturing method for forming the polysilicon gate electrode and the polysilicon gate wiring using polysilicon in order to use the gate-last process is described above. After the polysilicon gate electrode 114 a and the polysilicon gate wiring 114 b are formed, the upper surface of polysilicon is higher than the gate insulating film 113 on the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106 .
  • a manufacturing method for forming a silicide in an upper portion of the fin-shaped silicon layer is described.
  • the silicide is not formed in upper portions of the polysilicon gate electrode 114 a and the polysilicon gate wiring 114 b and in the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106 .
  • the manufacturing process is enlarged.
  • a third nitride film 117 is deposited.
  • the third nitride film 117 is etched to be left as a side wall.
  • a metal such as nickel or cobalt is deposited to form silicide 118 in an upper portion of the diffusion layer 112 formed in an upper portion of the fin-shaped silicon layer 103 .
  • the polysilicon gate electrode 114 a and the polysilicon gate wiring 114 b are covered with the third nitride film 117 and the second nitride film 115 , and the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106 is covered with the gate insulating film 113 , the polysilicon gate electrode 114 a, and the polysilicon gate wiring 114 b, and thus silicide is not formed in the polysilicon gate electrode 114 a, the polysilicon gate wiring 114 b, and the diffusion layer 110 .
  • the manufacturing method for forming a silicide in an upper portion of the fin-shaped silicon layer is described above.
  • a gate-last manufacturing method in which the polysilicon gate electrode and the polysilicon wiring are exposed by chemical mechanical polishing after an interlayer insulting film is deposited, the polysilicon gate electrode and the polysilicon wiring are etched, and then a metal is deposited.
  • a fourth nitride film 140 is deposited for protecting the silicide 118 .
  • an interlayer insulating film 119 is deposited and then planarized by chemical mechanical polishing.
  • the polysilicon gate electrode 114 a and the polysilicon gate wiring 114 b are exposed by chemical mechanical polishing.
  • the polysilicon gate electrode 114 a and the polysilicon gate wiring 114 b are etched. Wet etching is preferred.
  • a metal 120 is deposited and then planarized to fill, with the metal 120 , a portion from which the polysilicon gate electrode 114 a and the polysilicon gate wiring 114 b have been removed.
  • Atomic layer deposition is preferably used.
  • the metal 120 is etched to expose the gate insulating film 113 formed on the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106 . Consequently, a metal gate electrode 120 a and a metal gate wiring 120 b are formed.
  • the gate-last manufacturing method is described above, in which after the interlayer insulating film is deposited, the polysilicon gate is exposed by chemical mechanical polishing, the polysilicon gate is etched, and then a metal is deposited.
  • a manufacturing method for forming a contact is described. Since a silicide is not formed in the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106 , a contact is brought into direct contact with the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106 . As shown in FIG. 30 , an interlayer insulating film 121 is deposited and then planarized.
  • a fourth resist 122 is formed for forming a contact hole on the pillar-shaped silicon layer 106 .
  • the interlayer insulating film 121 is etched to form a contact hole 123 .
  • the fourth resist 122 is removed.
  • a fifth resist 124 is formed for forming contact holes on the metal gate wiring 120 b and on the fin-shaped silicon layer 103 .
  • the interlayer insulating films 121 and 119 are etched to form contact holes 125 and 126 .
  • the fifth resist 124 is removed.
  • the nitride film 140 and the gate insulating film 113 is etched to expose the silicide 118 and the diffusion layer 110 .
  • a metal is deposited to form contacts 143 , 127 , and 128 .
  • the manufacturing method for forming contacts is described above. Since a silicide is not formed in the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106 , the contact 127 is brought into direct contact with the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106 .
  • a metal 129 is deposited.
  • sixth resists 130 , 131 , and 132 are formed for forming the metal wiring.
  • the metal 129 is etched to metal wirings 133 , 134 , and 135 .
  • the sixth resists 130 , 131 , and 132 are removed.
  • FIG. 1 The result of the above-described manufacturing method is shown in FIG. 1 .
  • the resulting structure includes: the fin-shaped silicon layer 103 formed on the substrate 101 ; the first insulating film 104 formed around the fin-shaped silicon layer 103 ; the pillar-shaped silicon layer 106 formed on the fin-shaped silicon layer 103 , the width of the pillar-shaped silicon layer 106 being equal to the width of the fin-shaped silicon layer 103 ; the diffusion layer 112 formed in an upper portion of the fin-shaped silicon layer 103 and a lower portion of the pillar-shaped silicon layer 106 ; the diffusion layer 110 formed in an upper portion of the pillar-shaped silicon layer 106 ; the silicide 118 formed in an upper portion of the diffusion layer 112 in an upper portion of the fin-shaped silicon layer 103 ; the gate insulating film 113 formed around the pillar-shaped silicon layer 106 ; the metal gate electrode 120 a formed around the gate insulating film; the metal gate wiring 120 b connected to the metal gate electrode 120 a and extending in a direction perpendicular to the fin-shaped silicon layer 103 ;

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A manufacturing method includes forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer; forming diffusion layers in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer; forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring; forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring; and forming a contact.

Description

    RELATED APPLICATIONS
  • Pursuant to 35 U.S.C. §119(e), this application is a continuation application of U.S. application Ser. No. 13/666,445, filed Nov. 1, 2012 and claims the benefit of the filing date of Provisional U.S. Patent Application Ser. No. 61/557,501 filed on Nov. 9, 2011. The entire contents of which are hereby incorporated by reference.
    • BACKGROUND
  • 1. Technical Field
  • The present invention relates to a method for manufacturing a semiconductor device and to a semiconductor device.
  • 2. Description of the Related Art
  • Semiconductor integrated circuits, particularly integrated circuits using MOS transistors, are increasing in integration. With increases in integration, MOS transistors used in the integrated circuits are increasingly made finer up to a nano region. Finer MOS transistors have the problem of difficulty in suppressing leak currents and difficulty in decreasing the areas occupied by circuits because of the demand for securing necessary amounts of currents. In order to resolve the problem, there have been proposed surrounding gate transistors (SGT) having a structure in which a source, a gate, and a drain are disposed in a direction vertical to a substrate, and the gate surrounds a pillar-shaped semiconductor layer (for example, Japanese Unexamined Patent Application Publication Nos. 2-71556, 2-188966, and 3-145761).
  • By using a metal for a gate electrode instead of using polysilicon, depletion can be suppressed, and the resistance of the gate electrode can be decreased. However, a manufacturing process after a metal gate is formed must be one in which metal contamination by the metal gate is always taken into consideration.
  • In addition, in order to satisfy both a metal gate process and a high-temperature process for usual MOS transistors, a metal gate last process is used for actual products, in which a metal gate is formed after a high-temperature process (IEDM 2007 K. Mistry, et. al., pp. 247-250). The gate is formed using polysilicon, and then an interlayer insulating film is deposited. Then, the polysilicon gate is exposed by chemical mechanical polishing and etched, followed by deposition of a metal. Therefore, in order to satisfy both the metal gate process and the high-temperature process, the metal gate last process must be used for SGT, in which a metal gate is formed after the high-temperature process. Since, in the SGT, the upper surface of the pillar-shaped silicon layer is higher than the gate, some consideration is required for using the metal gate last process.
  • In addition, usual MOS transistors use a first insulating film in order to decrease a parasitic capacitance between gate wiring and a substrate. For example, in FINFET (IEDM 2010 C C. Wu, et. al., 27.1.1-27.1.4.), a first insulating film is formed around a fin-shaped semiconductor layer and then etched back to expose the fin-shaped semiconductor layer, thereby decreasing the parasitic capacitance between the gate wiring and the substrate. Also, in SGT, the first insulating film must be used for decreasing the parasitic capacitance between the gate wiring and the substrate. The SGT includes the pillar-shaped semiconductor layer in addition to the fin-shaped semiconductor layer, and thus some consideration is required for forming the pillar-shaped semiconductor layer.
    • SUMMARY
  • Accordingly, an object is to decrease a parasitic capacitance between a gate wiring and a substrate, provide a SGT manufacturing method using a gate last process, and provide a resulting SGT structure.
  • A method for manufacturing a semiconductor device of the present invention includes:
  • a first step of forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer, the width of the pillar-shaped silicon layer being equal to the width of the fin-shaped silicon layer;
  • a second step of, after the first step, forming diffusion layers by implanting impurities in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer;
  • a third step of, after the second step, forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring so that the gate insulating film covers the periphery and the top of the pillar-shaped silicon layer, the polysilicon gate electrode covers the gate insulating film, and after the polysilicon gate electrode and the polysilicon gate wiring are formed, the upper surface of polysilicon is higher than the gate insulating film on the diffusion layer formed in the upper portion of the pillar-shaped silicon layer;
  • a fourth step of, after the third step, forming a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer;
  • a fifth step of, after the fourth step, depositing an interlayer insulating film, exposing the polysilicon gate electrode and the polysilicon gate wiring, etching the polysilicon gate electrode and the polysilicon gate wiring, and then depositing a metal to form a metal gate electrode and a metal gate wiring, the metal gate wiring being connected to the metal gate electrode and extending in a direction perpendicular to the fin-shaped silicon layer; and
  • a sixth step of, after the fifth step, forming a contact so as to make direct contact between the contact and the diffusion layer in the upper portion of the pillar-shaped silicon layer.
  • The manufacturing method is also characterized in that a first resist is formed for forming the fin-shaped silicon layer on the silicon substrate; the silicon substrate is etched to form the fin-shaped silicon layer and the first resist is removed; the first insulating film is deposited around the fin-shaped silicon layer and then etched back to expose an upper portion of the fin-shaped silicon layer; a second resist is formed to be perpendicular to the fin-shaped silicon layer; the fin-shaped silicon layer is etched; and then the second resist is removed to form the pillar-shaped silicon layer so that a portion where the fin-shaped silicon layer and the second resist intersect at right angles becomes the pillar-shaped silicon layer.
  • The manufacturing method is further characterized in that in a structure including the fin-shaped silicon layer formed on the silicon substrate, the first insulating film formed around the fin-shaped silicon layer, and the pillar-shaped silicon layer formed on the fin-shaped silicon layer, a second oxide film is deposited, a first nitride film is formed on the second oxide film, the first nitride film is etched to be left as a side wall, the diffusion layers are formed by impurity implantation in an upper portion of the pillar-shaped silicon layer and an upper portion of the fin-shaped silicon layer, and the first nitride film and the second oxide film are removed, followed by heat treatment.
  • The manufacturing method is further characterized in that in a structure including the fin-shaped silicon layer formed on the silicon substrate, the first insulating film formed around the fin-shaped silicon layer, the pillar-shaped silicon layer formed on the fin-shaped silicon layer, the diffusion layer formed in the upper portion of the fin-shaped silicon layer and in the lower portion of the pillar-shaped silicon layer, and the diffusion layer formed in the upper portion of the pillar-shaped silicon layer, the gate insulating film is formed, polysilicon is deposited and then planarized so that after planarization, the upper surface of the polysilicon is higher than the gate insulating film on the diffusion layer formed in the upper portion of the pillar-shaped silicon layer, a second nitride film is deposited, a third resist is formed for forming the polysilicon gate electrode and the polysilicon gate wiring, the second nitride film is etched, the polysilicon is etched to form the polysilicon gate electrode and the polysilicon gate wiring, the gate insulating film is etched, and the third resist is removed.
  • The manufacturing method is further characterized in that a third nitride film is deposited and then etched to be left as a side wall, and a metal is deposited to form a silicide in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer.
  • The manufacturing method is further characterized in that a fourth nitride film is deposited, the interlayer insulating film is deposited and then planarized, the polysilicon gate electrode and the polysilicon gate wiring are exposed, the polysilicon gate electrode and the polysilicon gate wiring are removed, a metal is filled in a portion from which the polysilicon gate electrode and the polysilicon gate wiring have been removed, and the metal is etched to expose the gate insulating film on the diffusion layer in the upper portion of the pillar-shaped silicon layer, thereby forming the metal gate electrode and the metal gate wiring.
  • A semiconductor device of the present invention includes: a fin-shaped silicon layer formed on a silicon substrate; a first insulating film formed around the fin-shaped silicon layer; a pillar-shaped silicon layer formed on the fin-shaped silicon layer, the width of the pillar-shaped silicon layer being equal to the width of the fin-shaped silicon layer; a diffusion layer formed in an upper portion of the fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer; a diffusion layer formed in an upper portion of the pillar-shaped silicon layer; a silicide formed in an upper portion of the diffusion layer in the upper portion of the fin-shaped silicon layer; a gate insulating film formed around the pillar-shaped silicon layer; a metal gate electrode formed around the gate insulating film: a metal gate wiring connected to the metal gate electrode and extending in a direction perpendicular to the fin-shaped silicon layer; and a contact formed on the diffusion layer formed in the upper portion of the pillar-shaped silicon layer so as to make direct contact between the contact and the diffusion layer formed in the upper portion of the pillar-shaped silicon layer.
  • According to the present invention, it is possible to decrease a parasitic capacitance between a gate wiring and a substrate, provide a SGT manufacturing method using a gate last process, and provide a resulting SGT structure.
  • The fin-shaped silicon layer, the first insulating film, and the pillar-shaped silicon layer are formed based on a conventional FINFET manufacturing method and thus can be easily formed.
  • In addition, a silicide is generally formed in an upper portion of the pillar-shaped silicon layer, but the silicide must be formed after a polysilicon gate is formed because the deposition temperature of polysilicon is higher than the silicide formation temperature.
  • Therefore, when the silicide is formed in an upper portion of a silicon column, a hole is formed on a polysilicon gate electrode after the polysilicon gate is formed, the silicide is formed after a side wall composed of an insulating film is formed on the side wall of the hole, and then the hole is filled with an insulating film, thereby causing the problem of increasing the number of manufacturing steps. Therefore, the diffusion layers are formed before the polysilicon gate electrode and the polysilicon gate wiring are formed, the pillar-shaped silicon layer is covered with the polysilicon gate electrode, and the silicide is formed only in an upper portion of the fin-shaped silicon layer. Therefore, a usual metal gate last manufacturing method can be used, in which a gate is formed using polysilicon, the interlayer insulating film is deposited, the polysilicon gate is exposed by chemical mechanical polishing and then etched, and then a metal is deposited, thereby facilitating the formation of metal gate SGT.
    • BRIEF DESCRIPTION OF THE DRAWING
  • FIG. 1( a) is a plan view of a semiconductor device according to the present invention, FIG. 1( b) is a sectional view taken along line X-X′ in FIG. 1( a), and FIG. 1( c) is a sectional view taken along line Y-Y′ in FIG. 1( a).
  • FIG. 2( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 2( b) is a sectional view taken along line X-X′ in FIG. 2( a), and FIG. 2( c) is a sectional view taken along line Y-Y′ in FIG. 2( a).
  • FIG. 3( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 3( b) is a sectional view taken along line X-X′ in FIG. 3( a), and FIG. 3( c) is a sectional view taken along line Y-Y′ in FIG. 3( a).
  • FIG. 4( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 4( b) is a sectional view taken along line X-X′ in FIG. 4( a), and FIG. 4( c) is a sectional view taken along line Y-Y′ in FIG. 4( a).
  • FIG. 5( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 5( b) is a sectional view taken along line X-X′ in FIG. 5( a), and FIG. 5( c) is a sectional view taken along line Y-Y′ in FIG. 5( a).
  • FIG. 6( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 6( b) is a sectional view taken along line X-X′ in FIG. 6( a), and FIG. 6( c) is a sectional view taken along line Y-Y′ in FIG. 6( a).
  • FIG. 7( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 7( b) is a sectional view taken along line X-X′ in FIG. 7( a), and FIG. 7( c) is a sectional view taken along line Y-Y′ in FIG. 7( a).
  • FIG. 8( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 8( b) is a sectional view taken along line X-X′ in FIG. 8( a), and FIG. 8( c) is a sectional view taken along line Y-Y′ in FIG. 8( a).
  • FIG. 9( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 9( b) is a sectional view taken along line X-X′ in FIG. 9( a), and FIG. 9( c) is a sectional view taken along line Y-Y′ in FIG. 9( a).
  • FIG. 10( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 10( b) is a sectional view taken along line X-X′ in FIG. 10( a), and FIG. 10( c) is a sectional view taken along line Y-Y′ in FIG. 10( a).
  • FIG. 11( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 11( b) is a sectional view taken along line X-X′ in FIG. 11( a), and FIG. 11( c) is a sectional view taken along line Y-Y′ in FIG. 11( a).
  • FIG. 12( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 12( b) is a sectional view taken along line X-X′ in FIG. 12( a), and FIG. 12( c) is a sectional view taken along line Y-Y′ in FIG. 12( a).
  • FIG. 13( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 13( b) is a sectional view taken along line X-X′ in FIG. 13( a), and FIG. 13( c) is a sectional view taken along line Y-Y′ in FIG. 13( a).
  • FIG. 14( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 14( b) is a sectional view taken along line X-X′ in FIG. 14( a), and FIG. 14( c) is a sectional view taken along line Y-Y′ in FIG. 14( a).
  • FIG. 15( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 15( b) is a sectional view taken along line X-X′ in FIG. 15( a), and FIG. 15( c) is a sectional view taken along line Y-Y′ in FIG. 15( a).
  • FIG. 16( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 16( b) is a sectional view taken along line X-X′ in FIG. 16( a), and FIG. 16( c) is a sectional view taken along line Y-Y′ in FIG. 16( a).
  • FIG. 17( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 17( b) is a sectional view taken along line X-X′ in FIG. 17( a), and FIG. 17( c) is a sectional view taken along line Y-Y′ in FIG. 17( a).
  • FIG. 18( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 18( b) is a sectional view taken along line X-X′ in FIG. 18( a), and FIG. 18( c) is a sectional view taken along line Y-Y′ in FIG. 18( a).
  • FIG. 19( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 19( b) is a sectional view taken along line X-X′ in FIG. 19( a), and FIG. 19( c) is a sectional view taken along line Y-Y′ in FIG. 19( a).
  • FIG. 20( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 20( b) is a sectional view taken along line X-X′ in FIG. 20( a), and FIG. 20( c) is a sectional view taken along line Y-Y′ in FIG. 20( a).
  • FIG. 21( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 21( b) is a sectional view taken along line X-X′ in FIG. 21( a), and FIG. 21( c) is a sectional view taken along line Y-Y′ in FIG. 21( a).
  • FIG. 22( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 22( b) is a sectional view taken along line X-X′ in FIG. 22( a), and FIG. 22( c) is a sectional view taken along line Y-Y′ in FIG. 22( a).
  • FIG. 23( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 23( b) is a sectional view taken along line X-X′ in FIG. 23( a), and FIG. 23( c) is a sectional view taken along line Y-Y′ in FIG. 23( a).
  • FIG. 24( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 24( b) is a sectional view taken along line X-X′ in FIG. 24( a), and FIG. 24( c) is a sectional view taken along line Y-Y′ in FIG. 24( a).
  • FIG. 25( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 25( b) is a sectional view taken along line X-X′ in FIG. 25( a), and FIG. 25( c) is a sectional view taken along line Y-Y′ in FIG. 25( a).
  • FIG. 26( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 26( b) is a sectional view taken along line X-X′ in FIG. 26( a), and FIG. 26( c) is a sectional view taken along line Y-Y′ in FIG. 26( a).
  • FIG. 27( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 27( b) is a sectional view taken along line X-X′ in FIG. 27( a), and FIG. 27( c) is a sectional view taken along line Y-Y′ in FIG. 27( a).
  • FIG. 28( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 28( b) is a sectional view taken along line X-X′ in FIG. 28( a), and FIG. 28( c) is a sectional view taken along line Y-Y′ in FIG. 28( a).
  • FIG. 29( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 29( b) is a sectional view taken along line X-X′ in FIG. 29( a), and FIG. 29( c) is a sectional view taken along line Y-Y′ in FIG. 29( a).
  • FIG. 30( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 30( b) is a sectional view taken along line X-X′ in FIG. 30( a), and FIG. 30( c) is a sectional view taken along line Y-Y′ in FIG. 30( a).
  • FIG. 31( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 31( b) is a sectional view taken along line X-X′ in FIG. 31( a), and FIG. 31( c) is a sectional view taken along line Y-Y′ in FIG. 31( a).
  • FIG. 32( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 32( b) is a sectional view taken along line X-X′ in FIG. 32( a), and FIG. 32( c) is a sectional view taken along line Y-Y′ in FIG. 32( a).
  • FIG. 33( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 33( b) is a sectional view taken along line X-X′ in FIG. 33( a), and FIG. 33( c) is a sectional view taken along line Y-Y′ in FIG. 33( a).
  • FIG. 34( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 34( b) is a sectional view taken along line X-X′ in FIG. 34( a), and FIG. 34( c) is a sectional view taken along line Y-Y′ in FIG. 34( a).
  • FIG. 35( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 35( b) is a sectional view taken along line X-X′ in FIG. 35( a), and FIG. 35( c) is a sectional view taken along line Y-Y′ in FIG. 35( a).
  • FIG. 36( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 36( b) is a sectional view taken along line X-X′ in FIG. 36( a), and FIG. 36( c) is a sectional view taken along line Y-Y′ in FIG. 36( a).
  • FIG. 37( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 37( b) is a sectional view taken along line X-X′ in FIG. 37( a), and FIG. 37( c) is a sectional view taken along line Y-Y′ in FIG. 37( a).
  • FIG. 38( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 38( b) is a sectional view taken along line X-X′ in FIG. 38( a), and FIG. 38( c) is a sectional view taken along line Y-Y′ in FIG. 38( a).
  • FIG. 39( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 39( b) is a sectional view taken along line X-X′ in FIG. 39( a), and FIG. 39( c) is a sectional view taken along line Y-Y′ in FIG. 39( a).
  • FIG. 40( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 40( b) is a sectional view taken along line X-X′ in FIG. 40( a), and FIG. 40( c) is a sectional view taken along line Y-Y′ in FIG. 40( a).
  • FIG. 41( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 41( b) is a sectional view taken along line X-X′ in FIG. 41( a), and FIG. 41( c) is a sectional view taken along line Y-Y′ in FIG. 41( a).
  • FIG. 42( a) is a plan view of a method for manufacturing a semiconductor device according to the present invention, FIG. 42( b) is a sectional view taken along line X-X′ in FIG. 42( a), and FIG. 42( c) is a sectional view taken along line Y-Y′ in FIG. 42( a).
    •  DETAILED DESCRIPTION
  • A manufacturing process for forming a SGT structure according to an embodiment of the present invention is described below with reference to FIGS. 2 to 42.
  • First, a manufacturing method for forming a fin-shaped silicon layer on a silicon substrate, forming a first insulating film around the fin-shaped silicon layer, and forming a pillar-shaped silicon layer on the fin-shaped silicon layer is described. As shown in FIG. 2, a first resist 102 is formed for forming a fin-shaped silicon layer on a silicon substrate 101.
  • As shown in FIG. 3, the silicon substrate 101 is etched to form a fin-shaped silicon layer 103. Although, in this case, the fin-shaped silicon layer is formed using the resist as a mask, a hard mask such as an oxide film or a nitride film may be used.
  • As shown in FIG. 4, the first resist 102 is removed.
  • As shown in FIG. 5, a first insulating film 104 is deposited around the fin-shaped silicon layer 103. As the first insulating film, an oxide film formed by high-density plasma, or an oxide film formed by low-pressure chemical vapor deposition may be used.
  • As shown in FIG. 6, the first insulating film 104 is etched back to expose an upper portion of the fin-shaped silicon layer 103. The steps up to this step are the same as in the method for forming a fin-shaped silicon layer of Japanese Unexamined Patent Application Publication No. 2-188966.
  • As shown in FIG. 7, a second resist 105 is formed so as to be perpendicular to the fin-shaped silicon layer 103. A portion where the fin-shaped silicon layer 103 and the second resist 105 intersect at right angles becomes a pillar-shaped silicon layer. Since a linear resist can be used, the resist is unlikely to fall after patterning, thereby realizing a stable process.
  • As shown in FIG. 8, the fin-shaped silicon layer 103 is etched. A portion where the fin-shaped silicon layer 103 and the second resist 105 intersect at right angles becomes the pillar-shaped silicon layer 106. Therefore, the width of the pillar-shaped silicon layer 106 is equal to the width of the fin-shaped silicon layer. As a result, a structure is formed, in which the pillar-shaped silicon layer 106 is formed in an upper portion of the fin-shaped silicon layer 103, and the first insulating film 104 is formed around the fin-shaped silicon layer 103.
  • As shown in FIG. 9, the second resist 105 is removed.
  • Next, a description is given of a manufacturing method for forming diffusion layers by implanting impurities in an upper portion of the pillar-shaped silicon layer, an upper portion of the fin-shaped silicon layer, and a lower portion of the pillar-shaped silicon layer in order to use a gate-last process. As shown in FIG. 10, a second oxide film 107 is deposited, and a first nitride film 108 is formed. Since an upper portion of the pillar-shaped silicon layer is subsequently covered with a gate insulating film and a polysilicon gate electrode, a diffusion layer is formed in an upper portion of the pillar-shaped silicon layer before covering of the pillar-shaped silicon layer.
  • As shown in FIG. 11, the first nitride film 108 is etched to be left as a wide wall.
  • As shown in FIG. 12, impurities such as arsenic, phosphorus, or boron are implanted to form a diffusion layer 110 in an upper portion of the pillar-shaped silicon layer, and diffusion layers 109 and 111 in an upper portion of the fin-shaped silicon layer 103.
  • As shown in FIG. 13, the first nitride film 108 and the second oxide film 107 are removed.
  • As shown in FIG. 14, heat treatment is performed. The diffusion layers 109 and 111 in an upper portion of the fin-shaped silicon layer 103 are brought into contact with each other to form a diffusion layer 112. As described above, in order to use the gate-last process, the diffusion layers 110 and 112 are formed by impurity implantation in an upper portion of the pillar-shaped silicon layer and in an upper portion of the fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer.
  • Next, a description is given of a manufacturing method for forming a polysilicon gate electrode and a polysilicon gate wiring using polysilicon in order to use the gate-last process. In order to use the gate-last process, an interlayer insulating film is deposited, and then the polysilicon gate electrode and the polysilicon gate wiring are exposed by chemical mechanical polishing. Therefore, it is necessary to prevent an upper portion of the pillar-shaped silicon layer from being exposed by chemical mechanical polishing.
  • As shown in FIG. 15, a gate insulating film 113 is formed, and polysilicon 114 is deposited and then planarized. After planarization, the upper surface of the polysilicon is higher than the gate insulating film 113 disposed on the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106. As a result, when in order to use the gate-last process, the polysilicon gate electrode and the polysilicon gate wiring are exposed by chemical mechanical polishing after the interlayer insulating film is deposited, the upper portion of the pillar-shaped silicon layer is not exposed by chemical mechanical polishing.
  • In addition, a second nitride film 115 is deposited. The second nitride film is one which inhibits the formation of silicide in upper portions of the polysilicon gate electrode and the polysilicon gate wiring when the silicide is formed in an upper portion of the fin-shaped silicon layer.
  • As shown in FIG. 16, a third resist 116 is formed for forming the polysilicon gate electrode and the polysilicon gate wiring. A portion corresponding to gate wiring is preferably perpendicular to the fin-shaped silicon layer 103. This is because a parasitic capacitance between the gate wiring and the substrate is decreased.
  • As shown in FIG. 17, the second nitride film 115 is etched.
  • As shown in FIG. 18, the polysilicon 114 is etched to form a polysilicon gate electrode 114 a and a polysilicon gate wiring 114 b.
  • As shown in FIG. 19, the gate insulating film 113 is etched.
  • As shown in FIG. 20, the third resist 116 is removed.
  • The manufacturing method for forming the polysilicon gate electrode and the polysilicon gate wiring using polysilicon in order to use the gate-last process is described above. After the polysilicon gate electrode 114 a and the polysilicon gate wiring 114 b are formed, the upper surface of polysilicon is higher than the gate insulating film 113 on the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106.
  • Next, a manufacturing method for forming a silicide in an upper portion of the fin-shaped silicon layer is described. The silicide is not formed in upper portions of the polysilicon gate electrode 114 a and the polysilicon gate wiring 114 b and in the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106. When the silicide is formed in the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106, the manufacturing process is enlarged.
  • As shown in FIG. 21, a third nitride film 117 is deposited.
  • As shown in FIG. 22, the third nitride film 117 is etched to be left as a side wall.
  • As shown in FIG. 23, a metal such as nickel or cobalt is deposited to form silicide 118 in an upper portion of the diffusion layer 112 formed in an upper portion of the fin-shaped silicon layer 103. At this time, the polysilicon gate electrode 114 a and the polysilicon gate wiring 114 b are covered with the third nitride film 117 and the second nitride film 115, and the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106 is covered with the gate insulating film 113, the polysilicon gate electrode 114 a, and the polysilicon gate wiring 114 b, and thus silicide is not formed in the polysilicon gate electrode 114 a, the polysilicon gate wiring 114 b, and the diffusion layer 110.
  • The manufacturing method for forming a silicide in an upper portion of the fin-shaped silicon layer is described above.
  • Next, a gate-last manufacturing method is described, in which the polysilicon gate electrode and the polysilicon wiring are exposed by chemical mechanical polishing after an interlayer insulting film is deposited, the polysilicon gate electrode and the polysilicon wiring are etched, and then a metal is deposited.
  • As shown in FIG. 24, a fourth nitride film 140 is deposited for protecting the silicide 118.
  • As shown in FIG. 25, an interlayer insulating film 119 is deposited and then planarized by chemical mechanical polishing.
  • As shown in FIG. 26, the polysilicon gate electrode 114 a and the polysilicon gate wiring 114 b are exposed by chemical mechanical polishing.
  • As shown in FIG. 27, the polysilicon gate electrode 114 a and the polysilicon gate wiring 114 b are etched. Wet etching is preferred.
  • As shown in FIG. 28, a metal 120 is deposited and then planarized to fill, with the metal 120, a portion from which the polysilicon gate electrode 114 a and the polysilicon gate wiring 114 b have been removed. Atomic layer deposition is preferably used.
  • As shown in FIG. 29, the metal 120 is etched to expose the gate insulating film 113 formed on the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106. Consequently, a metal gate electrode 120 a and a metal gate wiring 120 b are formed. The gate-last manufacturing method is described above, in which after the interlayer insulating film is deposited, the polysilicon gate is exposed by chemical mechanical polishing, the polysilicon gate is etched, and then a metal is deposited.
  • Next, a manufacturing method for forming a contact is described. Since a silicide is not formed in the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106, a contact is brought into direct contact with the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106. As shown in FIG. 30, an interlayer insulating film 121 is deposited and then planarized.
  • As shown in FIG. 31, a fourth resist 122 is formed for forming a contact hole on the pillar-shaped silicon layer 106.
  • As shown in FIG. 32, the interlayer insulating film 121 is etched to form a contact hole 123.
  • As shown in FIG. 33, the fourth resist 122 is removed.
  • As shown in FIG. 34, a fifth resist 124 is formed for forming contact holes on the metal gate wiring 120 b and on the fin-shaped silicon layer 103.
  • As shown in FIG. 35, the interlayer insulating films 121 and 119 are etched to form contact holes 125 and 126.
  • As shown in FIG. 36, the fifth resist 124 is removed.
  • As shown in FIG. 37, the nitride film 140 and the gate insulating film 113 is etched to expose the silicide 118 and the diffusion layer 110.
  • As shown in FIG. 38, a metal is deposited to form contacts 143, 127, and 128. The manufacturing method for forming contacts is described above. Since a silicide is not formed in the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106, the contact 127 is brought into direct contact with the diffusion layer 110 in an upper portion of the pillar-shaped silicon layer 106.
  • Next, a manufacturing method for forming a metal wiring layer is described.
  • As shown in FIG. 39, a metal 129 is deposited.
  • As shown in FIG. 40, sixth resists 130, 131, and 132 are formed for forming the metal wiring.
  • As shown in FIG. 41, the metal 129 is etched to metal wirings 133, 134, and 135.
  • As shown in FIG. 42, the sixth resists 130, 131, and 132 are removed.
  • The manufacturing method for forming metal wiring layers is described above.
  • The result of the above-described manufacturing method is shown in FIG. 1.
  • The resulting structure includes: the fin-shaped silicon layer 103 formed on the substrate 101; the first insulating film 104 formed around the fin-shaped silicon layer 103; the pillar-shaped silicon layer 106 formed on the fin-shaped silicon layer 103, the width of the pillar-shaped silicon layer 106 being equal to the width of the fin-shaped silicon layer 103; the diffusion layer 112 formed in an upper portion of the fin-shaped silicon layer 103 and a lower portion of the pillar-shaped silicon layer 106; the diffusion layer 110 formed in an upper portion of the pillar-shaped silicon layer 106; the silicide 118 formed in an upper portion of the diffusion layer 112 in an upper portion of the fin-shaped silicon layer 103; the gate insulating film 113 formed around the pillar-shaped silicon layer 106; the metal gate electrode 120 a formed around the gate insulating film; the metal gate wiring 120 b connected to the metal gate electrode 120 a and extending in a direction perpendicular to the fin-shaped silicon layer 103; and the contact 127 formed on the diffusion layer 110, the diffusion layer 110 and the contact 127 being in direct contact with each other.
  • As described above, it is possible to decrease a parasitic capacitance between a gate wiring and a substrate and provide a SGT manufacturing method using a gate-last process and a resulting SGT structure.

Claims (5)

1. A method for manufacturing a semiconductor device, the method comprising:
providing a silicon substrate and forming a first resist thereon;
etching the silicon substrate to form a fin-shaped silicon layer on the silicon substrate and removing the first resist;
depositing a first insulating film around the fin-shaped silicon layer and etching back the first insulating film to expose an upper portion of the fin-shaped silicon layer;
forming a second resist so as to be perpendicular to the fin-shaped silicon layer; and
etching the fin-shaped silicon layer and removing the second resist to form a pillar-shaped silicon layer at a location where the fin-shaped silicon layer and the second resist intersect at a right angle.
2. The method for manufacturing a semiconductor device according to claim 1 further comprising:
forming a gate insulating film, a polysilicon gate electrode, and a polysilicon gate wiring, such that the gate insulating film covers a periphery and a top of the pillar-shaped silicon layer, and the polysilicon gate electrode covers the gate insulating film,
wherein after the polysilicon gate electrode and the polysilicon gate wiring are formed, an upper surface of the polysilicon gate electrode is higher than the gate insulating film on the top of the pillar-shaped silicon layer;
depositing an interlayer insulating film and exposing a portion of the polysilicon gate electrode and the polysilicon gate wiring;
etching the polysilicon gate electrode and the polysilicon gate wiring; and
depositing a metal to form a metal gate electrode and a metal gate wiring, such that the metal gate wiring is connected to the metal gate electrode and extends on the silicon substrate in a direction perpendicular to a direction of the fin-shaped silicon layer.
3. The method for manufacturing a semiconductor device according to claim 2, wherein forming the gate insulating film comprises forming the gate insulating film on the fin-shaped silicon layer, the first insulating film, and the pillar-shaped silicon layer,
the method further comprising:
depositing polysilicon and then plannarizing the polysilicon, such that after planarization, an upper surface of the polysilicon is higher than the gate insulating film on the upper portion of the pillar-shaped silicon layer;
depositing a nitride film;
forming a third resist for forming the polysilicon gate electrode and the polysilicon gate wiring;
etching the nitride film and the polysilicon to form the polysilicon gate electrode and the polysilicon gate wiring; and
etching the gate insulating film and removing the third resist.
4. The method for manufacturing a semiconductor device according to claim 3 further comprising depositing a second nitride film and etching the second nitride film to form a side wall.
5. The method for manufacturing a semiconductor device according to claim 4 further comprising:
plannarizing the interlayer insulating film and exposing a portion of the polysilicon gate electrode and the polysilicon gate wiring;
removing the polysilicon gate electrode and the polysilicon gate wiring and forming cavities;
filling a metal in the cavities; and
etching the metal to expose the gate insulating film on the upper portion of the pillar-shaped silicon layer to form a metal gate electrode and a metal gate wiring.
US14/272,944 2011-11-09 2014-05-08 Method for manufacturing semiconductor device and semiconductor device Abandoned US20140242766A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US14/272,944 US20140242766A1 (en) 2011-11-09 2014-05-08 Method for manufacturing semiconductor device and semiconductor device
US15/221,077 US10438836B2 (en) 2011-11-09 2016-07-27 Method for manufacturing a semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201161557501P 2011-11-09 2011-11-09
US13/666,445 US8759178B2 (en) 2011-11-09 2012-11-01 Method for manufacturing semiconductor device and semiconductor device
US14/272,944 US20140242766A1 (en) 2011-11-09 2014-05-08 Method for manufacturing semiconductor device and semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US13/666,445 Continuation US8759178B2 (en) 2011-11-09 2012-11-01 Method for manufacturing semiconductor device and semiconductor device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US15/221,077 Continuation-In-Part US10438836B2 (en) 2011-11-09 2016-07-27 Method for manufacturing a semiconductor device

Publications (1)

Publication Number Publication Date
US20140242766A1 true US20140242766A1 (en) 2014-08-28

Family

ID=48223119

Family Applications (4)

Application Number Title Priority Date Filing Date
US13/666,445 Active US8759178B2 (en) 2011-11-09 2012-11-01 Method for manufacturing semiconductor device and semiconductor device
US14/061,082 Active 2032-11-17 US9614075B2 (en) 2011-11-09 2013-10-23 Semiconductor device
US14/272,944 Abandoned US20140242766A1 (en) 2011-11-09 2014-05-08 Method for manufacturing semiconductor device and semiconductor device
US15/221,091 Active US9691896B2 (en) 2011-11-09 2016-07-27 Semiconductor device

Family Applications Before (2)

Application Number Title Priority Date Filing Date
US13/666,445 Active US8759178B2 (en) 2011-11-09 2012-11-01 Method for manufacturing semiconductor device and semiconductor device
US14/061,082 Active 2032-11-17 US9614075B2 (en) 2011-11-09 2013-10-23 Semiconductor device

Family Applications After (1)

Application Number Title Priority Date Filing Date
US15/221,091 Active US9691896B2 (en) 2011-11-09 2016-07-27 Semiconductor device

Country Status (1)

Country Link
US (4) US8759178B2 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8916478B2 (en) * 2011-12-19 2014-12-23 Unisantis Electronics Singapore Pte. Ltd. Method for manufacturing semiconductor device and semiconductor device
WO2014170949A1 (en) 2013-04-16 2014-10-23 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Method for producing semiconductor device, and semiconductor device
JP5657151B1 (en) * 2014-01-23 2015-01-21 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． Semiconductor device and manufacturing method of semiconductor device
US9985030B2 (en) * 2014-04-07 2018-05-29 International Business Machines Corporation FinFET semiconductor device having integrated SiGe fin
JP5861197B2 (en) * 2015-01-07 2016-02-16 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． Semiconductor device manufacturing method and semiconductor device
JP5890053B2 (en) * 2015-04-27 2016-03-22 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． Semiconductor device manufacturing method and semiconductor device
US10199480B2 (en) * 2016-09-29 2019-02-05 Globalfoundries Inc. Controlling self-aligned gate length in vertical transistor replacement gate flow
EP3404721A1 (en) * 2017-05-15 2018-11-21 IMEC vzw A method for forming pillars in a vertical transistor device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100001249A1 (en) * 2008-07-03 2010-01-07 Elpida Memory, Inc. Semiconductor device enabling further microfabrication
US20110220994A1 (en) * 2010-03-10 2011-09-15 Micron Technology, Inc. Method of Forming a DRAM Array of Devices with Vertically Integrated Recessed Access Device and Digitline

Family Cites Families (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3057661B2 (en) 1988-09-06 2000-07-04 株式会社東芝 Semiconductor device
JP2703970B2 (en) 1989-01-17 1998-01-26 株式会社東芝 MOS type semiconductor device
JPH02145761A (en) 1988-11-28 1990-06-05 Matsushita Electric Ind Co Ltd Manufacture of thin superconductor film
JP2950558B2 (en) 1989-11-01 1999-09-20 株式会社東芝 Semiconductor device
JP2748072B2 (en) 1992-07-03 1998-05-06 三菱電機株式会社 Semiconductor device and manufacturing method thereof
JPH0831576B2 (en) 1993-02-05 1996-03-27 株式会社東芝 Semiconductor device and manufacturing method thereof
JPH07245291A (en) 1994-03-03 1995-09-19 Sony Corp Method and apparatus for etching silicon substrate
JPH07263677A (en) 1994-03-18 1995-10-13 Mitsubishi Electric Corp Semiconductor device and its manufacture
JPH08227997A (en) 1995-02-20 1996-09-03 Hitachi Ltd Semiconductor device and its manufacture
US6034389A (en) 1997-01-22 2000-03-07 International Business Machines Corporation Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array
US5874760A (en) 1997-01-22 1999-02-23 International Business Machines Corporation 4F-square memory cell having vertical floating-gate transistors with self-aligned shallow trench isolation
DE19711482C2 (en) 1997-03-19 1999-01-07 Siemens Ag Method of manufacturing a vertical MOS transistor
JPH11297984A (en) 1998-04-07 1999-10-29 Seiko Epson Corp Structure of ldd type mos transistor and forming method
JP3376302B2 (en) 1998-12-04 2003-02-10 株式会社東芝 Semiconductor device and manufacturing method thereof
JP2001284598A (en) 2000-03-31 2001-10-12 Fujitsu Ltd Semiconductor device and manufacturing method thereof
US6461900B1 (en) 2001-10-18 2002-10-08 Chartered Semiconductor Manufacturing Ltd. Method to form a self-aligned CMOS inverter using vertical device integration
CN1305134C (en) * 2001-11-06 2007-03-14 雅马哈株式会社 Semiconductor device with fuse and making method thereof
US7348243B2 (en) 2003-12-27 2008-03-25 Dongbu Electronics Co., Ltd. Semiconductor device and method for fabricating the same
JP4717014B2 (en) 2004-01-22 2011-07-06 インターナショナル・ビジネス・マシーンズ・コーポレーション Vertical FIN-FETMOS device
US7262089B2 (en) 2004-03-11 2007-08-28 Micron Technology, Inc. Methods of forming semiconductor structures
JP2005268418A (en) 2004-03-17 2005-09-29 Fujio Masuoka Semiconductor memory and method for manufacturing the same
US20070257277A1 (en) 2004-06-04 2007-11-08 Nec Corporation Semiconductor Device and Method for Manufacturing the Same
US7442976B2 (en) 2004-09-01 2008-10-28 Micron Technology, Inc. DRAM cells with vertical transistors
JP4997694B2 (en) 2004-10-07 2012-08-08 富士電機株式会社 Semiconductor device and manufacturing method thereof
JP2006310651A (en) 2005-04-28 2006-11-09 Toshiba Corp Method of manufacturing semiconductor device
JP4720307B2 (en) 2005-06-15 2011-07-13 富士電機システムズ株式会社 Manufacturing method of semiconductor device
KR100739532B1 (en) 2006-06-09 2007-07-13 삼성전자주식회사 Method of forming a buried bit line
JP2008066562A (en) 2006-09-08 2008-03-21 Toshiba Corp Semiconductor device and its manufacturing method
US20080136030A1 (en) 2006-10-23 2008-06-12 Interuniversitair Microelektronicacentrum (Imec) Semiconductor device comprising a doped metal comprising main electrode
JP2008140996A (en) 2006-12-01 2008-06-19 Elpida Memory Inc Semiconductor device, and manufacturing method therefor
US8058683B2 (en) * 2007-01-18 2011-11-15 Samsung Electronics Co., Ltd. Access device having vertical channel and related semiconductor device and a method of fabricating the access device
JP5466816B2 (en) 2007-08-09 2014-04-09 ピーエスフォー ルクスコ エスエイアールエル Manufacturing method of vertical MOS transistor
JP2009081163A (en) 2007-09-25 2009-04-16 Elpida Memory Inc Semiconductor device and manufacturing method thereof
JP4316658B2 (en) 2008-01-29 2009-08-19 日本ユニサンティスエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP5317343B2 (en) 2009-04-28 2013-10-16 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Semiconductor device and manufacturing method thereof
WO2009110050A1 (en) 2008-02-15 2009-09-11 日本ユニサンティスエレクトロニクス株式会社 Method for manufacturing semiconductor device
JP4487221B1 (en) 2009-04-17 2010-06-23 日本ユニサンティスエレクトロニクス株式会社 Semiconductor device
JP4577592B2 (en) 2009-04-20 2010-11-10 日本ユニサンティスエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP5465958B2 (en) 2009-09-01 2014-04-09 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
JP5006379B2 (en) 2009-09-16 2012-08-22 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Semiconductor device
JP2011071235A (en) 2009-09-24 2011-04-07 Toshiba Corp Semiconductor device and method of manufacturing the same
JP5602414B2 (en) 2009-11-05 2014-10-08 ピーエスフォー ルクスコ エスエイアールエル Semiconductor device manufacturing method and semiconductor device
KR20110101876A (en) 2010-03-10 2011-09-16 삼성전자주식회사 Semiconductor device with a buried bit line and method of manufacturing the semiconductor device
JP5066590B2 (en) 2010-06-09 2012-11-07 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Semiconductor device and manufacturing method thereof
JP5087655B2 (en) 2010-06-15 2012-12-05 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Semiconductor device and manufacturing method thereof
JP4756221B2 (en) 2010-06-29 2011-08-24 日本ユニサンティスエレクトロニクス株式会社 Semiconductor memory device
US20120276695A1 (en) * 2011-04-29 2012-11-01 International Business Machines Corporation Strained thin body CMOS with Si:C and SiGe stressor
US8735971B2 (en) * 2011-12-02 2014-05-27 Unisantis Electronics Singapore Pte. Ltd. Method for producing semiconductor device and semiconductor device
US8772175B2 (en) * 2011-12-19 2014-07-08 Unisantis Electronics Singapore Pte. Ltd. Method for manufacturing semiconductor device and semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100001249A1 (en) * 2008-07-03 2010-01-07 Elpida Memory, Inc. Semiconductor device enabling further microfabrication
US20110220994A1 (en) * 2010-03-10 2011-09-15 Micron Technology, Inc. Method of Forming a DRAM Array of Devices with Vertically Integrated Recessed Access Device and Digitline

Also Published As

Publication number Publication date
US20130113037A1 (en) 2013-05-09
US8759178B2 (en) 2014-06-24
US9614075B2 (en) 2017-04-04
US20140042504A1 (en) 2014-02-13
US20160336444A1 (en) 2016-11-17
US9691896B2 (en) 2017-06-27

Similar Documents

Publication Publication Date Title
US9362353B2 (en) Semiconductor device
US9390978B2 (en) Method for producing semiconductor device and semiconductor device
US9202922B2 (en) Semiconductor device
US9246001B2 (en) Semiconductor device
JP5695745B2 (en) Semiconductor device manufacturing method and semiconductor device
US8759178B2 (en) Method for manufacturing semiconductor device and semiconductor device
US9299701B2 (en) Method for producing semiconductor device and semiconductor device
US8916478B2 (en) Method for manufacturing semiconductor device and semiconductor device
JP6329301B2 (en) Semiconductor device manufacturing method and semiconductor device
JP6284585B2 (en) Semiconductor device manufacturing method and semiconductor device
JP6156883B2 (en) Semiconductor device manufacturing method and semiconductor device

Legal Events

Date Code Title Description
STCV Information on status: appeal procedure

Free format text: NOTICE OF APPEAL FILED

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION