US20140105336A1 - Reduced power-consumption receivers - Google Patents
Reduced power-consumption receivers Download PDFInfo
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- US20140105336A1 US20140105336A1 US14/133,280 US201314133280A US2014105336A1 US 20140105336 A1 US20140105336 A1 US 20140105336A1 US 201314133280 A US201314133280 A US 201314133280A US 2014105336 A1 US2014105336 A1 US 2014105336A1
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- Prior art keywords
- mixer
- duty cycle
- gain state
- local oscillator
- coupled
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/02—Power saving arrangements
- H04W52/0203—Power saving arrangements in the radio access network or backbone network of wireless communication networks
- H04W52/0206—Power saving arrangements in the radio access network or backbone network of wireless communication networks in access points, e.g. base stations
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
- H03G3/20—Automatic control
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
Definitions
- the present disclosure relates generally to receivers, and more specifically to techniques for reducing power consumption in radio frequency (RF) receivers.
- RF radio frequency
- a receiver receives a radio-frequency (RF) signal from a transmitter, and down-converts the received signal from RF to base-band using one or more mixers. Each mixer mixes the received signal with a local oscillator (LO) signal.
- LO local oscillator
- An LO buffer is typically provided to buffer the LO signal before the mixer.
- Some topologies involve a surface acoustic-wave (SAW) filter that is disposed in the incoming RF signal path between a low-noise amplifier (LNA) and a mixer. It is desirable to be able to realize a wireless device receiver of adequate performance without using the somewhat costly and large SAW device.
- SAW surface acoustic-wave
- LNA low-noise amplifier
- a purely passive down-converting mixer is sometimes used.
- the passive mixer does not have an active gm-cell, such as a gain stage before the mixer's switching core. It is, however, often difficult for this topology to meet demanding noise figure (NF) requirements while still achieving good linearity (e.g., triple beat) performance.
- NF noise figure
- FIG. 1 illustrates an exemplary wireless communication environment in which exemplary embodiments of the disclosure can be practiced.
- FIG. 2 illustrates an exemplary wireless device using prior art techniques.
- FIG. 3 illustrates an exemplary embodiment of the disclosure.
- FIGS. 4A-G are exemplary circuit diagrams of degenerative impedance elements used in conjunction with the exemplary embodiments of the disclosure.
- FIG. 5 is a flow chart illustrating an exemplary method of the disclosure.
- FIG. 6 illustrates another exemplary embodiment of the disclosure.
- FIG. 7 is a flow chart illustrating another exemplary method of the disclosure.
- the techniques described herein are applicable to and may be used for any electronic setting in any electrical or electronic environment in which radio frequency reception is desired.
- the exemplary embodiments described herein are presented in the context of a wireless communication environment, though they are not meant to be limited to such, but applicable to any wire or wireless communication setting which use radio-frequency transmission and reception, such as cell-phones, base-stations as well as cable set-top boxes and the likes.
- a CDMA network may implement a radio technology such as Universal Terrestrial Radio Access (UTRA), cdma2000, etc.
- UTRA includes Wideband-CDMA (W-CDMA), Low Chip Rate (LCR), High Chip Rate (HCR), etc.
- CDMA2000 covers IS-2000, IS-95, and IS-856 standards.
- a TDMA network may implement a radio technology such as Global System for Mobile Communications (GSM).
- GSM Global System for Mobile Communications
- An OFDMA network may implement a radio technology such as Evolved UTRA (E-UTRA), Ultra Mobile Broadband (UMB), IEEE 802.11 (Wi-Fi), IEEE 802.16 (WiMAX), IEEE 802.20, Flash-OFDM®, etc.
- E-UTRA Evolved UTRA
- UMB Ultra Mobile Broadband
- IEEE 802.11 Wi-Fi
- WiMAX IEEE 802.16
- Flash-OFDM® Flash-OFDM®
- UTRA, E-UTRA and GSM are described in documents from an organization named “3rd Generation Partnership Project” (3GPP).
- 3GPP 3rd Generation Partnership Project 2
- 3GPP and 3GPP2 documents are publicly available. For clarity, certain aspects of the techniques are described below for 3GPP networks.
- FIG. 1 illustrates an exemplary wireless communication environment 1 comprising communication systems 120 and 122 and a wireless device 110 , such as a multi-antenna wireless device capable of communicating with multiple wireless communication systems 120 and 122 .
- Wireless system 120 may be a CDMA system that may implement one or more CDMA standards such as, e.g., IS-2000 (commonly referred to as CDMA 1x), IS-856 (commonly referred to as CDMA 1x EV-DO), IS-95, W-CDMA, and so on.
- Wireless system 120 includes a base transceiver system (BTS) 130 and a mobile switching center (MSC) 140 .
- BTS 130 provides over-the-air communication for wireless devices under its coverage area.
- Wireless system 122 couples to BTSs in wireless system 120 and provides coordination and control for these BTSs.
- Wireless system 122 may be a TDMA system that may implement one or more TDMA standards such as, e.g., GSM.
- Wireless system 122 includes a Node B 132 and a radio network controller (RNC) 142 .
- Node B 132 provides over-the-air communication for wireless devices under its coverage area.
- RNC 142 couples to Node Bs in wireless system 122 and provides coordination and control for these Node Bs.
- BTS 130 and Node B 132 are fixed stations that provide communication coverage for wireless devices and may also be referred to as base stations or some other terminology.
- MSC 140 and RNC 142 are network entities that provide coordination and control for the base stations and may also be referred to by other terminologies.
- Wireless device 110 may be a cellular phone, a personal digital assistant (PDA), a wireless-enabled computer, or some other wireless communication unit or device. Wireless device 110 may also be referred to as a mobile station (3GPP2 terminology), a user equipment (UE) (3GPP terminology), an access terminal, or some other terminology. Wireless device 110 is equipped with multiple antennas, e.g., one external antenna and one or more internal antennas. The multiple antennas may be used to provide diversity against deleterious path effects such as fading, multipath, interference, and so on. An RF modulated signal transmitted from an antenna at a transmitting entity may reach the multiple antennas at wireless device 110 via line-of-sight paths and/or reflected paths.
- PDA personal digital assistant
- Wireless device 110 may also be referred to as a mobile station (3GPP2 terminology), a user equipment (UE) (3GPP terminology), an access terminal, or some other terminology.
- Wireless device 110 is equipped with multiple antennas, e.g., one external antenna and one or more internal antenna
- At least one propagation path typically exists between the transmit antenna and each receive antenna at wireless device 110 . If the propagation paths for different receive antennas are independent, which is generally true to at least an extent, then diversity increases and the received signal quality improves when multiple antennas are used to receive the RF modulated signal.
- Wireless device 110 may or may not be capable of receiving signals from satellites 150 .
- Satellites 150 may belong to a satellite positioning system such as the well-known Global Positioning System (GPS), the European Galileo system, or some other systems.
- GPS Global Positioning System
- Each GPS satellite transmits a GPS signal encoded with information that allows a GPS receiver on Earth to measure the time of arrival (TOA) of the GPS signal. Measurements for a sufficient number of GPS satellites may be used to obtain an accurate three-dimensional position estimate for the GPS receiver.
- the wireless device 110 may be capable of communicating with any number of wireless systems of different wireless technologies (e.g., CDMA, GSM, GPS, and so on).
- FIG. 2 is a block diagram illustrating an exemplary wireless device 110 .
- Wireless device 110 includes a transceiver system 210 , such as a SAW-less transceiver, which at one end couples to an antenna 202 , such as a main antenna, which may be an external antenna, and at the other end is in communication with a mobile station modem (MSM) 220 , such as via path 240 .
- MSM 220 comprises a processor 224 which is in communication with a memory 222 .
- an incoming RF signal received in antenna 202 is received into the differential input terminals 20 a and 20 b of the low noise amplifier (LNA) 20 .
- LNA 20 amplifies the RF signal and drives differential signals from output leads 21 a and 21 b.
- Output leads 21 a and 21 b of LNA 20 are coupled to the inputs of mixers 22 a and 22 b, for down-converting the RF signal, such as to base-band signals I and Q.
- Output lead 21 a is coupled to a first differential input lead 22 a 2 of mixer 22 a
- output lead 21 b is coupled to a second differential input lead 22 a 1 of mixer 22 a.
- mixer 22 a comprises a passive mixer having no active gm-cell, such as a gain stage before the mixer's switching core.
- the mixer 22 a is a Gilbert Mixer which includes two cross-coupled switching elements 22 a 3 and 22 a 4 , such as field effect transistors (FET), and whose configuration and operation is well known in the art.
- Output lead 21 a is coupled to a first differential input lead 22 b 1 of mixer 22 b
- output lead 21 b is coupled to a second differential input lead 22 b 2 of mixer 22 b.
- mixer 22 b comprises a passive mixer having no active gm-cell, such as a gain stage before the mixer's switching core, and like mixer 22 a comprises a Gilbert Mixer having two cross-coupled switching elements.
- the transceiver system 210 also includes a voltage controlled oscillator 29 for generating a down-converting voltage signal which is first buffered in buffer 28 , and then frequency divided by the frequency divider 27 , such as divided by two. The output of the frequency divider 27 is then fed into the 25 duty cycle (DC) generator 26 , which outputs 25 DC signals 25 a and 25 b to buffers 24 a and 24 b, respectively. Buffers 24 a and 24 b then output buffered signals 23 a 1 , 23 a 2 and 23 b 1 , 23 b 2 to the mixers 22 a and 22 b respectively.
- DC duty cycle
- Mixers 22 a and 22 b then respectively mix signals 23 a 1 , 23 a 2 and 23 b 1 , 23 b 2 with the RF signals received in their inputs 22 a 1 , 22 a 2 and 22 b 1 , 22 b 2 , to generate down-converted Quadrature (Q) signals 50 a 1 , 50 a 2 and In-phase (I) signals 50 b 1 , 50 b 2 , respectively.
- the down-converted I and Q signals are then provided to the MSM 220 , such as via path 240 .
- a shortcoming in the above transceiver system 210 is that a 25DC LO consumes relatively high current resulting in higher consumption of power. Usage of a higher duty-cycle LO, such as a 50DC LO, however, can reduce power consumption but comes at the cost of reduced gain, resulting in degraded noise figure performance.
- FIG. 3 illustrates an exemplary embodiment of the disclosure, described in the context of a SAW-less GSM transceiver system 310 for exemplary purposes only, but which can be used with other communication systems as well.
- the transceiver system 310 couples to an antenna 302 , such as a main antenna, which may be an external antenna, and is in communication with a mobile station modem (MSM) 320 , such as via path 330 .
- MSM 320 comprises a processor 323 which is in communication with a memory 322 which may be internal to MSM 320 as shown, or external to MSM 320 (not shown).
- the transceiver system 310 includes a mixer 32 a, such as an active or passive mixer, for down-converting a RF signal, such as an Quadrature (Q) signal, first received on antenna 302 , and then into the differential input terminals 30 a and 30 b of the low noise amplifier (LNA) 30 , whose output leads 31 a and 31 b are then coupled to the mixer 32 a.
- LNA 30 is a variable gain amplifier.
- mixer 32 a comprises a passive mixer having no active gm-cell, such as a gain stage before the mixer's switching core. In the exemplary embodiment shown in FIG.
- mixer 32 a is a Gilbert Mixer which includes two cross-coupled switching elements 32 a 3 and 32 a 4 , each having a plurality of transistors, such as field effect transistors (FET).
- Mixer 32 a includes input leads 301 and 302 , with degenerative impedance elements, such as 304 and 305 , coupled to the input leads 301 and 302 , respectively.
- the degenerative impedance elements 304 and 305 are resistors having a resistance value greater than 20 ohms.
- the degenerative impedance elements 304 and 305 may be coupled to the input leads 301 and 302 internally to the mixer 32 a, as shown, or externally (not shown) along the input paths 301 a and 302 a, respectively.
- the transceiver system 310 further includes a local oscillator (LO) system 300 having a plurality of duty cycle modes to generate a LO signal for the mixer 32 a.
- the local oscillator system 300 includes a multi-mode duty cycle (DC) generator 36 , such as a programmable 25/50DC generator, that output LO signals 35 a to a buffer 33 a .
- DC duty cycle
- Buffered signals 33 a 1 and 33 a 2 are then respectively provided to the switching elements 32 a 4 and 32 a 3 of the mixer 32 a for down-converting of the RF signals received in the inputs leads 301 and 302 , to down-converted signals outputted from output paths 70 a 2 and 70 a 1 , respectively.
- the local oscillator system 300 operates in a first duty cycle based on a first gain state of the mixer 32 a, and in a second duty cycle based on a second gain state of the mixer 32 a.
- a control signal 51 is received in the local oscillator system 300 , such as from the processor 322 , to provide instruction to the duty cycle generator 36 as to which duty cycle to operate in.
- the duty cycle generator 36 is a programmable duty cycle generator.
- the transceiver system 310 also includes a voltage controlled oscillator 39 for generating a down-converting voltage signal which is then first buffered in buffer 38 , and then frequency divided by the frequency divider 37 , such as divided by two, before being fed into the local oscillator system 300 .
- the transceiver system 310 may include additional mixers, such as a mixer 32 b, for down-converting additional signals, such as In-Phase (I) signals.
- each additional mixer such as mixer 32 b
- each additional mixer also have degenerative impedance elements coupled to its inputs and also receives LO signals from the local oscillator system 300 , having additional buffers, such as buffer 33 b, which then operates based on the gains states of the mixers, such as both mixers 32 a and 32 b.
- additional buffers such as buffer 33 b
- the operation of the transceiver system 310 is described herein in detail only in the context of mixer 32 a, but can be readily applied to a configuration having more than one mixer, such as mixers 32 a and 32 b.
- FIGS. 4A-G are exemplary circuit diagrams of degenerative impedance elements 61 , with input leads 41 , which may be used as degenerative impedance elements, such as 304 and 305 , in the exemplary embodiments of the disclosure.
- a degenerative impedance element 61 may include a resistor as shown in FIG. 4A , a capacitor as shown in FIG. 4B , a transistor as shown in FIG. 4C , a resistor and a capacitor coupled in series as shown in FIG. 4D , a resistor and a transistor coupled in series as shown in FIG. 4E , a capacitor and transistor coupled in series as shown in FIG. 4F , and a resistor and a capacitor and a transistor coupled together in series as shown in FIG. 4G .
- FIG. 5 is a flow chart which in conjunction with FIG. 3 , illustrates an exemplary method of the disclosure.
- the process begins in block 500 in which a gain state of a mixer, such as mixer 32 a, is determined, such as by the processor 323 .
- the mixer 32 a is coupled to the local oscillator (LO) system 300 which has a plurality of duty cycle (DC) modes, such as 25DC and 50DC modes.
- LO local oscillator
- DC duty cycle
- a duty cycle mode is selected, such as by the processor 323 , based on the determined gain state of the mixer 32 a.
- the duty cycle mode is selected based on the determined gained states of the mixers, such as mixers 32 a and 32 b.
- the first gain state of the selected mixer(s) comprises a high gain state and the second gain of the selected mixer(s) comprises a low gain state.
- the local oscillator system 300 is instructed, such as by the processor 323 , to operate in a selected first duty cycle mode based on a determined first gain state of the mixer 32 a.
- the local oscillator system 300 is instructed, such as by the processor 323 , to operate in a selected second duty cycle mode based on a determined second gain state of the mixer.
- the first duty cycle comprises a lower duty cycle rate than a duty cycle rate of the second duty cycle, such as 25DC and 50DC, respectively.
- FIG. 6 illustrates an exemplary embodiment of the disclosure, described in the context of a SAW-less CDMA transceiver system 609 for exemplary purposes only, but which can be used with other communication systems as well.
- the transceiver system 609 couples to an antenna 602 , such as a main antenna, which may be an external antenna, and is in communication with a mobile station modem (MSM) 620 , such as via path 640 .
- MSM 620 comprises a processor 623 which is in communication with a memory 622 which may be internal or external to MSM 620 .
- the transceiver system 609 includes a mixer 62 a, such as an active or passive mixer, with two or more mixer cores, such as mixer cores 610 and 611 , for down-converting a RF signal, such as a Quadrature (Q) signal.
- the RF signal is first received in antenna 602 , and then into the differential input terminals 60 a and 60 b of the low noise amplifier (LNA) 60 , whose output leads 61 a and 61 b are then coupled to the input leads 613 and 612 of mixer 62 a, respectively.
- LNA 60 is a variable gain amplifier.
- mixer cores 610 and 611 may be an active core or a passive core, such as a switching core.
- mixer 62 a comprises a passive mixer having no gain stage before the switching cores 610 and 611 , with mixer cores 610 and 611 each comprising a Gilbert Mixer having two cross-coupled switching elements, such as those described in conjunction with FIG. 3 .
- each of the mixer cores 610 and 611 have a plurality of input leads, such as input leads 601 and 602 for mixer core 610 , and input leads 603 and 604 for mixer core 611 .
- the input 612 of the mixer 62 a is coupled to the input leads 602 and 604 of the mixer cores 610 and 611 , respectively, and the input 613 of the mixer 62 a is coupled to the input leads 601 and 603 of the mixer cores 610 and 611 , respectively.
- the mixer 62 a also includes outputs 620 a and 620 b , and each of the mixer cores 610 and 611 having a pair of outputs, such as outputs 601 b and 602 b for the mixer core 610 , and 603 b and outputs 604 b for the mixer core 611 .
- the output 620 b of the mixer 62 a is coupled to the output leads 602 b and 604 b of the mixer cores 610 and 611 , respectively
- the output 620 a of the mixer 62 a is coupled to the output leads 601 b and 603 b of the mixer cores 610 and 611 , respectively.
- a degenerative impedance element is coupled to the input lead of each of mixer cores 610 and 611 , such as degenerative impedance elements 605 and 606 coupled to the input leads 601 and 602 of the mixer core 610 , respectively, and degenerative impedance elements 607 and 608 coupled to the input leads 603 and 604 of the mixer core 611 , respectively.
- the degenerative impedance elements 605 , 606 , 607 and 608 may be respectively coupled to the input leads 601 , 602 , 603 and 604 either internally to the mixer cores 610 and 611 , as shown, or externally (not shown) along their input paths 601 a, 602 a, 603 a and 604 a, respectively.
- mixer 62 a the number of mixer cores in the mixer 62 a were selected as two for simplicity of description, but that mixer 62 a can have more than two mixer cores.
- one of the mixer cores is of a different impedance value from the other mixer cores in the mixer 62 a, such as by a predetermined impedance ratio.
- degenerative impedance elements of one mixer core are different than the degenerative impedance element of the other mixer cores, such as by a predetermined impedance ratio.
- mixer core 610 is of a different impedance value than mixer core 611 , such as by a predetermined impedance ratio of mixer core 610 to mixer core 611 , with the degenerative impedance elements 605 and 606 of mixer core 610 being of different impedance value than the degenerative impedance elements 607 and 608 of mixer core 611 , such as by a predetermined impedance ratio.
- mixer core 610 is of a smaller impedance value than mixer core 611 , such as by having a larger physical size than mixer core 611 , such as by a predetermined size ratio of mixer core 610 to mixer core 611 .
- each of the degenerative impedance elements 605 , 606 , 607 and 608 may comprise of a resistor, a capacitor, a transistor, a resistor and a capacitor coupled in series, a resistor and a transistor coupled in series, a capacitor and transistor coupled in series, and a resistor and a capacitor and a transistor coupled together in series, as shown an described above in conjunction with FIG. 4A-G .
- the transceiver system 609 also includes a voltage controlled oscillator 69 for generating a down-converting voltage signal which is first buffered in buffer 68 , and then frequency divided by the frequency divider 67 , such as divided by two, before being fed into the local oscillator (LO) system 600 .
- the local oscillator (LO) system 600 has a plurality of duty cycle modes to generate a LO signal provided to the mixer 62 a.
- the local oscillator system 600 includes a multi-mode duty cycle (DC) generator 66 , such as a programmable 25/50DC generator, that output LO signals, such as via coupling lines 75 to a buffer system 66 a which provides buffered signals to the mixer 62 a.
- the duty cycle generator 66 is a programmable duty cycle generator.
- a controller such as processor 623 is then used to (a) operate a first mixer core, such as mixer core 611 , and the local oscillator system 600 in a first duty cycle mode, such as 25DC, based on a first the gain of the mixer 62 a, (b) operate either the mixer 62 a or a second mixer core, such as mixer core 610 , and the local oscillator system 600 in the first duty cycle mode, such as 25DC, based on a second gain of the mixer 62 a, and (c) operate the first mixer core, such as mixer core 611 , and the local oscillator system 600 in a second duty cycle mode, such as 50DC, based on a third gain of the mixer 62 a.
- the instructions from a controller, such as the processor 623 are received in the multi-mode duty cycle (DC) generator 66 which will then operate in the instructed duty cycle mode.
- DC multi-mode duty cycle
- buffer system 66 a includes input leads coupled to corresponding output leads of the duty cycle generator system 66 , such as via coupling lines 75 .
- Buffer system 66 a also includes a first set of output leads 63 a 1 and 63 a 2 coupled to a corresponding input leads 630 a and 630 b of mixer core 611 to provide the mixer 62 a with an LO signal corresponding to one of the duty cycles of the multi-mode duty cycle (DC) generator 66 .
- DC multi-mode duty cycle
- Buffer system 66 a also includes a second set of output leads 64 a 1 and 64 a 2 coupled to input leads of mixer core 610 to provide the mixer 62 a with a signal corresponding to the one of the duty cycles of multi-mode duty cycle (DC) generator 66 .
- Buffered signals are then provided by pairs 63 a 1 , 63 a 2 , and 64 a 1 , 64 a 2 to the switching elements of the mixer cores 611 and 610 , respectively, for down-converting of the RF signals received in the inputs leads 612 and 613 , to down-converted signals outputted from outputs 620 b and 620 a, respectively.
- the buffer system 66 a includes two sub-buffers (not shown), with each sub-buffer outputting from a different pair of the output leads of the buffer system 66 a, such as output leads 63 a 1 , 63 a 2 and 64 a 1 , 64 a 2 .
- the sub-buffers are of different sizes corresponding to the different sizes of the mixer cores 610 and 611 , and are selected based on a control signal received via control line 65 a from a controller, such as the processor 623 .
- Selection of a sub-buffer via control line 65 a enables the selected sub-buffer to provide to its corresponding mixer core an LO signal corresponding to one of the duty cycles of the multi-mode duty cycle (DC) generator 66 , whereas other mixer cores are not provided with an LO signal from their corresponding sub-buffers. For example if a sub-buffer corresponding to mixer core 610 is selected, the selected sub-buffer provides an LO signal to the mixer core 610 via output leads 64 a 1 and 64 a 2 , while no LO signal is provided via output leads 63 a 1 and 63 a 2 to the mixer core 611 by the other not selected sub-buffer.
- DC multi-mode duty cycle
- the transceiver system 609 may include additional mixers, such as a mixer 62 b, for down-converting additional signals, such as In-Phase (I) signals.
- each additional mixer such as mixer 62 b
- each additional mixer also has a plurality of mixer cores like mixer 62 a as described above, each with degenerative impedance elements coupled to their inputs and also receive LO signals from the local oscillator system 600 which then operates based on the gains states of the mixers, such as both mixers 62 a and 62 b.
- the local oscillator system 600 will also have additional buffer systems for the additional mixers, such as buffer system 66 b for mixer 62 b.
- the operation of the transceiver system 609 is described herein in detail only in the context of mixer 62 a, but can be readily applied to a configuration having more than one mixer.
- each mixer such as mixers 62 a and 62 b, may include more than two mixer cores and a corresponding number of sub-buffers of different sizes in theirs buffer systems 66 a and 66 b, respectively.
- the local oscillator (LO) system 600 generates a LO signal provided to the mixers. As described below and in greater detail in conjunction with FIG.
- a controller such as processor 623 , then: (a) operates corresponding first mixer cores in each of the mixers, and the local oscillator system 600 in a first duty cycle mode based on a first gain of the mixers, (b) operates the mixers or a corresponding second mixer cores in each of the mixers, and the local oscillator system 600 in the first duty cycle mode based on a second gain of the mixers, and (c) operates the corresponding first mixer cores in each of the mixers and the local oscillator system 600 in a second duty cycle mode based on a third gain of the mixers.
- FIG. 7 is a flow chart which in conjunction with FIG. 6 , illustrates another exemplary method of the disclosure.
- the process begins in block 700 in which is determined a gain state of a mixer, such as mixer 62 a, having a plurality of mixer cores, such as mixer cores 610 and 611 , and coupled to a local oscillator (LO) 600 which has a plurality of duty cycle (DC) modes, such as 25DC and 50DC modes.
- LO local oscillator
- DC duty cycle
- the determined gain state corresponds to a first, second, or third gain of the mixer.
- the first gain state of the mixer comprises a high gain state, such as a high gain low-linearly (G 0 LL) state in a CDMA 1x receiver
- the second gain of the mixer comprises a low gain state, such as a low gain high-linearly (G 0 HL) state in a CDMA 1x receiver
- the third gain state comprises a low gain state lower than the second gain of the mixer, such as a low gain state G1, G2 or G3 in CDMA 1x receiver.
- a mixer core in the mixer such as mixer core 610 or 611 , is selected, as well as a duty cycle mode of the local oscillator system 600 , such as 25DC or 50DC modes.
- the selection of the mixer core and duty cycle is performed by a controller, such as processor 623 .
- the local oscillator system 600 is then instructed by a controller, such as processor 623 , to operate in a low duty cycle mode, such as 25DC, and to provide a LO signal to a selected mixer core of the mixer, such as mixer core 611 .
- the selected mixer core such as mixer core 611 , comprises a larger impedance value than a non-selected mixer core, such as mixer core 610 .
- a controller instructs the duty cycle generator 66 to operate in a lower duty cycle mode, such as 25DC mode, based on a control signal received in the duty cycle generator 66 via control line 65 .
- a controller also instructs the buffer system 66 a based on a control signal received in the buffer system 66 a via control line 65 a, to provide LO signal to the selected mixer core by via either output leads 64 a 1 , 64 a 2 or 63 a 1 , 63 a 2 , depending on which mixer core is selected.
- LO signal is provided to a selected mixer core via one or more multiplexers (not shown) placed along paths to one or more inputs of one or more mixer cores, such as along paths to inputs 601 a, 602 a, 630 c and 630 d of mixer core 610 , based on instructions from a controller, such as processor 623 .
- the local oscillator system 600 is then instructed by a controller, such as processor 623 , to operate in a low duty cycle mode, such as 25DC, and to provide a LO signal to either the mixer 62 a by selecting both mixer cores 610 and 611 , or to just a selected mixer core.
- the selected mixer core such as mixer core 610
- the selected mixer core comprises a smaller impedance value than a non-selected mixer core, such as mixer core 611 .
- a controller instructs the duty cycle generator 66 to operate in a lower duty cycle mode, such as 25DC mode, based on a control signal received in the duty cycle generator 66 via control line 65 .
- a controller also instructs the buffer system 66 a based on a control signal received in the buffer system 66 a via control line 65 a, to provide LO signal to the selected mixer core by via either output leads 64 a 1 , 64 a 2 or 63 a 1 , 63 a 2 , depending on which mixer core is selected, or to both mixer cores if both mixer cores are selected.
- LO signal is provided to a selected mixer or mixer core via one or more multiplexers (not shown) placed along paths to one or more inputs of one or more mixer cores, such as along paths to inputs 601 a, 602 a, 630 c and 630 d of mixer core 610 , based on instructions from a controller, such as processor 623 .
- the local oscillator system 600 is then instructed by a controller, such as processor 623 , to operate in a higher duty cycle mode, such as 50DC, and to provide a LO signal to a selected mixer core.
- the selected mixer core such as mixer core 611 , comprises a larger impedance value than a non-selected mixer core, such as mixer core 610 .
- a controller instructs the duty cycle generator 66 to operate in a higher duty cycle mode, such as 50DC mode, based on a control signal received in the duty cycle generator 66 via control line 65 .
- a controller also instructs the buffer system 66 a based on a control signal received in the buffer system 66 a via control line 65 a, to provide LO signal to the selected mixer core by via either output leads 64 a 1 , 64 a 2 or 63 a 1 , 63 a 2 , depending on which mixer core is selected.
- LO signal is provided to a selected mixer or mixer core via one or more multiplexers (not shown) placed along paths to one or more inputs of one or more mixer cores, such as along paths to inputs 601 a, 602 a , 630 c and 630 d of mixer core 610 , based on instructions from a controller, such as processor 623 .
- a controller such as processor 623 .
- RF receivers with a 25DC local oscillators achieve higher gain if LNA consumes the same current.
- Higher gain in the receiver front end is highly desired for better noise-figure (NF) in RF receivers, especially in SAW-less ones which have no gm-cell, such as a gain stage before the mixer's switching core.
- NF noise-figure
- the most challenging NF is required only in high gain modes.
- low gain modes are the most power dominant modes. To reduce power consumption in low gain modes and still meet relaxed NF specifications will make RF receiver the more power efficient.
- One advantage of embodiments of the invention over the prior art is that by using a 25DC LO in high gain modes and a 50DC LO in low gain modes more power efficiency and achieved as well as better NF for high gain modes.
- DSP digital signal processor
- ASIC application specific integrated circuit
- FPGA field programmable gate array
- a general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
- a processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
- a software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
- An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium.
- the storage medium may be integral to the processor.
- the processor and the storage medium may reside in an ASIC.
- the ASIC may reside in a user terminal.
- the processor and the storage medium may reside as discrete components in a user terminal.
- the methods described above can be implemented in computer program product having a computer-readable medium with code for causing a computer to perform the above described processes.
- the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium.
- Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another.
- a storage media may be any available media that can be accessed by a general purpose or special purpose computer.
- such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium.
- Disk and disc includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
Abstract
An exemplary embodiment disclosed comprises a mixer having a plurality of input leads; a first degenerative impedance element coupled to a first input lead of the mixer; a second degenerative impedance element coupled to a second input lead of the mixer; and a local oscillator (LO) system comprising a plurality of duty cycle modes to generate a LO signal for the mixer, the local oscillator system operates in a first duty cycle based on a first gain state of the mixer, and in a second duty cycle based on a second gain state of the mixer.
Description
- This application is a divisional application of U.S. patent application Ser. No. 12/052,657 entitled “REDUCED POWER-CONSUMPTION RECEIVERS” filed Mar. 20, 2008 and assigned to the assignee hereof and hereby expressly incorporated by reference herein.
- The present disclosure relates generally to receivers, and more specifically to techniques for reducing power consumption in radio frequency (RF) receivers.
- In a communication system, a receiver receives a radio-frequency (RF) signal from a transmitter, and down-converts the received signal from RF to base-band using one or more mixers. Each mixer mixes the received signal with a local oscillator (LO) signal. An LO buffer is typically provided to buffer the LO signal before the mixer.
- There are several different circuit topologies for realizing a wireless device receiver. Some topologies involve a surface acoustic-wave (SAW) filter that is disposed in the incoming RF signal path between a low-noise amplifier (LNA) and a mixer. It is desirable to be able to realize a wireless device receiver of adequate performance without using the somewhat costly and large SAW device. In order to achieve good linearity in a SAW-less receiver, a purely passive down-converting mixer is sometimes used. The passive mixer does not have an active gm-cell, such as a gain stage before the mixer's switching core. It is, however, often difficult for this topology to meet demanding noise figure (NF) requirements while still achieving good linearity (e.g., triple beat) performance.
- One current approach to achieve good NF performance is to use a 25-duty-cycle (25DC) LO in RF receivers for better gain. Another approach is the use of a higher duty-cycle LO, such as a 50DC LO, which reduces power consumption compared to a 25DC but comes at the cost of reduced gain.
- Accordingly, there is a need in the art for reducing the power consumption in receivers of wireless devices while maintaining acceptable NF.
-
FIG. 1 illustrates an exemplary wireless communication environment in which exemplary embodiments of the disclosure can be practiced. -
FIG. 2 illustrates an exemplary wireless device using prior art techniques. -
FIG. 3 illustrates an exemplary embodiment of the disclosure. -
FIGS. 4A-G are exemplary circuit diagrams of degenerative impedance elements used in conjunction with the exemplary embodiments of the disclosure. -
FIG. 5 is a flow chart illustrating an exemplary method of the disclosure. -
FIG. 6 illustrates another exemplary embodiment of the disclosure. -
FIG. 7 is a flow chart illustrating another exemplary method of the disclosure. - The techniques described herein are applicable to and may be used for any electronic setting in any electrical or electronic environment in which radio frequency reception is desired. For exemplary purposes only, the exemplary embodiments described herein are presented in the context of a wireless communication environment, though they are not meant to be limited to such, but applicable to any wire or wireless communication setting which use radio-frequency transmission and reception, such as cell-phones, base-stations as well as cable set-top boxes and the likes.
- The techniques described herein may be used for various wireless communication networks such as wireless communication networks such as CDMA, TDMA, FDMA, OFDMA and SC-FDMA networks. The terms “network” and “system” are often used interchangeably. A CDMA network may implement a radio technology such as Universal Terrestrial Radio Access (UTRA), cdma2000, etc. UTRA includes Wideband-CDMA (W-CDMA), Low Chip Rate (LCR), High Chip Rate (HCR), etc. CDMA2000 covers IS-2000, IS-95, and IS-856 standards. A TDMA network may implement a radio technology such as Global System for Mobile Communications (GSM). An OFDMA network may implement a radio technology such as Evolved UTRA (E-UTRA), Ultra Mobile Broadband (UMB), IEEE 802.11 (Wi-Fi), IEEE 802.16 (WiMAX), IEEE 802.20, Flash-OFDM®, etc. These various radio technologies and standards are known in the art. UTRA, E-UTRA and GSM are described in documents from an organization named “3rd Generation Partnership Project” (3GPP). CDMA2000 is described in documents from an organization named “3rd Generation Partnership Project 2” (3GPP2). 3GPP and 3GPP2 documents are publicly available. For clarity, certain aspects of the techniques are described below for 3GPP networks.
- The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.
-
FIG. 1 illustrates an exemplarywireless communication environment 1 comprisingcommunication systems wireless device 110, such as a multi-antenna wireless device capable of communicating with multiplewireless communication systems Wireless system 120 may be a CDMA system that may implement one or more CDMA standards such as, e.g., IS-2000 (commonly referred to as CDMA 1x), IS-856 (commonly referred to as CDMA 1x EV-DO), IS-95, W-CDMA, and so on.Wireless system 120 includes a base transceiver system (BTS) 130 and a mobile switching center (MSC) 140. BTS 130 provides over-the-air communication for wireless devices under its coverage area. MSC 140 couples to BTSs inwireless system 120 and provides coordination and control for these BTSs.Wireless system 122 may be a TDMA system that may implement one or more TDMA standards such as, e.g., GSM.Wireless system 122 includes a NodeB 132 and a radio network controller (RNC) 142. Node B 132 provides over-the-air communication for wireless devices under its coverage area.RNC 142 couples to Node Bs inwireless system 122 and provides coordination and control for these Node Bs. In general, BTS 130 and Node B 132 are fixed stations that provide communication coverage for wireless devices and may also be referred to as base stations or some other terminology. MSC 140 and RNC 142 are network entities that provide coordination and control for the base stations and may also be referred to by other terminologies. -
Wireless device 110 may be a cellular phone, a personal digital assistant (PDA), a wireless-enabled computer, or some other wireless communication unit or device.Wireless device 110 may also be referred to as a mobile station (3GPP2 terminology), a user equipment (UE) (3GPP terminology), an access terminal, or some other terminology.Wireless device 110 is equipped with multiple antennas, e.g., one external antenna and one or more internal antennas. The multiple antennas may be used to provide diversity against deleterious path effects such as fading, multipath, interference, and so on. An RF modulated signal transmitted from an antenna at a transmitting entity may reach the multiple antennas atwireless device 110 via line-of-sight paths and/or reflected paths. At least one propagation path typically exists between the transmit antenna and each receive antenna atwireless device 110. If the propagation paths for different receive antennas are independent, which is generally true to at least an extent, then diversity increases and the received signal quality improves when multiple antennas are used to receive the RF modulated signal. -
Wireless device 110 may or may not be capable of receiving signals from satellites 150. Satellites 150 may belong to a satellite positioning system such as the well-known Global Positioning System (GPS), the European Galileo system, or some other systems. Each GPS satellite transmits a GPS signal encoded with information that allows a GPS receiver on Earth to measure the time of arrival (TOA) of the GPS signal. Measurements for a sufficient number of GPS satellites may be used to obtain an accurate three-dimensional position estimate for the GPS receiver. In general, thewireless device 110 may be capable of communicating with any number of wireless systems of different wireless technologies (e.g., CDMA, GSM, GPS, and so on). -
FIG. 2 is a block diagram illustrating anexemplary wireless device 110.Wireless device 110 includes atransceiver system 210, such as a SAW-less transceiver, which at one end couples to anantenna 202, such as a main antenna, which may be an external antenna, and at the other end is in communication with a mobile station modem (MSM) 220, such as viapath 240.MSM 220 comprises aprocessor 224 which is in communication with amemory 222. - As shown in
FIG. 2 , an incoming RF signal received inantenna 202 is received into thedifferential input terminals LNA 20 amplifies the RF signal and drives differential signals from output leads 21 a and 21 b. Output leads 21 a and 21 b ofLNA 20 are coupled to the inputs ofmixers Q. Output lead 21 a is coupled to a first differential input lead 22 a 2 ofmixer 22 a, andoutput lead 21 b is coupled to a second differential input lead 22 a 1 ofmixer 22 a. In an exemplary embodiment,mixer 22 a comprises a passive mixer having no active gm-cell, such as a gain stage before the mixer's switching core. In the exemplary embodiment shown inFIG. 2 , themixer 22 a is a Gilbert Mixer which includes twocross-coupled switching elements 22 a 3 and 22 a 4, such as field effect transistors (FET), and whose configuration and operation is well known in the art. Similarly,Output lead 21 a is coupled to a firstdifferential input lead 22b 1 ofmixer 22 b, andoutput lead 21 b is coupled to a seconddifferential input lead 22b 2 ofmixer 22 b. In an exemplary embodiment,mixer 22 b comprises a passive mixer having no active gm-cell, such as a gain stage before the mixer's switching core, and likemixer 22 a comprises a Gilbert Mixer having two cross-coupled switching elements. - The
transceiver system 210 also includes a voltage controlledoscillator 29 for generating a down-converting voltage signal which is first buffered inbuffer 28, and then frequency divided by thefrequency divider 27, such as divided by two. The output of thefrequency divider 27 is then fed into the 25 duty cycle (DC)generator 26, which outputs 25DC signals 25 a and 25 b tobuffers Buffers b 1, 23b 2 to themixers Mixers b 1, 23b 2 with the RF signals received in theirinputs 22 a 1, 22 a 2 and 22b b 2, to generate down-converted Quadrature (Q) signals 50 a 1, 50 a 2 and In-phase (I) signals 50b 1, 50b 2, respectively. The down-converted I and Q signals are then provided to theMSM 220, such as viapath 240. - As described above, a shortcoming in the
above transceiver system 210 is that a 25DC LO consumes relatively high current resulting in higher consumption of power. Usage of a higher duty-cycle LO, such as a 50DC LO, however, can reduce power consumption but comes at the cost of reduced gain, resulting in degraded noise figure performance. -
FIG. 3 illustrates an exemplary embodiment of the disclosure, described in the context of a SAW-lessGSM transceiver system 310 for exemplary purposes only, but which can be used with other communication systems as well. As shown inFIG. 3 , thetransceiver system 310 couples to anantenna 302, such as a main antenna, which may be an external antenna, and is in communication with a mobile station modem (MSM) 320, such as viapath 330.MSM 320 comprises aprocessor 323 which is in communication with amemory 322 which may be internal toMSM 320 as shown, or external to MSM 320 (not shown). - As shown in
FIG. 3 , thetransceiver system 310 includes amixer 32 a, such as an active or passive mixer, for down-converting a RF signal, such as an Quadrature (Q) signal, first received onantenna 302, and then into thedifferential input terminals mixer 32 a. In an exemplary embodiment,LNA 30 is a variable gain amplifier. In an exemplary embodiment,mixer 32 a comprises a passive mixer having no active gm-cell, such as a gain stage before the mixer's switching core. In the exemplary embodiment shown inFIG. 3 ,mixer 32 a is a Gilbert Mixer which includes twocross-coupled switching elements 32 a 3 and 32 a 4, each having a plurality of transistors, such as field effect transistors (FET).Mixer 32 a includes input leads 301 and 302, with degenerative impedance elements, such as 304 and 305, coupled to the input leads 301 and 302, respectively. In an exemplary embodiment, thedegenerative impedance elements degenerative impedance elements mixer 32 a, as shown, or externally (not shown) along theinput paths - The
transceiver system 310 further includes a local oscillator (LO)system 300 having a plurality of duty cycle modes to generate a LO signal for themixer 32 a. Thelocal oscillator system 300 includes a multi-mode duty cycle (DC)generator 36, such as a programmable 25/50DC generator, that output LO signals 35 a to abuffer 33 a. Buffered signals 33 a 1 and 33 a 2 are then respectively provided to theswitching elements 32 a 4 and 32 a 3 of themixer 32 a for down-converting of the RF signals received in the inputs leads 301 and 302, to down-converted signals outputted from output paths 70 a 2 and 70 a 1, respectively. - As described below in greater detail in conjunction with
FIG. 5 , thelocal oscillator system 300 operates in a first duty cycle based on a first gain state of themixer 32 a, and in a second duty cycle based on a second gain state of themixer 32 a. In an exemplary embodiment, acontrol signal 51 is received in thelocal oscillator system 300, such as from theprocessor 322, to provide instruction to theduty cycle generator 36 as to which duty cycle to operate in. In an exemplary embodiment, theduty cycle generator 36 is a programmable duty cycle generator. Thetransceiver system 310 also includes a voltage controlledoscillator 39 for generating a down-converting voltage signal which is then first buffered inbuffer 38, and then frequency divided by thefrequency divider 37, such as divided by two, before being fed into thelocal oscillator system 300. - As shown in
FIG. 3 , thetransceiver system 310 may include additional mixers, such as amixer 32 b, for down-converting additional signals, such as In-Phase (I) signals. In an exemplary embodiment, each additional mixer, such asmixer 32 b, also have degenerative impedance elements coupled to its inputs and also receives LO signals from thelocal oscillator system 300, having additional buffers, such asbuffer 33 b, which then operates based on the gains states of the mixers, such as bothmixers transceiver system 310 is described herein in detail only in the context ofmixer 32 a, but can be readily applied to a configuration having more than one mixer, such asmixers -
FIGS. 4A-G are exemplary circuit diagrams ofdegenerative impedance elements 61, with input leads 41, which may be used as degenerative impedance elements, such as 304 and 305, in the exemplary embodiments of the disclosure. In an exemplary embodiment, adegenerative impedance element 61 may include a resistor as shown inFIG. 4A , a capacitor as shown inFIG. 4B , a transistor as shown inFIG. 4C , a resistor and a capacitor coupled in series as shown inFIG. 4D , a resistor and a transistor coupled in series as shown inFIG. 4E , a capacitor and transistor coupled in series as shown inFIG. 4F , and a resistor and a capacitor and a transistor coupled together in series as shown inFIG. 4G . -
FIG. 5 is a flow chart which in conjunction withFIG. 3 , illustrates an exemplary method of the disclosure. The process begins inblock 500 in which a gain state of a mixer, such asmixer 32 a, is determined, such as by theprocessor 323. Themixer 32 a is coupled to the local oscillator (LO)system 300 which has a plurality of duty cycle (DC) modes, such as 25DC and 50DC modes. Next, inblock 510, a duty cycle mode is selected, such as by theprocessor 323, based on the determined gain state of themixer 32 a. In a configuration in whichtransceiver system 310 includes more than one mixer, such asmixers mixers - Next, in
block 520, thelocal oscillator system 300 is instructed, such as by theprocessor 323, to operate in a selected first duty cycle mode based on a determined first gain state of themixer 32 a. Next, inblock 530, thelocal oscillator system 300 is instructed, such as by theprocessor 323, to operate in a selected second duty cycle mode based on a determined second gain state of the mixer. In an exemplary embodiment, the first duty cycle comprises a lower duty cycle rate than a duty cycle rate of the second duty cycle, such as 25DC and 50DC, respectively. The overall flow then ends. -
FIG. 6 illustrates an exemplary embodiment of the disclosure, described in the context of a SAW-lessCDMA transceiver system 609 for exemplary purposes only, but which can be used with other communication systems as well. As shown inFIG. 6 thetransceiver system 609 couples to anantenna 602, such as a main antenna, which may be an external antenna, and is in communication with a mobile station modem (MSM) 620, such as viapath 640.MSM 620 comprises aprocessor 623 which is in communication with amemory 622 which may be internal or external toMSM 620. - As shown in
FIG. 6 , thetransceiver system 609 includes amixer 62 a, such as an active or passive mixer, with two or more mixer cores, such asmixer cores antenna 602, and then into thedifferential input terminals mixer 62 a, respectively. In an exemplary embodiment,LNA 60 is a variable gain amplifier. In an exemplary embodiment, one or more of themixer cores FIG. 6 ,mixer 62 a comprises a passive mixer having no gain stage before the switchingcores mixer cores FIG. 3 . - As shown in
FIG. 6 , each of themixer cores mixer core 610, and input leads 603 and 604 formixer core 611. In an exemplary embodiment, theinput 612 of themixer 62 a is coupled to the input leads 602 and 604 of themixer cores input 613 of themixer 62 a is coupled to the input leads 601 and 603 of themixer cores mixer 62 a also includesoutputs mixer cores outputs mixer core mixer core 611. In an exemplary embodiment, theoutput 620 b of themixer 62 a is coupled to the output leads 602 b and 604 b of themixer cores output 620 a of themixer 62 a is coupled to the output leads 601 b and 603 b of themixer cores - Next, a degenerative impedance element is coupled to the input lead of each of
mixer cores degenerative impedance elements mixer core 610, respectively, anddegenerative impedance elements 607 and 608 coupled to the input leads 603 and 604 of themixer core 611, respectively. Thedegenerative impedance elements mixer cores input paths - It should be noted that the number of mixer cores in the
mixer 62 a were selected as two for simplicity of description, but thatmixer 62 a can have more than two mixer cores. In an exemplary embodiment, one of the mixer cores is of a different impedance value from the other mixer cores in themixer 62 a, such as by a predetermined impedance ratio. In an exemplary embodiment, degenerative impedance elements of one mixer core are different than the degenerative impedance element of the other mixer cores, such as by a predetermined impedance ratio. - In the exemplary embodiment shown in
FIG. 6 ,mixer core 610 is of a different impedance value thanmixer core 611, such as by a predetermined impedance ratio ofmixer core 610 tomixer core 611, with thedegenerative impedance elements mixer core 610 being of different impedance value than thedegenerative impedance elements 607 and 608 ofmixer core 611, such as by a predetermined impedance ratio. In an exemplary embodiment,mixer core 610 is of a smaller impedance value thanmixer core 611, such as by having a larger physical size thanmixer core 611, such as by a predetermined size ratio ofmixer core 610 tomixer core 611. - In an exemplary embodiment, each of the
degenerative impedance elements FIG. 4A-G . - As shown in
FIG. 6 , thetransceiver system 609 also includes a voltage controlledoscillator 69 for generating a down-converting voltage signal which is first buffered inbuffer 68, and then frequency divided by thefrequency divider 67, such as divided by two, before being fed into the local oscillator (LO)system 600. The local oscillator (LO)system 600 has a plurality of duty cycle modes to generate a LO signal provided to themixer 62 a. Thelocal oscillator system 600 includes a multi-mode duty cycle (DC)generator 66, such as a programmable 25/50DC generator, that output LO signals, such as viacoupling lines 75 to abuffer system 66 a which provides buffered signals to themixer 62 a. In an exemplary embodiment, theduty cycle generator 66 is a programmable duty cycle generator. - As described in greater detail in conjunction with
FIG. 7 , a controller, such asprocessor 623 is then used to (a) operate a first mixer core, such asmixer core 611, and thelocal oscillator system 600 in a first duty cycle mode, such as 25DC, based on a first the gain of themixer 62 a, (b) operate either themixer 62 a or a second mixer core, such asmixer core 610, and thelocal oscillator system 600 in the first duty cycle mode, such as 25DC, based on a second gain of themixer 62 a, and (c) operate the first mixer core, such asmixer core 611, and thelocal oscillator system 600 in a second duty cycle mode, such as 50DC, based on a third gain of themixer 62 a. The instructions from a controller, such as theprocessor 623 are received in the multi-mode duty cycle (DC)generator 66 which will then operate in the instructed duty cycle mode. - In an exemplary embodiment,
buffer system 66 a includes input leads coupled to corresponding output leads of the dutycycle generator system 66, such as via coupling lines 75.Buffer system 66 a also includes a first set of output leads 63 a 1 and 63 a 2 coupled to a corresponding input leads 630 a and 630 b ofmixer core 611 to provide themixer 62 a with an LO signal corresponding to one of the duty cycles of the multi-mode duty cycle (DC)generator 66.Buffer system 66 a also includes a second set of output leads 64 a 1 and 64 a 2 coupled to input leads ofmixer core 610 to provide themixer 62 a with a signal corresponding to the one of the duty cycles of multi-mode duty cycle (DC)generator 66. Buffered signals are then provided by pairs 63 a 1, 63 a 2, and 64 a 1, 64 a 2 to the switching elements of themixer cores outputs - In an exemplary embodiment, the
buffer system 66 a includes two sub-buffers (not shown), with each sub-buffer outputting from a different pair of the output leads of thebuffer system 66 a, such as output leads 63 a 1, 63 a 2 and 64 a 1, 64 a 2. In an exemplary embodiment, the sub-buffers are of different sizes corresponding to the different sizes of themixer cores control line 65 a from a controller, such as theprocessor 623. Selection of a sub-buffer viacontrol line 65 a enables the selected sub-buffer to provide to its corresponding mixer core an LO signal corresponding to one of the duty cycles of the multi-mode duty cycle (DC)generator 66, whereas other mixer cores are not provided with an LO signal from their corresponding sub-buffers. For example if a sub-buffer corresponding tomixer core 610 is selected, the selected sub-buffer provides an LO signal to themixer core 610 via output leads 64 a 1 and 64 a 2, while no LO signal is provided via output leads 63 a 1 and 63 a 2 to themixer core 611 by the other not selected sub-buffer. - As shown in
FIG. 6 , thetransceiver system 609 may include additional mixers, such as amixer 62 b, for down-converting additional signals, such as In-Phase (I) signals. In an exemplary embodiment, each additional mixer, such asmixer 62 b, also has a plurality of mixer cores likemixer 62 a as described above, each with degenerative impedance elements coupled to their inputs and also receive LO signals from thelocal oscillator system 600 which then operates based on the gains states of the mixers, such as bothmixers local oscillator system 600 will also have additional buffer systems for the additional mixers, such asbuffer system 66 b formixer 62 b. For simplicity, the operation of thetransceiver system 609 is described herein in detail only in the context ofmixer 62 a, but can be readily applied to a configuration having more than one mixer. - In addition, each mixer, such as
mixers buffer systems system 600 generates a LO signal provided to the mixers. As described below and in greater detail in conjunction withFIG. 7 , a controller, such asprocessor 623, then: (a) operates corresponding first mixer cores in each of the mixers, and thelocal oscillator system 600 in a first duty cycle mode based on a first gain of the mixers, (b) operates the mixers or a corresponding second mixer cores in each of the mixers, and thelocal oscillator system 600 in the first duty cycle mode based on a second gain of the mixers, and (c) operates the corresponding first mixer cores in each of the mixers and thelocal oscillator system 600 in a second duty cycle mode based on a third gain of the mixers. -
FIG. 7 is a flow chart which in conjunction withFIG. 6 , illustrates another exemplary method of the disclosure. The process begins inblock 700 in which is determined a gain state of a mixer, such asmixer 62 a, having a plurality of mixer cores, such asmixer cores - In an exemplary embodiment, the first gain state of the mixer comprises a high gain state, such as a high gain low-linearly (G0LL) state in a CDMA 1x receiver, the second gain of the mixer comprises a low gain state, such as a low gain high-linearly (G0HL) state in a CDMA 1x receiver, and the third gain state comprises a low gain state lower than the second gain of the mixer, such as a low gain state G1, G2 or G3 in CDMA 1x receiver.
- Next, in
block 710, based on the determined gain state of the mixer, such asmixer 62 a, a mixer core in the mixer, such asmixer core local oscillator system 600, such as 25DC or 50DC modes. In an exemplary embodiment, the selection of the mixer core and duty cycle is performed by a controller, such asprocessor 623. - Next, in
block 720, if the mixer, such asmixer 62 a, is determined to be in the first gain state, such as in a high gain low-linearly (G0LL) state in a CDMA 1x receiver, thelocal oscillator system 600 is then instructed by a controller, such asprocessor 623, to operate in a low duty cycle mode, such as 25DC, and to provide a LO signal to a selected mixer core of the mixer, such asmixer core 611. In an exemplary embodiment, the selected mixer core, such asmixer core 611, comprises a larger impedance value than a non-selected mixer core, such asmixer core 610. A controller, such asprocessor 623, instructs theduty cycle generator 66 to operate in a lower duty cycle mode, such as 25DC mode, based on a control signal received in theduty cycle generator 66 viacontrol line 65. A controller, such asprocessor 623, also instructs thebuffer system 66 a based on a control signal received in thebuffer system 66 a viacontrol line 65 a, to provide LO signal to the selected mixer core by via either output leads 64 a 1, 64 a 2 or 63 a 1, 63 a 2, depending on which mixer core is selected. In another exemplary embodiment, LO signal is provided to a selected mixer core via one or more multiplexers (not shown) placed along paths to one or more inputs of one or more mixer cores, such as along paths toinputs mixer core 610, based on instructions from a controller, such asprocessor 623. - Next, in
block 730, if the mixer, such asmixer 62 a, is determined to be in the second gain state, such as a low gain high-linearly (G0HL) state in a CDMA 1x receiver, thelocal oscillator system 600 is then instructed by a controller, such asprocessor 623, to operate in a low duty cycle mode, such as 25DC, and to provide a LO signal to either themixer 62 a by selecting bothmixer cores mixer core 610, comprises a smaller impedance value than a non-selected mixer core, such asmixer core 611. A controller, such asprocessor 623, instructs theduty cycle generator 66 to operate in a lower duty cycle mode, such as 25DC mode, based on a control signal received in theduty cycle generator 66 viacontrol line 65. A controller, such asprocessor 623, also instructs thebuffer system 66 a based on a control signal received in thebuffer system 66 a viacontrol line 65 a, to provide LO signal to the selected mixer core by via either output leads 64 a 1, 64 a 2 or 63 a 1, 63 a 2, depending on which mixer core is selected, or to both mixer cores if both mixer cores are selected. In another exemplary embodiment, LO signal is provided to a selected mixer or mixer core via one or more multiplexers (not shown) placed along paths to one or more inputs of one or more mixer cores, such as along paths toinputs mixer core 610, based on instructions from a controller, such asprocessor 623. - Next, in
block 730, if the mixer, such asmixer 62 a, is determined to be in the third gain state, such as a low gain state G1, G2 or G3 in CDMA 1x receiver, thelocal oscillator system 600 is then instructed by a controller, such asprocessor 623, to operate in a higher duty cycle mode, such as 50DC, and to provide a LO signal to a selected mixer core. In an exemplary embodiment, the selected mixer core, such asmixer core 611, comprises a larger impedance value than a non-selected mixer core, such asmixer core 610. A controller, such asprocessor 623, instructs theduty cycle generator 66 to operate in a higher duty cycle mode, such as 50DC mode, based on a control signal received in theduty cycle generator 66 viacontrol line 65. A controller, such asprocessor 623, also instructs thebuffer system 66 a based on a control signal received in thebuffer system 66 a viacontrol line 65 a, to provide LO signal to the selected mixer core by via either output leads 64 a 1, 64 a 2 or 63 a 1, 63 a 2, depending on which mixer core is selected. In another exemplary embodiment, LO signal is provided to a selected mixer or mixer core via one or more multiplexers (not shown) placed along paths to one or more inputs of one or more mixer cores, such as along paths toinputs mixer core 610, based on instructions from a controller, such asprocessor 623. The overall flow then ends. - Compared to 50DC local oscillators, RF receivers with a 25DC local oscillators achieve higher gain if LNA consumes the same current. Higher gain in the receiver front end is highly desired for better noise-figure (NF) in RF receivers, especially in SAW-less ones which have no gm-cell, such as a gain stage before the mixer's switching core. In most wireless communication systems, the most challenging NF is required only in high gain modes. One the other hand, low gain modes are the most power dominant modes. To reduce power consumption in low gain modes and still meet relaxed NF specifications will make RF receiver the more power efficient. One advantage of embodiments of the invention over the prior art is that by using a 25DC LO in high gain modes and a 50DC LO in low gain modes more power efficiency and achieved as well as better NF for high gain modes.
- It should be noted that the various exemplary embodiments were discussed separately for purposes of illustrations, but that they may be combined in one embodiment having some or all of the features of the separately illustrated embodiments.
- Those of skill in the art would understand that information and signals may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
- The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
- The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.
- It should be noted that the methods described above can be implemented in computer program product having a computer-readable medium with code for causing a computer to perform the above described processes. In one or more exemplary embodiments, the functions described may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.
- The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples and designs described herein but are to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. An apparatus comprising:
a mixer having a plurality of input leads;
a first degenerative impedance element coupled to a first input lead of the mixer;
a second degenerative impedance element coupled to a second input lead of the mixer; and
a local oscillator (LO) system comprising a plurality of duty cycle modes to generate a LO signal for the mixer, the local oscillator system operates in a first duty cycle based on a first gain state of the mixer, and in a second duty cycle based on a second gain state of the mixer.
2. The apparatus of claim 1 , wherein the first gain state of the mixer comprises a high gain state and the second gain of the mixer comprises a low gain state.
3. The apparatus of claim 1 , wherein the first duty cycle comprises a lower duty cycle rate than a duty cycle rate of the second duty cycle.
4. The apparatus of claim 1 , wherein each of the first and the second degenerative impedance elements comprising at least one of a resistor, a capacitor, a transistor, a resistor and a capacitor coupled in series, a resistor and a transistor coupled in series, a capacitor and transistor coupled in series, and a resistor and a capacitor and a transistor coupled together in series.
5. The apparatus of claim 1 , wherein the mixer comprises a plurality of mixers each having a plurality of input leads with each lead coupled to a different degenerative impedance element, wherein the LO system generates the LO signal for the plurality of mixers, and wherein the local oscillator operates in the first duty cycle based on the first gain state of the plurality of mixers, and in the second duty cycle based on the second gain state of the plurality of mixers.
6. A method comprising:
determining a gain state of a mixer coupled to a local oscillator (LO) having a plurality of duty cycle modes, wherein the determined gain state corresponds to at least one of a first and second gains of the mixer;
selecting a duty cycle mode from the plurality of duty cycle modes of the local oscillator system based on the determined gain state of the mixer;
instructing the local oscillator system to operate in a selected first duty cycle mode based on a determined first gain state of the mixer; and
instructing the local oscillator system to operate in a selected second duty cycle mode based on a determined second gain state of the mixer.
7. A computer program product comprising:
computer-readable medium comprising:
code for causing a computer to determine a gain state of a mixer coupled to a local oscillator (LO) having a plurality of duty cycle modes, wherein the determined gain state corresponds to at least one of a first and second gains of the mixer;
code for causing the computer to select a duty cycle mode from the plurality of duty cycle modes of the local oscillator system based on the determined gain state of the mixer;
code for causing the computer to instruct the local oscillator system to operate in a selected first duty cycle mode based on a determined first gain state of the mixer; and
code for causing the computer to instruct the local oscillator system to operate in a selected second duty cycle mode based on a determined second gain state of the mixer.
8. An apparatus comprising:
means for determining a gain state of a mixer coupled to a local oscillator (LO) having a plurality of duty cycle modes, wherein the determined gain state corresponds to at least one of a first and second gains of the mixer;
means for selecting a duty cycle mode from the plurality of duty cycle modes of the local oscillator system based on the determined gain state of the mixer; and
means for instructing the local oscillator system to operate in a selected first duty cycle mode based on a determined first gain state of the mixer; and to operate in a selected second duty cycle mode based on a determined second gain state of the mixer.
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- 2009-03-20 EP EP09721725A patent/EP2279565A1/en not_active Withdrawn
- 2009-03-20 JP JP2011501001A patent/JP2011515967A/en not_active Ceased
-
2013
- 2013-07-19 JP JP2013150974A patent/JP2013255255A/en active Pending
- 2013-12-18 US US14/133,280 patent/US20140105336A1/en not_active Abandoned
Patent Citations (2)
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US20010021645A1 (en) * | 2000-03-08 | 2001-09-13 | Nippon Telegraph And Telephone Corporation | Mixer circuit |
US8041327B2 (en) * | 2006-03-16 | 2011-10-18 | Newport Media, Inc. | Wideband resistive input mixer with noise-cancelled impedance |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20090075620A1 (en) * | 2007-09-14 | 2009-03-19 | Qualcomm Incorporated | Local oscillator buffer and mixer having adjustable size |
US8929840B2 (en) | 2007-09-14 | 2015-01-06 | Qualcomm Incorporated | Local oscillator buffer and mixer having adjustable size |
WO2020256331A1 (en) * | 2019-06-18 | 2020-12-24 | Samsung Electronics Co., Ltd. | Structure of electronic device for optimizing performance of antenna and method thereof |
KR20200144241A (en) * | 2019-06-18 | 2020-12-29 | 삼성전자주식회사 | Structure of electronic device for optimizing performance of antenna and method thereof |
US11063358B2 (en) | 2019-06-18 | 2021-07-13 | Samsung Electronics Co., Ltd. | Structure of electronic device for optimizing performance of antenna and method thereof |
KR102608378B1 (en) | 2019-06-18 | 2023-12-01 | 삼성전자주식회사 | Structure of electronic device for optimizing performance of antenna and method thereof |
Also Published As
Publication number | Publication date |
---|---|
EP2279565A1 (en) | 2011-02-02 |
CN102037655A (en) | 2011-04-27 |
JP2013255255A (en) | 2013-12-19 |
KR101157438B1 (en) | 2012-07-13 |
WO2009117707A1 (en) | 2009-09-24 |
US8639205B2 (en) | 2014-01-28 |
KR20100124828A (en) | 2010-11-29 |
TW201001936A (en) | 2010-01-01 |
US20090239592A1 (en) | 2009-09-24 |
JP2011515967A (en) | 2011-05-19 |
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