JPH05343923A - Semiconductor device - Google Patents

Abstract

PURPOSE:To form an impedance variable element having a large impedance change difficult of being realized by a bipolar transistor(TR) in the same process by employing a FET for the impedance variable element. CONSTITUTION:When a high frequency signal is fed to terminals 103, 104, 105, 106, a large current flows to FETs 1-4 and a small current flows to FETs 5-8. The difference current flows to a constant current source comprising an FET 11 through an FET 9. Thus, for example, in a pair of the FETs 1, 2, the FET 2 is turned on by a large signal input and the FET1 is turned off. Similarly, in a pair of the FETs 5, 6, the FET 6 is turned off by a large signal input and the FET5 is turned on. Thus, an input level of a local signal is decreased equivalently by the bypass of the FET 9 and the conversion gain is reduced. Then, the conversion gain is changed by changing the impedance of the bypass and the gain control variable is increased by a large impedance change. Thus, no special variable impedance element is required.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using GaAs MESFET.

[0002]

2. Description of the Related Art In recent years, a semiconductor device which operates at a low voltage has been demanded for low power driving. As a conventional variable conversion gain mixer, there is, for example, one in which a variable impedance element is added to a double balanced differential amplifier as shown in FIG. 3 (for example, Japanese Patent Application No. 3-118710).

In FIG. 3, 31 to 34 are FETs used as switching elements, 35 and 36 are FETs operating as a source coupling pair, and 37 and 38.
Is a constant current source, 39 is an FET used as a variable impedance element, and 40 is a gain control terminal 307.
The resistor is inserted so that a large current does not flow to the gate of the FET 39 due to the voltage applied to the gate of the FET 39. Terminal 30 here
A local signal is input between terminals 3 and 304 and terminals 305, 30
By inputting an RF signal between 6 terminals 301, 30
An IF signal having a frequency that is the sum or difference of the local signal frequency and the RF signal frequency is obtained between the two. Here, the load inserted between the terminals 301 and 302 and the power supply is omitted in the drawing.

The frequency mixing is performed by the switching elements of the FETs 31 to 34, and the FETs are fed by the local signal.
The RF signal and the local signal are multiplied by repeating ON and OFF of 31, 34 and FETs 32, 33.

The conversion gain of this circuit is FET35,
It is determined by the gain of the source-coupled pair of 36, which is determined by the resistance of the FET 39. This is because the resistance of the FET 39 acts as a non-feedback resistance, and when the resistance is large, the gain is low, and when the resistance is small, the gain is high.

[0006]

However, the conventional double-balanced differential amplifier has a problem that it is difficult to operate at a low voltage because the double-balanced differential amplifier includes three stages when a constant current source is included. It was

In view of the above problems, it is an object of the present invention to provide a semiconductor device having the function of a conversion gain variable mixer and capable of low voltage operation.

[0008]

In order to solve the above problems, a semiconductor device of the present invention comprises nine FETs and two constant current sources, and a drain of the first FET and a second FET. FE
Drain of T and drain of 7th FET and 8th FET
Of the third FET as the first signal terminal, the drain of the third FET, the drain of the fourth FET, the drain of the fifth FET and the drain of the sixth FET as the second signal terminal, and the drain of the second FET of The gate and the gate of the third FET are used as the third signal terminal, the gate of the sixth FET and the gate of the seventh FET are used as the fourth signal terminal, and the gate of the first FET and the gate of the fifth FET are used. As a fifth signal terminal, and a fourth FE
The gate of T and the gate of the eighth FET are used as the sixth signal terminal, the source of the first FET, the source of the second FET, the source of the third FET, the source of the fourth FET, and the ninth F.
The drain of ET is connected to the first constant current source, and the fifth FE is connected.
The source of T, the source of the sixth FET, the source of the seventh FET, the source of the eighth FET and the source of the ninth FET are connected to the second constant current source, and the third signal terminal and the fourth signal terminal are connected. Between the first signal terminal and the second signal terminal, the first frequency signal between the first and second signal terminals, and the second frequency signal between the fifth and sixth signal terminals. A third signal frequency, which is a mixed frequency of the first frequency and the second frequency, is output to, and the conversion gain is changed by the gate voltage of the ninth FET, so that nine FETs and two constant current sources are provided. And a drain of the first FET, a drain of the second FET, and a drain of the second FET.
The drain of the FET and the drain of the eighth FET are used as the first signal terminal, and the drain of the third FET and the fourth FET
Drain, the drain of the fifth FET, and the drain of the sixth FET as the second signal terminal, the gate of the second FET and the gate of the third FET as the third signal terminal, and the drain of the sixth FET The gate and the gate of the seventh FET are used as the fourth signal terminal, the gate of the first FET and the gate of the fifth FET are used as the fifth signal terminal, and the gate of the fourth FET and the gate of the eighth FET are used. Is the sixth signal terminal, and the source of the first FET, the source of the second FET, the source of the third FET, the source of the fourth FET and the drain of the ninth FET are the first constant current source. Connect, the source of the 5th FET, the source of the 6th FET, the source of the 7th FET, and the 8th FET
And the source of the ninth FET are connected to the second constant current source, the signal of the first frequency is input between the third signal terminal and the fourth signal terminal, and the fifth signal terminal and the The signal of the second frequency is input between the signal terminals of 6 and the first signal terminal and the second signal terminal.
A third signal frequency, which is a mixed frequency of the first frequency and the second frequency, is output between the signal terminals of
It has a configuration in which the conversion gain is changed by the gate voltage of T.

[0009]

According to the present invention, the number of vertically stacked FETs can be reduced by one as compared with the double-balanced differential amplifier by the above-mentioned configuration, so that low voltage operation is possible and the FET is used as the impedance variable element. Therefore, it is possible to form an impedance variable element having a large amount of impedance change, which is difficult with a bipolar transistor, in the same process.

[0010]

EXAMPLE A semiconductor device according to an example of the present invention will be described below.
A description will be given with reference to the drawings.

FIG. 1 is a circuit diagram of a semiconductor device according to an embodiment of the present invention. In FIG. 1, 1 to 11 are threshold values −
0.4V GaAs MESFET, 12 is a resistor of 5 kΩ, and is inserted so that a large current does not flow to the gate of the FET of 11 by the gain control voltage applied to 107. Further, the IF signal is output from the terminals 101 and 102, and the terminal 1
Input local signals to 03 and 104, and connect to terminals 105 and 1
06 input the RF signal. 107 is a gain control terminal. The FETs 1 to 8 are FETs that form a mixer and have a gate width of 200 μm, and 9 is a FET that acts as an impedance variable element, and the gate width is 800 μm.
FETs 10 and 11 function as a constant current source and have a gate width of 800 μm.

The operation of the semiconductor device configured as described above will be described below with reference to FIGS. 1 and 2.

In FIG. 1, the frequency mixing is from 1 to
8 FET switching is performed. Now terminal 1
03 is applied to the terminal 104, a terminal 104 is applied to the high-frequency signal of −vl, the terminal 105 is applied to vr, and the terminal 106 is applied to the high-frequency signal of −vr. Here, for simplicity, FET
The case where there is no bypass by 9 will be described first. In this case, the FET2 and FET3 are turned on and the FET6 and FET7 are turned off by the relatively large local signal vl. Therefore, for example, in the pair of FET1 and FET2, FE
Most of the current flows through T2, and FET1 is turned off.
Similarly, FET4 is OFF, FET5 is ON, and FET8 is ON. Therefore, the RF signal is FET5 and FET
It is output to the terminals 101 and 102 via the terminal 8. Next, when a high frequency signal of -vl is applied to the terminal 103 and a high frequency signal of vl is applied to the terminal 104, FET2 and FET3 are OFF, FET6 and FET7 are ON, FET1 is ON, FET4 is OFF,
FET5 is OFF and FET8 is OFF. Therefore, the RF signal is 101,1 via FET1 and FET4.
It is output to the 02 terminal. In this way, the RF signal is switched by the local signal, so that the RF signal and the local signal are multiplied.

Next, the gain control effect of the FET 9 will be described. If there is no bypass by FET9, FET1
And FET2, FET3 and FET4, FET5 and FET
6, FE which is a constant current source for each pair of FET7 and FET8
Half the current of T10 and FET11 flows as a bias current. For this reason, for example, when a large signal is applied to the gate of the FET2, the O of the pair of FET1
N, OFF occurs. However, if there is a bypass by the FET 9, it becomes difficult to turn on and off each pair. For example, when vl is applied to the terminal 103, a high-frequency signal of -vl is applied to the terminal 104, vr is applied to the terminal 105, and a high-frequency signal of -vr is applied to the terminal 106, a large current flows through the FET1 to FET4 side, and the FET5 to FET5. A small current flows on the FET8 side. The current of this difference flows through the FET 9 to the constant current source of the FET 11. Therefore, for example, FET1 and FET2
In the pair, FE must be turned on with a larger signal than FET2 as compared with the case where there is no bypass by FET9.
T1 does not turn off. Similarly, in the pair of FET5 and FET6, the FET5 cannot be turned on unless the FET6 is turned off by a larger signal. Thus, the bypass of the FET 9 equivalently lowers the input level of the local signal and reduces the conversion gain. Therefore, the conversion gain can be changed by changing the bypass impedance, and the conversion gain is large when the bypass impedance is large and small when the bypass impedance is small. If this amount of impedance change is large, the amount of gain control is large, but since the FET is used as a variable impedance element in the present invention, a large amount of impedance change can be obtained without using a variable impedance element.

It should be noted that when the RF signal input terminal and the local signal input terminal are interchanged, multiplication is performed and the conversion gain changes due to the bypass impedance. In this case, it is considered that the input level of the RF signal equivalently changes. Good.

Next, FIG. 2 shows conversion gain control characteristics when the semiconductor device is used as a down converter. Terminal 10
Connect a coil balun to 1 and 102 and set DC bias to 3V
Then, the IF signal intensity of 400 MHz was measured in a 50Ω system. Also, connect a coil balun to terminals 103 and 104
C bias is 1.5V, strength is 0dBm in 50Ω system,
A local signal having a frequency of 1750 MHz was input. Further, a coil balun was connected to the terminals 105 and 106, the DC bias was set to 1.5 V, and an RF signal having a strength of -20 dBm and a frequency of 1350 MHz was input in a 50Ω system. The voltage applied to the gain control terminal 107 at this time is shown on the horizontal axis, and the conversion gain is shown on the vertical axis. It can be seen from FIG. 2 that the conversion gain changes by about 10 dB.

As described above, according to this embodiment, Vds of the FET that constitutes the constant current source and the Vds of the FET that constitutes the mixer.
Is 1.5 V and operates in the saturation region, the number of vertically stacked stages is one less than that of the double balanced differential amplifier, and it is possible to operate at a low voltage.

Further, since the impedance between the drain and source of the FET changes from about 10Ω to about 500Ω at about 1.5V, the conversion gain can be controlled by the potential between the power supply voltage and the ground.

The DC bias, the gate width of the FET, and the signal frequency vary depending on each circuit configuration, and are not limited to this embodiment. There are various constant current sources, and the present invention is not limited to this embodiment. Again 12
The resistor was inserted so that a large current flows from the gain control power source to the FET 9 so as not to cause inconveniences such as fluctuations in bias and destruction of the FET 9, but it is not necessary unless such a voltage is applied.

[0020]

As described above, according to the present invention, the number of vertically stacked FETs can be reduced by one as compared with the double balanced differential amplifier, so that low voltage operation is possible, and FETs are used as variable impedance elements. Therefore, it is possible to form an impedance variable element having a large amount of impedance change, which is difficult with a bipolar transistor, in the same process.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a conversion gain control characteristic diagram for explaining the operation in the embodiment.

FIG. 3 is a circuit diagram of a conventional semiconductor device.

[Explanation of symbols]

 1-11 FET 12 resistance 101-102 IF signal output terminal 103-104 local signal input terminal 105-106 RF signal input terminal 107 gain control terminal

Claims (1)

[Claims] 1. A FET comprising nine FETs and two constant current sources, the drain of the first FET, the drain of the second FET, the drain of the seventh FET, and the drain of the eighth FET. The signal terminal of 1, the drain of the third FET, the drain of the fourth FET, the drain of the fifth FET and the sixth F
The drain of ET serves as the second signal terminal, the gate of the second FET and the gate of the third FET serve as the third signal terminal,
The gate of the sixth FET and the gate of the seventh FET are used as the fourth signal terminal, the gate of the first FET and the gate of the fifth FET are used as the fifth signal terminal, and the gate of the fourth FET and the gate of the fourth FET are used. The gate of the 8th FET is used as the 6th signal terminal, and the 1st F
The source of ET, the source of the second FET, the source of the third FET, the source of the fourth FET, and the drain of the ninth FET are connected to the first constant current source, and the source of the fifth FET and the source of the fifth FET are connected. The source of the 6th FET, the source of the 7th FET, the source of the 8th FET, and the source of the 9th FET are connected to the 2nd constant current source, and between the 3rd signal terminal and the 4th signal terminal. First
A signal of the frequency is input, a signal of the second frequency is input between the fifth signal terminal and the sixth signal terminal, and the first frequency is input between the first signal terminal and the second signal terminal. Outputting a third signal frequency, which is a mixed frequency with the second frequency,
9 FETs and 2 constant current sources are provided to change the conversion gain according to the gate voltage of the FETs of the first FET, the drain of the first FET, the drain of the second FET, the drain of the seventh FET, and the eighth FET. Drain of the third FET, the drain of the fourth FET, the drain of the fifth FET, the drain of the sixth FET as the second signal terminal, and the drain of the second signal terminal of the second FET FET gate and third F
The gate of ET serves as the third signal terminal, the gate of the sixth FET and the gate of the seventh FET serve as the fourth signal terminal, and the gate of the first FET and the gate of the fifth FET serve as the fifth signal. As a terminal, the gate of the fourth FET and the gate of the eighth FET as a sixth signal terminal, the source of the first FET, the source of the second FET, the source of the third FET, and the fourth F
The source of ET and the drain of the ninth FET are connected to the first constant current source, the source of the fifth FET, the source of the sixth FET, the source of the seventh FET, the source of the eighth FET, and the source of the eighth FET. The source of FET 9 is connected to the second constant current source, and the third
The signal of the first frequency is input between the signal terminal and the fourth signal terminal, and the signal of the second frequency is input between the fifth signal terminal and the sixth signal terminal. A third signal frequency, which is a mixed frequency of the first frequency and the second frequency, is output between the second signal terminals, and the conversion gain is changed by the gate voltage of the ninth FET. Semiconductor device.