JP2010147988A - Amplifier circuit and radio receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce noise, that a transimpedance amplifier itself generates, while suppressing increase of power consumption. <P>SOLUTION: An operational amplifier AP is connected to a post-stage of a mixer MX, an inverted output terminal of the operational amplifier AP is connected to an inverted input terminal of the operational amplifier AP via a feedback resistor FR11, a non-inverted output terminal of the operational amplifier AP is connected to a non-inverted input terminal of the operational amplifier AP via a feedback resistor FR12, and a negative resistor NR1 is connected between the inverted input terminal and the non-inverted input terminal of the operational amplifier AP. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an amplifier circuit and a wireless receiver, and is particularly suitable for application to a method of reducing noise generated by an operational amplifier while suppressing an increase in current consumption of the operational amplifier.

  In a radio receiver or the like, IV conversion is performed using a transimpedance amplifier in order to amplify a minute current signal. Here, in order to reduce the noise generated by the transimpedance amplifier itself, there is a method of increasing the current flowing through the transimpedance amplifier.

  Further, for example, Patent Document 1 discloses an equalizer filter, a variable conductance amplifier, a load resistor, a variable negative resistor, a capacitor, an amplitude detection means for the filter output, and a resistance value of the variable negative resistor as a current. And a method for controlling the resistance value of the variable negative resistance so that the output amplitude detected by the amplitude detecting means matches the amplitude information preset in the register. .

  However, in order to reduce the noise generated by the transimpedance amplifier itself, increasing the current flowing through the transimpedance amplifier increases the power consumption of the transimpedance amplifier and increases the occupied area of the transimpedance amplifier. There was a problem.

  In the method disclosed in Patent Document 1, the negative resistance circuit can cancel the resistance component of the load resistance connected to the output side of the variable conductance amplifier, but reduces the noise generated by the variable conductance amplifier itself. There was a problem that you can't.

JP-A-6-342561

  Accordingly, an object of the present invention is to provide an amplifier circuit and a wireless receiver that can reduce noise generated by a transimpedance amplifier itself while suppressing an increase in power consumption.

  In order to solve the above-described problem, according to one aspect of the present invention, an operational amplifier, a feedback resistor connected between an input terminal and an output terminal of the operational amplifier, an inverting input terminal and a non-inverting input of the operational amplifier An amplifier circuit comprising: a negative resistance connected to a terminal.

  According to another aspect of the present invention, an operational amplifier includes a feedback resistor connected between an inverting input terminal and an output terminal of the operational amplifier, and a negative resistance connected to the inverting input terminal of the operational amplifier. An amplifier circuit characterized by the above is provided.

  Further, according to one aspect of the present invention, a receiving antenna that receives a radio frequency signal propagating in space, a low noise amplifier that amplifies the radio frequency signal received by the receiving antenna, and the low noise amplifier that is amplified. 5. The down converter that converts a radio frequency signal into a baseband signal or an intermediate frequency signal, and the baseband signal or the intermediate frequency signal converted by the down converter is amplified. 6. Provided is a wireless receiver comprising an amplifier circuit.

  As described above, according to the present invention, it is possible to reduce noise generated by the transimpedance amplifier itself while suppressing an increase in power consumption.

  Hereinafter, an amplifier circuit and a wireless receiver according to embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing a schematic configuration of a radio reception circuit to which an amplifier circuit according to a first embodiment of the present invention is applied.
In FIG. 1, a mixer MX is connected to the subsequent stage of the low noise amplifier LA, and an operational amplifier AP is connected to the subsequent stage of the mixer MX. The low noise amplifier LA can amplify the radio frequency signal received by the receiving antenna. The mixer MX can down-convert the radio frequency signal amplified by the low noise amplifier LA into a baseband signal or an intermediate frequency signal.

  The operational amplifier AP is provided with an inverting input terminal and a non-inverting input terminal, and is provided with an inverting output terminal and a non-inverting output terminal. The inverting output terminal of the operational amplifier AP is connected to the inverting input terminal of the operational amplifier AP via the feedback resistor FR11. Further, a capacitor C11 is connected in parallel to the feedback resistor FR11. The non-inverting output terminal of the operational amplifier AP is connected to the non-inverting input terminal of the operational amplifier AP via the feedback resistor FR12. Further, a capacitor C12 is connected in parallel to the feedback resistor FR12. Further, a negative resistance NR11 is connected between the inverting input terminal and the non-inverting input terminal of the operational amplifier AP.

  The power consumption of the operational amplifier AP is preferably set so that the noise generated in the negative resistor NR11 itself is smaller than the noise generated in the operational amplifier AP itself.

  When the input signal Vin is input to the operational amplifier AP, it is amplified by the operational amplifier AP and then output as the output signal Vout. Here, the voltage output from the operational amplifier AP is fed back to the inverting input terminal and the non-inverting input terminal via the feedback resistors FR11 and FR12, respectively, so that the operational amplifier AP can be operated as a transimpedance amplifier. Conversion can be performed. Further, the capacitors C11 and C12 are connected in parallel to the feedback resistors FR11 and FR12, respectively, so that it can be operated as a low-pass filter. Note that when the operational amplifier AP itself generates noise, the noise is superimposed on the output signal Vout and output.

  Here, the noise generated by the operational amplifier AP itself is affected by the resistance component determined by the input resistance and the feedback resistances FR11 and FR12 viewed from the input side of the operational amplifier AP. Therefore, a negative resistance NR11 is connected between the inverting input terminal and the non-inverting input terminal of the operational amplifier AP, and the resistance component determined by the input resistance and the feedback resistances FR11 and FR12 viewed from the input side of the operational amplifier AP is negative. By canceling with the resistor NR11, noise generated by the operational amplifier AP itself can be reduced. For example, the NF can be improved from 2.1 dB to 1.7 dB by connecting the negative resistance NR11 between the inverting input terminal and the non-inverting input terminal of the operational amplifier AP.

  Note that the noise generated by the operational amplifier AP itself can also be reduced by increasing the bias current flowing through the operational amplifier AP. In this case, in order to increase the bias current flowing through the operational amplifier AP, for example, to improve NF from 2.1 dB to 1.7 dB, the power consumption of the operational amplifier AP increases by about 50 to 100%.

  On the other hand, in the method of connecting the negative resistance NR1 between the inverting input terminal and the non-inverting input terminal of the operational amplifier AP, only the power consumption of about 10% of the operational amplifier AP is consumed in the negative resistance NR11. It is possible to suppress an increase in power consumption of the transimpedance amplifier, and to suppress an increase in the occupied area of the transimpedance amplifier.

FIG. 2 is a diagram illustrating an example of a circuit configuration of the mixer MX in FIG.
In FIG. 2, the mixer MX is provided with field effect transistors M21 to M24. Here, the sources of the field effect transistors M21 and M22 are connected to each other, and the sources of the field effect transistors M23 and M24 are connected to each other. The drains of the field effect transistors M21 and M23 are connected to each other, and the drains of the field effect transistors M22 and M24 are connected to each other. The gates of the field effect transistors M21 and M24 are connected to each other, and the gates of the field effect transistors M22 and M23 are connected to each other.

Then, the local oscillation signal LO ⁺ is input in common to the gates of the field effect transistors M21 and M24, and the local oscillation signal LO ⁻ is input in common to the gates of the field effect transistors M22 and M23, and the local oscillation signals LO ⁺ , LO ^- at be to respectively turn on / off the field effect transistor M21 to M24, a radio frequency signal RFin ^+, RFin ^- the local oscillation signal ^LO +, LO ^- are multiplied, the radio frequency signal RFin ^+, RFin ^- the base It is converted into a band signal BBout ⁺ BBout ⁻ and output.

  Hereinafter, the reason why the noise generated by the operational amplifier AP itself can be reduced by connecting the negative resistance NR1 between the inverting input terminal and the non-inverting input terminal of the operational amplifier AP will be described.

FIG. 3 is a diagram showing a configuration in which the input side of the operational amplifier AP in FIG. 1 is modeled using a signal source and an input resistance.
In FIG. 3, when the mixer MX of FIG. 2 is modeled in the baseband frequency domain, it can be expressed using the signal source Vs and the input resistors IR11 and IR12. Then, by connecting the input resistor IR11 to the inverting input terminal of the operational amplifier AP and connecting the input resistor IR12 to the non-inverting input terminal of the operational amplifier AP, a configuration in which the mixer MX is connected to the front stage of the operational amplifier AP in FIG. can do.

FIG. 4 is a diagram showing a circuit configuration when the non-inverting input terminal of the operational amplifier AP2 in FIG. 3 is grounded.
In FIG. 4, in the configuration in which the input side of the operational amplifier AP2 in FIG. 3 is modeled, the non-inverting input terminal of the operational amplifier AP2 is grounded, and the signal source Vs is connected to the inverting input terminal of the operational amplifier AP via the input resistor R1. It can be expressed by configuration.

FIG. 5 is a diagram showing a general circuit configuration when the operational amplifier AP of FIG. 1 is used as a transimpedance amplifier.
In FIG. 5, the non-inverting input terminal of the operational amplifier AP2 is grounded, the signal source Vs is connected to the inverting input terminal of the operational amplifier AP via the input resistor R1, and a feedback resistor is connected between the output terminal and the inverting input terminal of the operational amplifier AP. A transimpedance amplifier can be configured by connecting R2. The configuration in FIG. 5 matches the configuration in which the capacitor C11 is removed from the configuration in FIG.

FIG. 6 is a diagram in which the signal source Vs is removed from the transimpedance amplifier of FIG. 5 and the noise source Vn of the operational amplifier AP2 is expressed in terms of input.
In FIG. 6, by expressing the noise source Vn of the operational amplifier AP2 in terms of input, the noise source Vn is connected to the inverting input terminal of the operational amplifier AP2.

FIG. 7 is a diagram in which the noise source Vn of FIG. 5 is replaced with the input ground side of the operational amplifier AP2.
In FIG. 7, when the output of the operational amplifier AP2 is fed back to the input and the gain Av of the operational amplifier AP2 is large, the potential difference between the inverting input terminal and the non-inverting input terminal of the operational amplifier AP2 becomes zero. The connection point Vx with the input resistor R1 can be regarded as a virtual ground. Also, there is no positive or negative noise. For this reason, even if the noise source Vn of FIG. 6 is replaced on the non-inverting input terminal side of the operational amplifier AP2, it can be regarded as equivalent.

FIG. 8 is a diagram in which the configuration of FIG. 7 is rewritten.
In FIG. 8, when the configuration of FIG. 7 is rewritten, it can be seen that it is a voltage follower. Here, when the value of the input resistor R1 is R1, and the value of the feedback resistor R2 is R2, the gain Gv of the circuit of FIG. 8 can be given by 1 + R2 / R1. Therefore, when the noise value of the noise source Vn is Vn, the value of the noise Vnout output from the operational amplifier AP2 can be given by Vn (1 + R2 / R1).

FIG. 9 is a diagram showing a configuration in which a negative resistance R3 is added to the input side of the operational amplifier AP2 in FIG.
In FIG. 9, when the negative resistance R3 is added to the inverting input terminal of the operational amplifier AP2 in FIG. 8, the value of the noise Vnout output from the operational amplifier AP2 can be given by Vn (1 + R2 (R1 + R3) / (R1R3)). it can. Here, assuming that the value of the negative resistance R3 is R3, the value of the noise Vnout output from the operational amplifier AP2 is set by setting the value of the negative resistance R3 so as to satisfy the condition of R3 = −R1R2 / (R1 + R2). Can be set to zero.

  Further, the gain Gv of the circuit of FIG. 9 can be given by AvR2 / (R1 (1-Av) + R2 + R1R2 / R3). Here, when the gain Av of the operational amplifier AP2 is sufficiently large, the gain Gv of the circuit of FIG. 9 can be given by −R2 / R1, which is the same as the gain when the negative resistance R3 is not added.

FIG. 10 is a diagram in which the negative resistance R3 of FIG. 9 is added to the transimpedance amplifier of FIG.
Further, the gain Gv of the circuit of FIG. 10 can be given by AvR2 / (R1 (1-Av) + R2 + R1R2 / R3). here,
When the gain Av of the operational amplifier AP2 is sufficiently large, the gain Gv of the circuit of FIG. 10 can be given by −R2 / R1, and is similar to the gain when the negative resistance R3 is not added (FIG. 5).

(Second Embodiment)
FIG. 11 is a circuit diagram showing a schematic configuration of an amplifier circuit according to the second embodiment of the present invention.
In FIG. 11, the inverting output terminal of the operational amplifier AP is connected to the inverting input terminal of the operational amplifier AP through the feedback resistor FR11. An input resistor IR1a and a negative resistor NR11a are connected to the inverting input terminal of the operational amplifier AP.

  The non-inverting output terminal of the operational amplifier AP is connected to the non-inverting input terminal of the operational amplifier AP via the feedback resistor FR12. An input resistor IR1b and a negative resistor NR11b are connected to the non-inverting input terminal of the operational amplifier AP. Note that the input resistors IR1a and IR1b may be the output impedance of the previous stage of the operational amplifier AP.

  Here, by connecting the negative resistance NR11a to the inverting input terminal of the operational amplifier AP and connecting the negative resistance NR11b to the non-inverting input terminal of the operational amplifier AP, the input resistors IR1a and IR1b and the feedback resistors FR11 and FR12 are connected. The determined resistance component can be canceled by the negative resistors NR11a and NR11b, and even when a differential transimpedance amplifier is configured by the operational amplifier AP, noise generated by the operational amplifier AP itself can be reduced.

(Third embodiment)
FIG. 12 is a circuit diagram showing a schematic configuration of the amplifier circuit according to the third embodiment of the present invention.
In FIG. 12, the inverting output terminal of the operational amplifier AP2 is connected to the inverting input terminal of the operational amplifier AP2 via the feedback resistor FR22. An input resistor IR21 and a negative resistor NR21 are connected to the inverting input terminal of the operational amplifier AP2. The non-inverting output terminal of the operational amplifier AP2 is grounded. Note that the input resistor IR21 may be an output impedance before the operational amplifier AP2.

  Here, by connecting the negative resistance NR21 to the inverting input terminal of the operational amplifier AP2, the resistance component determined by the input resistance IR21 and the feedback resistance FR22 can be canceled by the negative resistance NR21. Even when a phase transimpedance amplifier is configured, noise generated by the operational amplifier AP2 itself can be reduced.

(Fourth embodiment)
FIG. 13 is a diagram showing a circuit configuration of a negative resistance used in the amplifier circuit according to the fourth embodiment of the present invention.
In FIG. 13, this negative resistance is provided with a field effect transistor M31, an inverter IV1, and a bias current source IS1. The drain of the field effect transistor M31 is connected to the gate of the field effect transistor M31 via the inverter IV1, and the source of the field effect transistor M31 is connected to the bias current source IS1. An output terminal T1 is provided at the drain of the field effect transistor M31.

The voltage applied to the drain of the field effect transistor M31 is inverted by the inverter IV1, and then applied to the gate of the field effect transistor M31. For this reason, when the potential of the output terminal T1 increases, the potential of the gate of the field effect transistor M31 decreases and the current flowing through the field effect transistor M31 decreases. Therefore, the circuit of FIG. 13 can operate as a negative resistance. it can.
13 can be used as the negative resistors NR11a and NR11b in FIG. 11 or the negative resistor NR21 in FIG.

(Fifth embodiment)
FIG. 14 is a diagram showing a circuit configuration of a negative resistance used in the amplifier circuit according to the fifth embodiment of the present invention.
In FIG. 14, the negative resistance is provided with a bias current source IS2 in addition to the configuration of FIG. The drain of the field effect transistor M31 is connected to the gate of the field effect transistor M31 via the inverter IV1 and also to the bias current source IS2.

Then, a current is supplied from the bias current source IS2 to the drain of the field effect transistor M31, and it is possible to prevent the current from being drawn from the output terminal T1 side. Therefore, even when the output terminal T1 is connected to the input terminal of the operational amplifier AP in FIG. 11 or the input terminal of the operational amplifier AP2 in FIG. 12, it is possible to prevent the operation of the operational amplifiers AP and AP2 from being affected.
14 can be used as the negative resistors NR11a and NR11b in FIG. 11 or the negative resistor NR21 in FIG.

(Sixth embodiment)
FIG. 15 is a diagram showing a circuit configuration of a negative resistance used in the amplifier circuit according to the sixth embodiment of the present invention.
In FIG. 15, the negative resistance is provided with a field effect transistor M32 and an inverter IV2 in addition to the configuration of FIG. The drain of the field effect transistor M32 is connected to the gate of the field effect transistor M32 via the inverter IV2, and the source of the field effect transistor M32 is connected to the bias current source IS2. The drain of the field effect transistor M32 is connected to the drain of the field effect transistor M31.

The voltages applied to the drains of the field effect transistors M31 and M32 are inverted by the inverters IV1 and IV2, respectively, and then applied to the gates of the field effect transistors M31 and M32. For this reason, when the potential of the output terminal T1 rises, the gate potential of the field effect transistors M31 and M32 falls and the current flowing through the field effect transistors M31 and M32 decreases, so that the circuit of FIG. Can work.
The negative resistance in FIG. 15 can be used as the negative resistance NR11a, NR11b in FIG. 11 or the negative resistance NR21 in FIG.

(Seventh embodiment)
FIG. 16 is a diagram showing a circuit configuration of a negative resistance used in the amplifier circuit according to the seventh embodiment of the present invention.
In FIG. 16, this negative resistance is provided with field effect transistors M41 and M42 and a bias current source IS3. The drain of the field effect transistor M41 is connected to the gate of the field effect transistor M42, and the drain of the field effect transistor M42 is connected to the gate of the field effect transistor M41. The sources of the field effect transistors M41 and M42 are connected in common to the bias current source IS3. The drain of the field effect transistor M41 is provided with an output terminal T1, and the drain of the field effect transistor M42 is provided with an output terminal T2.

The voltage applied to the drain of the field effect transistor M41 is applied to the gate of the field effect transistor M42, and the voltage applied to the drain of the field effect transistor M42 is applied to the gate of the field effect transistor M41. . When the potential of the output terminal T1 rises, the current flowing into the output terminal T2 increases and the current flowing from the output terminal T1 to the output terminal T2 decreases. Therefore, the circuit of FIG. 16 can operate as a negative resistance. it can.
The negative resistance in FIG. 16 can be used as the negative resistance NR11 in FIG.

(Eighth embodiment)
FIG. 17 is a diagram showing a circuit configuration of a negative resistance used in the amplifier circuit according to the eighth embodiment of the present invention.
In FIG. 17, this negative resistance is provided with field effect transistors M43 and M44 and a bias current source IS4 in addition to the configuration of FIG. The drain of the field effect transistor M43 is connected to the drain of the field effect transistor M41, and the drain of the field effect transistor M44 is connected to the drain of the field effect transistor M42. The gates of the field effect transistors M43 and M44 are connected to each other and given a bias, and the sources of the field effect transistors M43 and M44 are commonly connected to the bias current source IS4.

Then, a current is supplied from the bias current source IS4 to the drains of the field effect transistors M41 and M42, so that it is possible to prevent the current from being drawn from the output terminals T1 and T2. Therefore, even when the output terminals T1 and T2 are connected between the input terminals of the operational amplifier AP in FIG. 1, it is possible to prevent the operation of the operational amplifier AP from being affected.
Note that the negative resistance in FIG. 17 can be used as the negative resistance NR11 in FIG.

(Ninth embodiment)
FIG. 18 is a diagram showing a circuit configuration of a negative resistance used in the amplifier circuit according to the ninth embodiment of the present invention.
In FIG. 18, this negative resistance is provided with field effect transistors M45 and M46 and a bias current source IS4 in addition to the configuration of FIG. The drain of the field effect transistor M45 is connected to the drain of the field effect transistor M41, and the drain of the field effect transistor M46 is connected to the drain of the field effect transistor M42. The gate of the field effect transistor M45 is connected to the drain of the field effect transistor M46, the gate of the field effect transistor M46 is connected to the drain of the field effect transistor M45, and the sources of the field effect transistors M45 and M46 are bias current sources. Commonly connected to IS4.

The voltage applied to the drains of the field effect transistors M41 and M45 is applied to the gates of the field effect transistors M42 and M46, and the voltage applied to the drains of the field effect transistors M42 and M46 is applied to the field effect transistors M41 and M46. , Applied to the gate of M45. When the potential of the output terminal T1 rises, the current flowing into the output terminal T2 increases and the current flowing from the output terminal T1 to the output terminal T2 decreases, so that the circuit of FIG. 18 can operate as a negative resistance. it can.
The negative resistance in FIG. 18 can be used as the negative resistance NR11 in FIG.
Here, in the configurations of FIGS. 16 to 18, a negative resistance can be realized without using the inverters IV1 and IV12 of FIGS. 13 to 15, and noise generated from the inverters IV1 and IV12 is input to the operational amplifier AP. Therefore, NF can be improved.

(10th Embodiment)
FIG. 19 is a diagram showing a circuit configuration of a negative resistance used in the amplifier circuit according to the tenth embodiment of the present invention.
In FIG. 19, this negative resistance is provided with field effect transistors M51 to M55, a bias current source IS5, detection resistors R11 and R12, and a comparator CP. The drain of the field effect transistor M51 is connected to the gate of the field effect transistor M52, and the drain of the field effect transistor M52 is connected to the gate of the field effect transistor M51. The sources of the field effect transistors M51 and M52 are commonly connected to the bias current source IS5. The drain of the field effect transistor M51 is provided with an output terminal T1, and the drain of the field effect transistor M52 is provided with an output terminal T2.

  The drain of the field effect transistor M53 is connected to the drain of the field effect transistor M51, and the drain of the field effect transistor M54 is connected to the drain of the field effect transistor M52. The gate of the field effect transistor M53 is connected to the drain of the field effect transistor M54, the gate of the field effect transistor M54 is connected to the drain of the field effect transistor M53, and the sources of the field effect transistors M53 and M54 are field effect. Commonly connected to the drain of the transistor M55.

In addition, a series circuit of detection resistors R11 and R12 is connected between the drains of the field effect transistors M51 and M52. The negative terminal of the comparator CP is connected to the reference potential Vref, and the output terminal of the comparator CP is connected to the gate of the field effect transistor M55. Note that the reference potential Vref can be a potential serving as a reference for the output DC bias of the operational amplifier AP.
The negative resistance output terminal T1 is connected to the non-inverting input terminal of the operational amplifier AP, and the negative resistance output terminal T2 is connected to the inverting input terminal of the operational amplifier AP.

  Here, when feedback is applied so that the DC bias of the output signal Vout of the operational amplifier AP is the same potential as the reference potential Vref, the DC bias of the input signal Vin of the operational amplifier AP is also the same potential as the reference potential Vref.

  The voltage between the negative resistance output terminals T1 and T2 is detected by the detection resistors R11 and R12, and is output to the positive terminal of the comparator CP. The comparator CP compares the voltage between the output terminals T1 and T2 with the reference potential Vref, and outputs the difference between them to the gate of the field effect transistor M55. Then, a current corresponding to the difference flows through the field effect transistor M55 to the field effect transistors M53 and M54, and the voltage between the output terminals T1 and T2 is controlled to be equal to the reference potential Vref.

  Thereby, the voltage between the output terminals T1 and T2 of the negative resistance can be made equal to the voltage between the input terminals of the operational amplifier AP. Even when the negative resistance is connected between the input terminals of the operational amplifier AP, the operational amplifier AP. It is possible to prevent a DC current from flowing between the negative resistance and the negative resistance.

(Eleventh embodiment)
FIG. 20 is a diagram showing a circuit configuration of a negative resistance bias current source used in the amplifier circuit according to the eleventh embodiment of the present invention.
In FIG. 20, this bias current source is provided with field effect transistors M61 to M67 and a resistor R13. The source of the field effect transistor M61 is connected to the sources of the field effect transistors M61, M66, and M67 via the resistor R13. The gates of the field effect transistors M61 and M62 are connected to the drain of the field effect transistor M61, and the gates of the field effect transistors M66 and M67 are connected to the drain of the field effect transistor M66.

  The drain of the field effect transistor M63 is connected to the drain of the field effect transistor M61, the drain of the field effect transistor M64 is connected to the drain of the field effect transistor M62, and the drain of the field effect transistor M65 is connected to the field effect transistor M66. Connected to the drain. The gates of the field effect transistors M63 to M65 are connected to the drain of the field effect transistor M62, and the sources of the field effect transistors M63 to M65 are connected in common.

  The gate widths of the field effect transistors M63 and M64 are set to be the same, and the gate width of the field effect transistor M62 is set to be larger than the gate width of the field effect transistor M61.

  A current determined by the gate widths of the field effect transistors M61 and M62 and the value of the resistor R13 flows through the drain of the field effect transistor M62. The current mirror operation of the field effect transistors M64 and M65 causes a current corresponding to the value of the current flowing through the drain of the field effect transistor M62 to flow through the drain of the field effect transistor M66. Further, due to the current mirror operation of the field effect transistors M66 and M67, a current corresponding to the value of the current flowing through the drain of the field effect transistor M66 flows through the drain of the field effect transistor M67, and a bias current is output.

As a result, the conductance of the bias current source can be kept constant, and the negative resistance value can be stabilized even when variations in characteristics of the field effect transistor and temperature variations occur.
20 can be used as the bias current sources IS1 and IS2 in FIGS. 13 to 15, the bias current sources IS3 and IS4 in FIGS. 16 to 18 and the bias current source IS5 in FIG.

(Twelfth embodiment)
FIG. 21 is a block diagram showing a schematic configuration of a radio receiver to which the amplifier circuit according to the twelfth embodiment of the present invention is applied.
In FIG. 21, the radio receiver includes a receiving antenna 101 that receives a radio frequency signal propagating in space, a low noise amplifier 102 that amplifies the radio frequency signal received by the receiving antenna 101, and a difference that performs down-conversion of the received signal. The dynamic down converter 103, filter elements 104 and 105 for removing unnecessary high-frequency components from the in-phase component I and the quadrature component Q output from the down converter 103, and the minute current signal that has passed through the filter elements 104 and 105, respectively. An operational amplifier 106 for amplification is provided.

  Here, the operational amplifier 106 is provided with an inverting input terminal and a non-inverting input terminal, as well as an inverting output terminal and a non-inverting output terminal. The inverting output terminal of the operational amplifier 106 is connected to the inverting input terminal of the operational amplifier 106 via the feedback resistor FR1. A capacitor C1 is connected in parallel to the feedback resistor FR1. The non-inverting output terminal of the operational amplifier 106 is connected to the non-inverting input terminal of the operational amplifier 106 through the feedback resistor FR2. A capacitor C2 is connected in parallel to the feedback resistor FR2. Further, a negative resistance NR1 is connected between the inverting input terminal and the non-inverting input terminal of the operational amplifier 106.

  The radio frequency signal received by the receiving antenna 101 is amplified by the low noise amplifier 102 and then input to the down converter 103. In the down converter 103, the radio frequency signal amplified by the low noise amplifier 102 is multiplied by the local oscillation signals LI and LQ to be down-converted, and the in-phase component I and the quadrature component Q of the baseband signal are generated. .

  The in-phase component I and quadrature component Q of the baseband signal generated by the down converter 103 are amplified by the operational amplifier 106 after unnecessary frequency components are removed by the filter circuits 104 and 105, respectively.

Here, by connecting the negative resistance NR11 between the inverting input terminal and the non-inverting input terminal of the operational amplifier 106, an increase in power consumption of the operational amplifier 106 is suppressed and noise generated by the operational amplifier 106 itself is reduced. NF can be improved.
In the embodiment of FIG. 21, the method of applying the amplifier circuit of FIG. 1 to the direct conversion type radio receiver has been described. However, the radio frequency signal is once converted into an intermediate frequency signal and then converted into a baseband signal. The amplifier circuit of FIG. 1 may be applied to the wireless receiver.
In the above-described embodiment, the method of configuring the negative resistance using the field effect transistor has been described. However, a bipolar transistor may be used instead of the field effect transistor.

1 is a block diagram showing a schematic configuration of a wireless reception circuit to which an amplifier circuit according to a first embodiment of the present invention is applied. The figure which shows an example of the circuit structure of the mixer MX of FIG. The figure which shows the structure which modeled the input side of operational amplifier AP of FIG. 1 using the signal source and input resistance. The figure which shows the circuit structure at the time of grounding the non-inverting input terminal of operational amplifier AP2 of FIG. The figure which shows the general circuit structure at the time of using the operational amplifier AP2 of FIG. 1 as a transimpedance amplifier. FIG. 6 is a diagram in which the signal source Vs is removed from the transimpedance amplifier of FIG. 5 and the noise source Vn of the operational amplifier AP2 is expressed in terms of input. FIG. 6 is a diagram in which the noise source Vn of FIG. 5 is replaced with the input ground side of the operational amplifier AP2. The figure which rewrote the structure of FIG. The figure which shows the structure which added negative resistance R3 to the input side of operational amplifier AP2 of FIG. FIG. 10 is a diagram in which the negative resistance R3 of FIG. 9 is added to the transimpedance amplifier of FIG. The circuit diagram which shows schematic structure of the amplifier circuit which concerns on 2nd Embodiment of this invention. The circuit diagram which shows schematic structure of the amplifier circuit which concerns on 3rd Embodiment of this invention. The figure which shows the circuit structure of the negative resistance used for the amplifier circuit which concerns on 4th Embodiment of this invention. The figure which shows the circuit structure of the negative resistance used for the amplifier circuit which concerns on 5th Embodiment of this invention. The figure which shows the circuit structure of the negative resistance used for the amplifier circuit which concerns on 6th Embodiment of this invention. The figure which shows the circuit structure of the negative resistance used for the amplifier circuit which concerns on 7th Embodiment of this invention. The figure which shows the circuit structure of the negative resistance used for the amplifier circuit which concerns on 8th Embodiment of this invention. The figure which shows the circuit structure of the negative resistance used for the amplifier circuit which concerns on 9th Embodiment of this invention. The figure which shows the circuit structure of the negative resistance used for the amplifier circuit which concerns on 10th Embodiment of this invention. The figure which shows the circuit structure of the bias current source of the negative resistance used for the amplifier circuit which concerns on 11th Embodiment of this invention. The block diagram which shows schematic structure of the radio | wireless receiver with which the amplifier circuit which concerns on 12th Embodiment of this invention is applied.

Explanation of symbols

  LA, 102 Low noise amplifier, MX mixer, AP, AP2 operational amplifier, NR11, NR11a, NR11b, R3, NR21, NR1 Negative resistance, FR11, FR12, R2, FR22, FR1, FR2 Feedback resistance, C11, C12, C21, C22 , C1, C2 capacitors, M21 to M24, M31, M32, M41 to M46, M51 to M55, M61 to M67 Field effect transistors, IR11, IR12, R1, IR21, IR1a, IR1b Input resistance, Vs signal source, Vn noise source , IV1, IV2 inverter, IS1 to IS5 bias current source, CP comparator, R11, R12 detection resistor, R13 resistor, 101 receiving antenna, 103 down converter, 104, 105 filter element, 106 operational amplifier

Claims (5)

An operational amplifier,
A feedback resistor connected between an input terminal and an output terminal of the operational amplifier;
An amplifier circuit comprising: a negative resistance connected between an inverting input terminal and a non-inverting input terminal of the operational amplifier. The negative resistance is
A pair of first field effect transistors with one drain connected to the other gate;
A bias current source for supplying a bias current to a source of the first field effect transistor;
A pair of second field effect transistors connected in cascade to the first field effect transistors, one drain connected to the other gate;
A detection circuit for detecting a voltage between terminals of the negative resistance;
The amplifier circuit according to claim 1, further comprising: a third field effect transistor that controls a bias current supplied to a source of the second field effect transistor based on a detection result by the detection circuit. An operational amplifier,
A feedback resistor connected between the inverting input terminal and the output terminal of the operational amplifier;
An amplifier circuit comprising: a negative resistance connected to an inverting input terminal of the operational amplifier.   4. The power consumption of the operational amplifier is set so that noise generated in the negative resistance itself is smaller than noise generated in the operational amplifier itself. 2. The amplifier circuit according to item 1. A receiving antenna for receiving radio frequency signals propagating in space;
A low noise amplifier for amplifying a radio frequency signal received by the receiving antenna;
A down converter that converts the radio frequency signal amplified by the low noise amplifier into a baseband signal or an intermediate frequency signal;
A radio receiver comprising: the amplifying circuit according to any one of claims 1 to 4 that amplifies a baseband signal or an intermediate frequency signal converted by the down converter.

Images