US20130099304A1 - 3-dimensional nonvolatile memory device and method of manufacturing the same - Google Patents

3-dimensional nonvolatile memory device and method of manufacturing the same Download PDF

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US20130099304A1
US20130099304A1 US13/603,049 US201213603049A US2013099304A1 US 20130099304 A1 US20130099304 A1 US 20130099304A1 US 201213603049 A US201213603049 A US 201213603049A US 2013099304 A1 US2013099304 A1 US 2013099304A1
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layer
etching
forming
material layers
charge trap
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US13/603,049
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Inventor
Min Soo Kim
Dong Sun Sheen
Young Jin Lee
Jin Hae Choi
Joo Hee Han
Sung Jin Whang
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SK Hynix Inc
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Individual
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Assigned to SK Hynix Inc. reassignment SK Hynix Inc. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHOI, JIN HAE, HAN, JOO HEE, KIM, MIN SOO, LEE, YOUNG JIN, SHEEN, DONG SUN, WHANG, SUNG JIN
Publication of US20130099304A1 publication Critical patent/US20130099304A1/en
Priority to US14/540,824 priority Critical patent/US9466609B2/en
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    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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    • H01L29/42312—Gate electrodes for field effect devices
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    • H01L29/42344—Gate electrodes for transistors with charge trapping gate insulator with at least one additional gate, e.g. program gate, erase gate or select gate
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Definitions

  • the present invention relates to a semiconductor device and a method of manufacturing the same. More specifically, the present invention relates to a 3-dimensional nonvolatile memory device and a method of manufacturing the same.
  • a nonvolatile memory device is a kind of memory device, which is capable of intactly retaining stored data without power supply.
  • a two-dimensional memory device manufactured as a single layer on a silicon substrate may be reaching a technical limit for increasing integration density, a three-dimensional nonvolatile memory device, which includes memory cells vertically stacked on a silicon substrate has been proposed recently.
  • FIG. 1 is a cross-sectional view of a conventional 3-dimensional nonvolatile memory device.
  • the conventional 3-dimensional nonvolatile memory device may include channels CH protruding from a substrate 10 and a plurality of memory cells MC stacked along the channels CH. Also, the memory device may further include a lower selection gate LSG formed under the plurality of memory cells MC and an upper selection gate USG formed on the plurality of memory cells MC. Bit lines BL may be provided on the upper selection gate USG. The bit lines BL are connected to the channels CH.
  • a plurality of memory cells MC connected in series between the lower selection gate LSG and the upper selection gate USG may constitute one string STRING, which may locate vertically on the substrate 10 .
  • reference numerals 11 , 14 , and 17 denote interlayer insulating layers.
  • a reference numeral 12 denotes a lower selection line.
  • Reference numeral 15 denotes a word line.
  • a reference numeral 18 denotes an upper selection line.
  • reference numerals 13 and 19 denote gate insulating layers.
  • a reference numeral 16 denotes a charge blocking layer, a charge trap layer, and a tunnel insulating layer.
  • a method of forming the memory cells CH is briefly described.
  • a plurality of conductive layers 15 and a plurality of interlayer insulating layers 14 may be alternately formed and etched in order to form trenches.
  • a charge blocking layer, a charge trap layer, and a tunnel insulating layer 16 may be formed on inner walls of the trenches.
  • a channel layer may be formed in the trenches. Due to the above-described manufacturing process, charge trap layers of the plurality of memory cells MC stacked along the channels CH may be connected to one another.
  • the charge trap layer may serve as a substantial data storage where data is stored by injecting or emitting charges.
  • charges stored in one memory cell MC may be moved or transported to another memory cell MC so that stored data may be changed or damaged.
  • the present invention is directed to a 3-dimensional nonvolatile memory device, which is capable of improving data retention characteristics and a method of manufacturing the same.
  • One aspect of the present invention provides a nonvolatile memory device including plural control gates stacked on a substrate, plural first channels, configured to penetrate the control gates, and plural memory layer patterns, each located between the control gate and the first channel, configured to respectively surround the first channel, wherein the memory layer patterns are isolated from one another.
  • Another aspect of the present invention provides a method of manufacturing a nonvolatile memory device.
  • the method includes alternately forming first material layers and second material layers, etching the first material layers and the second material layers to form first trenches, etching the second material layers exposed in the first trenches, forming a charge trap layer along inner surfaces of the first trenches in which the second material layers are etched, forming a channel layer on the charge trap layer to form first channels having protrusions protruding between the stacked first material layers, etching the first material layers and the second material layers to form slits between adjacent first trenches, etching the charge trap layer exposed to inner walls of the slits to isolate the charge trap layer of stacked memory cells from one another, and forming an insulating layer in the slits in which the charge trap layer is etched.
  • Another aspect of the present invention provides a method of manufacturing a nonvolatile memory device.
  • the method includes alternately forming conductive layers and first sacrificial layers; etching the conductive layers and the first sacrificial layers to form first trenches; forming a charge trap layer along inner surfaces of the first trenches; forming a channel layer on the charge trap layer to form first channels protruding from a substrate; etching the conductive layers and the second sacrificial layers to form slits between adjacent first trenches; etching the first sacrificial layers exposed in the slits to expose the charge trap layer; etching the charge trap layer exposed in the slits to isolate the charge trap layer of stacked memory cells from one another; forming junctions in the first channels exposed by etching the charge trap layer; and forming an insulating layer in the slits.
  • FIG. 1 is a cross-sectional view of a structure of a conventional 3-dimensional nonvolatile memory device
  • FIGS. 2A through 2F are cross-sectional views illustrating a method of manufacturing a 3-dimensional nonvolatile memory device according to a first exemplary embodiment of the present invention
  • FIGS. 3A through 3D are cross-sectional views illustrating a method of manufacturing a 3-dimensional nonvolatile memory device according to a second exemplary embodiment of the present invention.
  • FIGS. 4A through 4D are cross-sectional views illustrating a method of manufacturing a 3-dimensional nonvolatile memory device according to a third exemplary embodiment of the present invention.
  • FIG. 5 is a cross-sectional view of a structure of a 3-dimensional nonvolatile memory device including memory cells according to the first exemplary embodiment
  • FIG. 6 is a cross-sectional view of a structure of a 3-dimensional nonvolatile memory device including memory cells according to the second embodiment
  • FIG. 7 is a cross-sectional view of a structure of a 3-dimensional nonvolatile memory device including memory cells according to the third exemplary embodiment
  • FIG. 8 is a configuration diagram of a memory system according to an exemplary embodiment of the present invention.
  • FIG. 9 is a configuration diagram of a computing system according to an exemplary embodiment of the present invention.
  • FIGS. 2A through 2F are cross-sectional views illustrating a method of manufacturing a 3-dimensional nonvolatile memory device according to a first exemplary embodiment of the present invention. For brevity, only a memory cell region is illustrated in FIGS. 2A through 2F .
  • a plurality of first material layers 21 and a plurality of second material layers 22 may be alternately formed.
  • forming the first material layers 21 may be to form control gates, while the second material layers may be formed to form interlayer insulating layers configured to isolate stacked control gates from one another. Accordingly, the numbers of the stacked first material layers 21 and second material layers 22 may be determined by the number of memory cells to be stacked.
  • the first material layers 21 and the second material layers 22 may be formed of materials having different etch selectivity ratios.
  • the first material layers 21 may be a conductive layer for control gates, while the second material layers 22 may be a sacrificial layer. Otherwise, the first material layers 21 may be a sacrificial layer, while the second material layers 22 may be an interlayer insulating layer.
  • the first material layers 21 are sacrificial layers such as a nitride layer.
  • the second material layers 22 are interlayer insulating layers, such as an oxide layer.
  • the plurality of first material layers 21 and the plurality of second material layers 22 may be etched to form a plurality of first trenches.
  • the plurality of second material layers 22 exposed to inner walls of the first trenches may be etched by a partial thickness.
  • a memory layer 23 may be formed along inner surfaces of the first trenches formed by a process of etching the plurality of second material layers 22 by the partial thickness.
  • the memory layer 23 may include a charge blocking layer, a charge trap layer, and a tunnel insulating layer. However, according to an embodiment, only the charge trap layer and the tunnel insulating layer, except for the charge blocking layer, may be formed.
  • a channel layer may be formed on the memory layer 23 , thereby forming first channels 24 through the stacked first material layers 21 and second material layers 22 .
  • forming the channel layer on the inner walls of the first trenches may be to fill into regions obtained by a process of etching the plurality of second material layers 22 by the partial thickness.
  • the first channels 24 may include a plurality of protrusions ‘A’, each protruding between the stacked first material layers 21 .
  • forming the channel layer to such a thickness may be to completely fill central regions of the first trenches or open the central regions of the first trenches.
  • an insulating layer 25 may be formed on the opened central regions.
  • the plurality of first material layers 21 and the plurality of second material layers 22 may be etched to form slits S between adjacent first channels 24 .
  • a reference numeral 21 A denotes etched first material layers.
  • a reference numeral 22 A denotes etched second material layers.
  • FIG. 2 B illustrates that the plurality of second material layers 22 A partially remain after a step of forming the slits ‘S,’ the plurality of second material layers 22 may be wholly removed.
  • the memory layer 23 may be exposed by removing the remaining second material layers 22 A.
  • the memory layer 23 exposed in the slits S may be etched (refer to reference character “B”). In this case, since the protrusions ‘A’ locates between the first material layers 21 A, the collapse of the first material layers 21 A may not occur. Further, the memory layer 23 may be easily etched.
  • the memory layer 23 may be patterned into a plurality of memory layer patterns 23 A.
  • the charge trap layers of the memory cells stacked along the first channels 24 may be isolated from one another. Accordingly, the transport of charges between the stacked memory cells may not occur.
  • impurities may be implanted into the protrusions ‘A’ of the first channels 24 exposed by etching the memory layer 23 , thereby forming junctions.
  • adjusting a doping depth of the impurities may control the depth of the junctions.
  • the plurality of first material layers 21 A exposed in the slits ‘S’ may be removed to form a plurality of control gate regions.
  • the plurality of protrusions ‘A’ may function as molds for control gates. Regions between the protrusions may become the control gate regions.
  • depositing a conductive layer in the plurality of control gate regions may be to form a plurality of control gates 28 .
  • a first metal layer 26 may be formed along the inner surfaces of the slits ‘S’ including the plurality of control gate regions, Forming second metal layer 27 on the first metal layer 26 may be to fill the control gate regions.
  • the first metal layer 26 may be a barrier metal layer.
  • the second metal layer 27 may be a gap-fill metal layer.
  • the second metal layer 27 formed on the inner walls of the slits ‘S’ except the plurality of control gate regions may be etched by a combination of a wet etching process and a dry etching process.
  • a cleaning process may etch the first metal layer 26 formed on the inner walls of the slits S except the plurality of control gate regions.
  • the conductive layer formed in the plurality of control gate regions may be separated into the plurality of control gates 28 .
  • a charge blocking layer may be formed before forming the control gates 28 .
  • a plurality of protrusions protruding between the stacked control gates 28 may be etched.
  • a reference numeral 24 A denotes first channels having etched protrusions.
  • the effective length of a channel of each of the memory cells may be reduced.
  • the protrusions may be partially etched or may not be etched but remain.
  • junctions may be formed in the first channels 24 A between the stacked control gates 28 .
  • an insulating layer may be formed in the slits S in which the plurality of protrusions are etched.
  • a plurality of memory cells stacked along the first channels 24 A may be formed.
  • angled C shaped memory layer patterns 23 A may respectively surround the control gates 28 . That is, the memory layer patterns 23 A may locate between the first channels 24 A and the plurality of control gates 28 to surround top and bottom surfaces of the plurality of control gates 28 . Accordingly, the plurality of memory cells stacked along the first channels 24 A may include the isolated charge trap layers, respectively.
  • the first material layers 21 may be formed as a conductive layer for control gates, such as a doped polysilicon (doped poly-Si) layer or a doped amorphous silicon layer, while the second material layer 22 may be formed as a sacrificial layer such as an undoped poly-Si layer or an undoped amorphous silicon layer.
  • doped means being doped with a dopant, such as boron (B), and “undoped” means being not doped with a dopant.
  • an insulating layer may be formed in the slits ‘S.’
  • the formation the memory cells stacked along the first channels 24 may be completed.
  • the plurality of first material layers 21 exposed in the slits 5 may be silicided.
  • the silicidation of the first material layers 21 may include forming a metal layer in the slits ‘S,’ siliciding the first material layers 21 using an annealing process, and removing the remaining metal layer.
  • junctions may be formed in the protrusions protruding between the stacked first material layers 21 , the protrusions may be etched, or junctions may be formed in the first channels 24 between the stacked first material layers 21 after etching the protrusions.
  • FIGS. 3A through 3D are cross-sectional views illustrating a method of manufacturing a 3-dimensional nonvolatile memory device according to a second embodiment of the present invention.
  • the second embodiment pertains to a method of forming control gates by forming additional molds after etching protrusions of first channels.
  • a description of the same processes as in the first embodiment will be omitted.
  • first channels 33 including a plurality of protrusions may be formed through a plurality of first material layers 31 .
  • a memory layer 32 may locate between the first channels 33 and a plurality of control gates 31 to surround the first channels 33 .
  • Slits ‘S’ may be formed between adjacent first channels 34 .
  • depositing the first material layers 31 may be to form a sacrificial layer, such as a nitride layer, while the second material layers 32 may be formed as an interlayer insulating layer, such as an oxide layer.
  • the plurality of protrusions of the first channels 33 which may protrude between the stacked first material layers 31 , may be etched.
  • the memory layer 32 configured to surround the plurality of protrusions may be etched together.
  • mold regions M regions where the plurality of protrusions and the memory layer 32 are etched (hereinafter, mold regions M) may be required for forming molds used to form subsequent control gates 31 .
  • the memory layer 32 may be patterned into a plurality of memory layer patterns 32 A, which may be respectively interposed in an I-shape between the first channels 33 A and the first material layers 31 . Accordingly, each memory layer pattern 32 A may be separated with a predetermined distance to prevent charges from moving between the memory cells.
  • the protrusions of the first channels 33 A may be removed so that channels of the memory cells do not surround control gates but be formed in straight shapes. Thus, the channel effective length of the memory cells may decrease.
  • junctions may be formed by implanting impurities into the first channels 33 A exposed between the stacked first material layers 31 .
  • the mold regions ‘M’ may be filled with an insulating layer, such as an oxide layer.
  • insulating layers formed in the mold regions ‘M’ may be molds 35 for forming control gates.
  • the plurality of first material layers 31 may be removed to form a plurality of control gate regions.
  • the plurality of control gate regions may be isolated from one another by the molds 35 .
  • a conductive layer may be formed in the plurality of control gate regions to form a plurality of control gates 38 .
  • Each of the control gates 38 may include a first metal layer 36 and a second metal layer 37 .
  • the first metal layer 36 may be a barrier metal layer, while the second metal layer 37 may be a gap-fill metal layer.
  • an insulating layer 39 may be formed in the slits ‘S’ in which the plurality of control gates 38 are formed.
  • the formation of the memory cells stacked along the first channels 33 A may be completed.
  • the first material layers 31 may be a conductive layer for control gates, while the second material layers 32 may be a sacrificial layer.
  • an insulating layer may be formed in the slits 5 , and the formation of memory cells stacked along the first channels 33 A may be completed.
  • the plurality of first material layers 31 exposed to inner walls of the slits S may be silicided.
  • FIGS. 4A through 4D are cross-sectional views illustrating a method of manufacturing a 3-dimensional nonvolatile memory device according to a third exemplary embodiment of the present invention.
  • FIGS. 4A to 4D only a memory cell region is illustrated for brevity.
  • first material layers 41 and a plurality of second material layers 42 may be alternately formed.
  • first material layers 41 may be conductive layers for control gates, while the second material layers 42 may be sacrificial layers.
  • etching the plurality of first material layers 41 and the plurality of second material layers 42 may form a plurality of first trenches.
  • a memory layer 43 may be formed on inner walls of the first trenches.
  • the memory layer 43 may include a charge blocking layer, a charge trap layer, and a tunnel insulating layer.
  • a channel layer may be formed on the memory layer 43 to form first channels 44 passing through the plurality of first material layers 41 and the plurality of second material layers 42 .
  • first channels 44 have a structure to open central regions of the first channels 44
  • deposting an insulating layer 45 may to fill in the open central regions.
  • the plurality of first material layers 41 and the plurality of second material layers 42 may be etched to form slits ‘S’ between adjacent first channels 44 . Thereafter, the plurality of second material layers 42 exposed in the slits ‘S’ may be etched.
  • etching the plurality of second material layers 42 may be to expose a part of the memory layer 43 .
  • etching the exposed memory layer may split the memory layer 43 into a plurality of memory layer patterns 43 A, which may locate only between each first channel 44 and each first material layers 41 .
  • impurities may be implanted into the first channels 44 exposed between the memory layer patterns 43 A, thereby forming junctions 46 .
  • the junctions 46 may be formed by implanting ions in a lateral direction.
  • the formation of the junctions 46 may include forming doped third material layers (not shown) and diffusing impurities of the third material layers into the exposed first channels 44 using an annealing process. In this case, after forming the junctions 46 , the third material layers may be removed.
  • the first channels 44 A may include a plurality of junctions 46 formed between the stacked first material layers 41 .
  • the junctions 46 may be respectively disposed between the stacked memory cells. Accordingly, the junctions 46 may be provided in the first channels 44 A between the stacked memory cells so that the memory device may be driven in an enhanced mode.
  • an insulating layer 47 may be formed in the slits ‘S’ in which the junctions 46 are formed, thereby completing the formation of the memory cells stacked along the first channels 44 A.
  • FIG. 5 is a cross-sectional view of a structure of a 3-dimensional nonvolatile memory device including memory cells according to the first embodiment.
  • the memory device may include an interlayer insulating layer 52 formed on a substrate 51 , a pipe gate 53 formed on the interlayer insulating layer 52 , a second channel 55 formed in the pipe gate 53 and connected to a pair of first channels 24 A.
  • one pair of first channels 24 A and one second channel 55 may be connected in a U-shape and constitute one string channel CH.
  • the memory device may further include a gate insulating layer 54 configured to surround the second channel 55 .
  • the gate insulating layer 54 may be formed during formation of a memory layer 23 , while the second channel 55 may be formed during the formation of the first channels 24 A.
  • the pipe gate 53 may be etched to form a second trench in a position connected to a pair of first trenches, and a sacrificial layer may be formed in the second trench.
  • the sacrificial layer may be removed to form a U-shaped trench including a pair of first trenches and a second trench.
  • the memory layer 23 and a channel layer may be formed. In this case, the memory layer 23 and the channel layer may be formed in the U-shaped trench.
  • the memory layer 23 surrounding the second channel 55 may be separated from the memory layer 23 surrounding the first channels 24 A during the etching of the memory layer 23 to form the plurality of memory layer patterns 23 A.
  • the memory layer patterns 23 A surrounding the first channels 24 A may respectively surround a plurality of control gates 28 in an angled C-shape.
  • the memory layer patterns 23 A might be separated from one another.
  • the memory layer patterns 23 A surrounding the second channel 55 may surround sidewalls and bottom surface of the second channel 55 in a U-shape, and serve as the gate insulating layer 54 .
  • charge trap layers of the stacked memory cells may be isolated from one another.
  • the memory layer pattern 23 A of the lowermost memory cell may be separated from the gate insulating layer 54 of the pipe gate 53 .
  • connections between the first channels 24 A and the second channel 55 exposed in a slit ‘S’ may be etched during the etching of protrusions of the first channels 24 . Accordingly, an etching process may be controlled to prevent the first channels 24 A from being separated from the second channel 55 due to the complete etching of the connections between the first channels 24 A and the second channel 55 .
  • a protection layer may be formed on bottom surfaces of slits ‘S’ prior to a protrusion etching process.
  • the protection layer may have substantially the same height with the control gate of the lowermost memory cell, in order to cover the connections between the first channels 24 A and the second channel 55 through the bottom surfaces of the slits ‘S.’
  • an etching depth for the slits ‘S’ may be controlled in a range of completely exposing the first material layers 21 but not etching the lowermost second material layer 22 .
  • the connections between the first channels 24 A and the second channel 55 may be not exposed during the protrusion etching process.
  • the width of the pipe trench may be reduced not to expose the connections between the first channels 24 A and the second channel 55 .
  • the pipe gate 53 may be further formed.
  • the gate insulating layer 54 formed on the second channel 55 may be maintained.
  • the gate insulating layer 54 may be maintained using the same method as the above-described method of preventing the etching of the connections between the first channels 24 A and the second channel 55 .
  • FIG. 6 is a cross-sectional view of a structure of a 3-dimensional nonvolatile memory device including memory cells according to the second exemplary embodiment.
  • the memory device may include an interlayer insulating layer 62 formed on a substrate 61 , a pipe gate 63 formed on the interlayer insulating layer 62 , a second channel 65 formed in the pipe gate 63 and connected to a pair of first channels 24 A, and a gate insulating layer 64 configured to surround the second channel 65 .
  • One pair of first channels 24 A and one second channel 65 may be connected in a U-shape and constitute one string channel CH. Also, memory layer patterns 23 A may be respectively interposed in an I-shape between a plurality of control gates and the first channels 24 A.
  • FIG. 7 is a cross-sectional view of a structure of a 3-dimensional nonvolatile memory device including memory cells according to the third exemplary embodiment.
  • the memory device may include an interlayer insulating layer 72 formed on a substrate 71 , a pipe gate 73 formed on the interlayer insulating layer 72 , a second channel 75 formed in the pipe gate 73 and connected to a pair of first channels 74 A, and a gate insulating layer 74 configured to surround the second channel 75 .
  • first channels 24 A and one second channel 75 may be connected in a U-shape and constitute one channel CH.
  • memory layer patterns 43 A may be respectively interposed in an I-shape between a plurality of control gates and the first channels 24 A.
  • junctions 46 may be disposed in first channels 44 A between stacked memory cells.
  • FIG. 8 is a configuration diagram of a memory system 100 according to an exemplary embodiment of the present invention.
  • the memory system 100 may include a nonvolatile memory device 120 and a memory controller 110 .
  • the nonvolatile memory device 120 may be formed to have the above-described cell structure. Also, the nonvolatile memory device 120 may be a multi-chip package (MCP) including a plurality of flash memory chips.
  • MCP multi-chip package
  • the memory controller 110 may be configured to control the nonvolatile memory device 120 and include a static random access memory (SRAM) 111 , a central processing unit 112 , a host interface 113 , an error correction code (ECC) unit 114 , and a memory interface 115 .
  • SRAM 111 may be used as an operation memory of the CPU 112 .
  • the CPU 112 may perform the overall control operation for exchanging data of the memory controller 110 .
  • the host interface 112 may include a data exchange protocol of a host connected to the memory system 100 .
  • the ECC unit 114 may detect and correct errors in data read from the nonvolatile memory device 120 .
  • the memory interface 115 may interface with the nonvolatile memory device 120 .
  • the memory controller 110 may include a read context manager (RCM) configured to store code data required for interfacing with the host.
  • RCM read context manager
  • the memory system 100 having the above-described construction may be a memory card or solid-state disk (SSD) having operational characteristics of both the nonvolatile memory device 120 and the memory controller 110 .
  • the memory controller 110 may communicate with the outside (e.g., the host) through one of various interface protocols, such as a universal serial bus (USB), a man machine communication (MMC), a peripheral component interconnect-express (PCI-E), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), a small computer system interface (SCSI), an enhanced small device interface (ESDI), or an intelligent drive electronics (IDE).
  • USB universal serial bus
  • MMC man machine communication
  • PCI-E peripheral component interconnect-express
  • SATA serial advanced technology attachment
  • PATA parallel advanced technology attachment
  • SCSI small computer system interface
  • ESDI enhanced small device interface
  • IDE intelligent drive electronics
  • FIG. 9 is a configuration diagram of a computing system 200 according to an exemplary embodiment of the present invention.
  • the computing system 200 may include a CPU 220 , a random access memory (RAM) 230 , a user interface 240 , a modem 250 , and a memory system 210 , which may be electrically connected to each other through a system bus 260 .
  • the computing system 200 may further include a battery configured to supply an operating voltage to the computing system 200 .
  • the computing system 200 may further include an application chipset, a camera image processor (CIS), and a mobile dynamic random access memory (mobile DRAM).
  • the memory system 210 may include a nonvolatile memory 212 and a memory controller 211 .
  • charge trap layers of stacked memory cells may be isolated from one another. Accordingly, interferences between selection gates as well as between memory cells may be reduced, thereby improving the efficiency of program, erase, and read operations. Furthermore, junctions may be formed in channels between stacked control gates so that a memory device may be driven in an enhanced mode.

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