US20120199977A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
US20120199977A1
US20120199977A1 US13/362,678 US201213362678A US2012199977A1 US 20120199977 A1 US20120199977 A1 US 20120199977A1 US 201213362678 A US201213362678 A US 201213362678A US 2012199977 A1 US2012199977 A1 US 2012199977A1
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Prior art keywords
metal film
semiconductor device
young
film
modulus
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Abandoned
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US13/362,678
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English (en)
Inventor
Sukehiro Yamamoto
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Seiko Instruments Inc
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Seiko Instruments Inc
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Assigned to SEIKO INSTRUMENTS INC. reassignment SEIKO INSTRUMENTS INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YAMAMOTO, SUKEHIRO
Publication of US20120199977A1 publication Critical patent/US20120199977A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]

Definitions

  • the present invention relates to a semiconductor device having a bonding pad.
  • FIG. 5 is a schematic cross-sectional view illustrating a vicinity of a bonding pad of a conventional semiconductor device having a bonding pad.
  • a first metal film 51 is provided on an insulating film 53 provided on the surface of a semiconductor substrate 50 .
  • a second metal film 52 is provided directly over the first metal film 51 .
  • a protective film 54 covers over the second metal film 52 , and has an opening portion above a bonding pad.
  • the protective film 54 covers the second metal film 52 other than the opening portion of the protective film 54 . Accordingly, the opening portion of the protective film 54 defines a region to be used as the bonding pad.
  • the Young's modulus of the first metal film 51 is higher than that of the second metal film 52 .
  • This structure enhances durability of the vicinity of the bonding pad with respect to stress generated by impact of wire bonding since the first metal film 51 having a higher Young's modulus is provided as the underlayer of the bonding pad (see, for example, Japanese Patent Application Laid-open No. 2009-027098).
  • the second metal film 52 and the first metal film 51 both strain to generate cracks in the insulating film 53 , which has been a problem.
  • the present invention has been made in view of the above-mentioned problem, and it is an object thereof to provide a semiconductor device capable of preventing generation of cracks in an insulating film provided under a bonding pad.
  • the present invention provides a semiconductor device having a bonding pad, including: a first metal film provided on an insulating film provided on a semiconductor substrate; a second metal film provided on the first metal film; a third metal film provided on the second metal film; and a protective film including an opening portion above the third metal film, and covering the first metal film, the second metal film, and the third metal film at portions excluding the opening portion, in which the second metal film has a Young's modulus higher than a Young's modulus of the first metal film and a Young's modulus of the third metal film.
  • the three-layered bonding pad including the first metal film, the second metal film, and the third metal film is used, and the second metal film has a Young's modulus higher than the Young's moduli of the first metal film and the third metal film.
  • This structure can prevent generation of cracks in the insulating film provided under the bonding pad.
  • FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention
  • FIGS. 2A and 2B are schematic cross-sectional views illustrating strain in films caused by wire bonding
  • FIG. 3 is a schematic cross-sectional view illustrating a semiconductor device according to Modified Example 1 of the embodiment of the present invention
  • FIG. 4 is a schematic cross-sectional view illustrating a semiconductor device according to Modified Example 2 of the embodiment of the present invention.
  • FIG. 5 is a schematic cross-sectional view illustrating a conventional semiconductor device.
  • FIG. 1 is a schematic cross-sectional view illustrating a semiconductor device according to the embodiment of the present invention.
  • a first metal film 11 is provided on an insulating film 14 provided on the surface of a semiconductor substrate 10 .
  • a second metal film 12 is provided on the first metal film 11 .
  • a third metal film 13 is provided on the second metal film 12 .
  • a protective film 15 including an opening portion is provided on the third metal film 13 and the insulating film 14 .
  • the opening portion of the protective film 15 defines a region of the bonding pad.
  • the protective film 15 covers the first metal film 11 , the second metal film 12 , and the third metal film 13 at portions excluding the opening portion thereof.
  • the size of the opening portion determines a region that can be used as the bonding pad, and is smaller than the sizes of the first metal film 11 , the second metal film 12 , and the third metal film 13 .
  • the first metal film 11 and the third metal film 13 can be formed of aluminum, for example, and the second metal film 12 can be formed of copper or tungsten.
  • the Young's modulus of aluminum is approximately 70 GPa
  • the Young's modulus of copper is approximately 120 GPa
  • the Young's modulus of tungsten is approximately 400 GPa.
  • the Young's modulus of the second metal film 12 is higher than the Young's moduli of the first metal film 11 and the third metal film 13 .
  • FIGS. 2A and 2B are schematic cross-sectional views illustrating the strain in the films caused by wire bonding.
  • the first metal film 11 , the second metal film 12 , and the third metal film 13 are substantially parallel to one another and are flatly overlapped.
  • the third metal film 13 having a low Young's modulus greatly strains due to stress generated by impact of the wire bonding, with the center as an impact point of the wire bonding (note that, FIG. 2B is an image view exaggerating the strain).
  • the second metal film 12 has a higher Young's modulus than that of the third metal film 13 , the stress due to the strain in the third metal film 13 is dispersed mainly in a planar direction rather than in a direction perpendicular to the second metal film 12 .
  • the second metal film 12 thus strains substantially uniformly, though the second metal film 12 strains rather greatly with the center as the impact point of wire bonding.
  • the stress due to the strain in the second metal film 12 is absorbed by the first metal film 11 having a low Young's modulus. Accordingly, the bottom surface of the first metal film 11 , namely a bonding surface between the first metal film 11 and the insulating film 14 , hardly strains, and hence the impact of wire bonding hardly affects the insulating film 14 . As a result, cracks are further prevented from being generated in the insulating film 14 .
  • the undermost layer of the bonding pad is the first metal film in the above description, but the undermost layer may be made of any material having a low Young's modulus in addition to metal.
  • a polyimide resin film may be used.
  • the polyimide resin has a low Young's modulus of approximately 3.5 GPa.
  • the polyimide resin has generally a good affinity for a semiconductor device, and is thus widely used.
  • FIG. 3 is a schematic cross-sectional view illustrating Modified Example 1 of the embodiment of the present invention.
  • the first metal film 11 is provided on the insulating film 14 , but, as illustrated in FIG. 3 , the first metal film 11 may be embedded in the insulating film 14 .
  • the second metal film 12 is provided on the embedded first metal film 11 .
  • the insulating film 14 has a groove, and the first metal film 11 is embedded in the groove.
  • the groove has a bottom surface formed into a substantially planar shape.
  • the first metal film does not form a step and can thus be formed thick. The strain due to the stress of the second metal film 12 is thus more easily absorbed by the first metal film 11 .
  • FIG. 4 is a schematic cross-sectional view illustrating Modified Example 2 of the embodiment of the present invention.
  • the structure of FIG. 4 is substantially the same as the structure of FIG. 3 , but different in that the bottom surface of the groove of the insulating film 14 is formed so as to be a curve surface that is convex downward or part of a substantially spherical surface as illustrated in FIG. 4 , whereas the bottom surface thereof is formed into a substantially planar shape in FIG. 3 .
  • the bottom surface of the first metal film 11 may be formed so as to be a curve surface that is convex downward or part of a substantially spherical surface.
  • This structure prevents stress concentration on corner portions in the bottom surface of the first metal film 11 .
  • the strain due to the stress of the second metal film 12 is thus even more easily absorbed by the first metal film 11 .

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
US13/362,678 2011-02-07 2012-01-31 Semiconductor device Abandoned US20120199977A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011-024241 2011-02-07
JP2011024241A JP5677115B2 (ja) 2011-02-07 2011-02-07 半導体装置

Publications (1)

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US20120199977A1 true US20120199977A1 (en) 2012-08-09

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US13/362,678 Abandoned US20120199977A1 (en) 2011-02-07 2012-01-31 Semiconductor device

Country Status (5)

Country Link
US (1) US20120199977A1 (enrdf_load_stackoverflow)
JP (1) JP5677115B2 (enrdf_load_stackoverflow)
KR (1) KR101903188B1 (enrdf_load_stackoverflow)
CN (1) CN102629568B (enrdf_load_stackoverflow)
TW (1) TW201304011A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9053973B2 (en) 2013-01-07 2015-06-09 Denso Corporation Semiconductor device
US20180233571A1 (en) * 2017-02-15 2018-08-16 Toyota Jidosha Kabushiki Kaisha Semiconductor device and method of manufacturing the same

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016143804A (ja) * 2015-02-03 2016-08-08 トヨタ自動車株式会社 半導体装置
JP2017224753A (ja) * 2016-06-16 2017-12-21 セイコーエプソン株式会社 半導体装置及びその製造方法
JP2018186144A (ja) 2017-04-25 2018-11-22 株式会社村田製作所 半導体装置及びパワーアンプモジュール

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US20090194889A1 (en) * 2008-02-05 2009-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad structure
US7649207B2 (en) * 2006-05-17 2010-01-19 Au Optronics Corp. Thin film transistor
US7656045B2 (en) * 2006-02-23 2010-02-02 Freescale Semiconductor, Inc. Cap layer for an aluminum copper bond pad
US7741714B2 (en) * 2004-11-02 2010-06-22 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad structure with stress-buffering layer capping interconnection metal layer
US20120225505A1 (en) * 2009-03-04 2012-09-06 Philips Lumileds Lighting Company, Llc Method of bonding a semiconductor device using a compliant bonding structure

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JPH09330928A (ja) * 1996-06-13 1997-12-22 Toshiba Corp 配線層の形成方法
JP2005019493A (ja) * 2003-06-24 2005-01-20 Renesas Technology Corp 半導体装置
US6960836B2 (en) * 2003-09-30 2005-11-01 Agere Systems, Inc. Reinforced bond pad
US20050215048A1 (en) 2004-03-23 2005-09-29 Lei Li Structure and method for contact pads having an overcoat-protected bondable metal plug over copper-metallized integrated circuits
JP2009016619A (ja) * 2007-07-05 2009-01-22 Denso Corp 半導体装置及びその製造方法
US8030780B2 (en) * 2008-10-16 2011-10-04 Micron Technology, Inc. Semiconductor substrates with unitary vias and via terminals, and associated systems and methods

Patent Citations (5)

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Publication number Priority date Publication date Assignee Title
US7741714B2 (en) * 2004-11-02 2010-06-22 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad structure with stress-buffering layer capping interconnection metal layer
US7656045B2 (en) * 2006-02-23 2010-02-02 Freescale Semiconductor, Inc. Cap layer for an aluminum copper bond pad
US7649207B2 (en) * 2006-05-17 2010-01-19 Au Optronics Corp. Thin film transistor
US20090194889A1 (en) * 2008-02-05 2009-08-06 Taiwan Semiconductor Manufacturing Company, Ltd. Bond pad structure
US20120225505A1 (en) * 2009-03-04 2012-09-06 Philips Lumileds Lighting Company, Llc Method of bonding a semiconductor device using a compliant bonding structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9053973B2 (en) 2013-01-07 2015-06-09 Denso Corporation Semiconductor device
US20180233571A1 (en) * 2017-02-15 2018-08-16 Toyota Jidosha Kabushiki Kaisha Semiconductor device and method of manufacturing the same
US10115798B2 (en) * 2017-02-15 2018-10-30 Toyota Jidosha Kabushiki Kaisha Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date
CN102629568B (zh) 2016-05-04
JP2012164825A (ja) 2012-08-30
KR20120090827A (ko) 2012-08-17
CN102629568A (zh) 2012-08-08
TW201304011A (zh) 2013-01-16
KR101903188B1 (ko) 2018-10-01
JP5677115B2 (ja) 2015-02-25

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Effective date: 20120213

STCB Information on status: application discontinuation

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