US20120001265A1 - Method of manufacturing semiconductor device which a plurality of types of transistors are mounted - Google Patents
Method of manufacturing semiconductor device which a plurality of types of transistors are mounted Download PDFInfo
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- US20120001265A1 US20120001265A1 US13/232,402 US201113232402A US2012001265A1 US 20120001265 A1 US20120001265 A1 US 20120001265A1 US 201113232402 A US201113232402 A US 201113232402A US 2012001265 A1 US2012001265 A1 US 2012001265A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
Definitions
- This invention relates to a method of manufacturing a semiconductor device on which a plurality of types of transistors are mounted and the semiconductor device
- oxide films may be deposited on surfaces of element regions in order to prevent damage to a semiconductor substrate by well implementation or channel implementation.
- the sacrifice oxide film is removed with chemical solution, i.e., hydrofluoric acid (HF) prior to forming a gate insulator.
- chemical solution i.e., hydrofluoric acid (HF)
- HF hydrofluoric acid
- a chemical solution such as HF also etches the oxide film for demarcation of the element regions (hereinafter referred as to “buried oxide film”), thus the buried oxide film differs in height after removing the sacrifice oxide film compared to before removing the sacrifice oxide film.
- Japanese Laid-open Patent Publication 2001-24055 discloses a planarization technology for the buried oxide film, i.e., a method for leveling the buried oxide film protruded from the surface of the element region to the element region's height.
- an oxide film hereinafter referred as to “thermal oxidized film”
- the buried oxide film and the thermal oxidized film are coated with photoresist.
- the thermal oxidized film is exposed by etching the photoresist and the buried oxide film at an even rate.
- the buried oxide film and the thermal oxidized film are etched by wet etching at the even rate to expose the element regions.
- the buried oxide film is leveled to the element region in height.
- the etching rate of the buried oxide film with the chemical solution such as HF differs according to the type of implemented ion, an amount of the ion's atomic weight or implementation dosage. As such, where plural types of transistors are implemented together, the etching rates of the buried oxide film vary by region of a semiconductor substrate. Thus, where the sacrificed oxide film is removed with the chemical solution such as HF after well/channel implementation, the surface of the buried oxide film may be unleveled.
- a method of manufacturing a semiconductor device includes the steps of: forming a trench on a semiconductor substrate to define a first element region and a second element region; burying a first oxide film in said trench; forming a second oxide film on surfaces of said first and second element regions; performing a first ion doping using a first mask which is exposing a first region containing said first element region and a part of said first oxide; performing a second ion doping using a second mask which is exposing a second region containing said second element region and a part of said first oxide film; and removing said second oxide film formed in said first element region and said second element region by etching, wherein said first oxide film is selectively thinned using said first or second mask after performing said first or second ion doping.
- a method of manufacturing a semiconductor comprising the steps of: forming a trench on a semiconductor substrate to define a plurality of element regions; burying a first oxide film in said trench; forming a second oxide on surfaces of said plurality of element regions; performing ion doping to said plurality of element regions; forming a third oxide film on said first oxide film after performing ion doping to said element regions; and removing said second oxide film by etching after forming said third oxide on said first oxide.
- a semiconductor device comprising: a semiconductor substrate where a plurality of element regions are defined with a trench on a surface of said semiconductor substrate; an oxide film buried in said trench; a gate insulator film formed on a surface of a plurality of said element regions; a gate electrode formed on a surface of said gate insulator film, wherein at least a part of said oxide film includes a first layer and a second layer deposited on said first layer with lower density of an ion compared to the first layer.
- FIGS. 1-24 are illustrations showing the process of manufacturing the semiconductor device in the first embodiment.
- FIGS. 25-32 are illustrations showing the process of manufacturing the semiconductor device in a variation of the first embodiment.
- FIGS. 33-41 are illustrations showing the process of manufacturing the semiconductor device in a variation of the second embodiment.
- the left side of a vertical wavy line is the first region R 1 wherein the first transistor is formed and the right side of the vertical wavy line is the second region R 2 wherein the second transistor is formed.
- the first transistor is defined as n-MOS transistor and the second transistor is defined as p-MOS transistor.
- an oxide film 2 is formed on a silicon substrate 1 by thermal oxidation method.
- a thickness of the oxide film 2 is defined as 10 nm here.
- a silicon nitride film 3 is deposited by CVD (chemical vapor deposition) method.
- a thickness of the silicon nitride film 3 is defined as 60-120 nm here.
- a resist pattern (not illustrated) coats the silicon nitride film 3 by photolithography method. Thereafter, the silicon nitride film 3 and the oxide film 2 are etched using said resist pattern as a mask. After etching the silicon nitride film 3 and the oxide film 2 , the resist pattern is removed.
- the silicon substrate 1 is etched by RIE (reactive ion etching), thereby silicon trench 1 T are formed on the silicon substrate 1 .
- the silicon trench 1 T defines a plurality of element regions 1 A and 1 B on the silicon substrate 1 .
- the element regions 1 A and 1 B are active regions wherein a variety of transistors are formed.
- a depth of the silicon trench 1 T is defined as 200-350 nm here.
- an oxide film 4 can be formed inside of the silicon trench 1 T by the thermal oxidation method as per FIG. 3 .
- a thickness of the oxide film 4 is defined on the order of 5 nm here.
- an oxide film 5 is deposited on the silicon trench 1 T and the silicon nitride film 3 by, i.e., HDP-CVD (high density plasma chemical vapor deposition), thereby the oxide film 5 is filled in the silicon trench 1 T.
- HDP-CVD high density plasma chemical vapor deposition
- the oxide film 5 is polished by CMP (chemical mechanical polishing).
- CMP chemical mechanical polishing
- the silicon nitride film 3 is removed by wet etching. Since the silicon nitride film 3 is removed, the oxide 5 is higher than the element regions 1 A and 1 B. Subsequently, using the chemical such as HF, the oxide 2 is removed by wet etching, and then an oxide film 7 is formed on the surfaces of the element regions 1 A and 1 B of the silicon substrate 1 by high-temperature anneal at temperatures of 800-1000 degree C., i.e. thermal oxidation method.
- the oxide film 7 formed by the thermal oxidation method has a denser constitution than the oxide film 5 formed by the HDP-CVD.
- the first resist pattern P 1 is formed on the silicon substrate 1 by the photolithography method.
- the first resister pattern P 1 exposes the first region R 1 wherein an n-MOS transistor is formed and covers the second region R 2 wherein a p-MOS transistor is formed.
- the well implementation and then the channel implementation are done in sequence.
- the oxide film 5 formed in the first region R 1 are doped with the ion such as B or In as with the element region 1 A, thus the etching rate of the oxide film 5 with the chemical such as HF rises.
- the first resist pattern P 1 is stripped by wet etching.
- SPM sulfuric-peroxide-mixture
- APM a mixed solution of ammonia and hydrogen peroxide
- the second resist pattern P 2 is formed on the silicon substrate 1 by the photolithography method.
- the second resist pattern P 2 covers the first region R 1 wherein the n-MOS transistor is formed and exposes the second region R 2 wherein the p-MOS transistor is formed.
- the second resist pattern P 2 as a mask, the well implementation and then the channel implementation are subsequently done.
- the oxide film 5 formed in the second region R 2 are doped with the ion such as P or As as with the element region 1 B, thereby raised the etching rate of the oxide film 5 with the chemical such as HF.
- the atomic weight of As doped into the oxide film 5 in the second region R 2 is smaller than that of In doped into the oxide film 5 in first region R 1 , thus the etching rate of the oxide film 5 formed in the second region R 2 is lower than that of the oxide film 5 formed in the first region R 1 .
- the dosage of the ion is not taken into account, however, the etching rate of those oxide film 5 fluctuate with the dosage the ions.
- the oxide film 5 formed in the second region R 2 are etched by the wet etching using the chemical solution such as HF.
- the oxide film 7 should be thinned by ⁇ .
- the heights of the oxide film 5 in the first region R 1 and the second region R 2 can be equalized after removing the oxide film 7 .
- the oxide film 7 has a lower etching rate with the chemical such as HF compared to that of the oxide film 7 . Therefore, if the chemical such as HF is used to thin the oxide film 5 , the oxide 7 is not etched.
- the second resist pattern P 2 is stripped by wet etching.
- APM can be used instead of the SPM. Since the oxide film 5 in the second region R 2 is etched, the oxide film 5 in the first region R 1 differs from those in the second region R 2 in height. Thereby the oxide film 5 formed in the first region R 1 is higher than those in the second region R 2 .
- the oxide film 7 is removed by wet etching.
- the oxide film 5 formed in the first region R 1 and the second region R 2 is etched at the different etching rates.
- the oxide films 5 in both the first and second regions are equal in height after removing the oxide films 7 .
- difference in height between the oxide films 5 in both first and second regions can be avoided.
- oxide films 8 are formed on the surfaces of the element regions 1 A and 1 B by the thermal CVD.
- a thickness of the oxide film 8 is defined as 1 nm here.
- a polysilicon film 9 is deposited over the oxide films 5 and the oxide films 8 by the CVD.
- a thickness of the polysilicon film 9 is defined as 100-150 nm here.
- an antireflection film 10 and then a photoresist film 11 are coated on the surface of the polysilicon film 9 in sequence by the spin coating process. Thereafter, the photoresist film 11 is patterned and then resist pattern 11 a is formed on the surface of the antireflection film 10 .
- the antireflection film 10 , the polysilicion film 9 and the oxide films 8 are etched and then gate insulators 12 and gate electrodes 13 are formed on the element regions 1 A and 1 B. After forming the gate insulators 12 and the gate electrodes 13 , the resist patterns 11 a and the antireflection films 10 are removed.
- the third resist pattern P 3 is formed by photolithography.
- the third resist pattern P 3 exposes the first region R 1 wherein the n-MOS transistor is formed and covers the second region R 2 wherein the p-MOS transistor is formed.
- ion doping is performed to form source extension regions la and drain extension regions 1 b in the element region 1 A formed in the first region R 1 , after which the third resist pattern P 3 is removed with the chemical such as SPM.
- the fourth resist pattern P 4 is formed by photolithography.
- the fourth resist pattern P 4 covers the first region R 1 wherein the n-MOS transistor is formed and exposes the second region R 2 wherein the p-MOS transistor is formed.
- ion doping is performed to form the source extension regions 1 a and the drain extension regions 1 b in the element region 1 B formed in the second region R 2 , after which the fourth resist pattern P 4 is removed with the chemical such as SPM.
- the oxidized silicon film is formed over the oxide films 5 , the element region 1 A/ 1 B and the gate electrodes 13 . Thereafter, the oxidized silicon film is etched anisotropically to form sidewall insulators 15 on both sides of the gate electrodes 13 .
- the thickness of the sidewall insulator 15 is defined as 90 nm here.
- the fifth resist pattern P 5 is formed by the photolithography method.
- the fifth resist pattern P 5 exposes the first region R 1 wherein the n-MOS transistor is formed and coats the second region R 2 wherein the p-MOS transistor is formed.
- ion doping is performed to form source regions 1 c and drain regions 1 d in the element region 1 A formed in the first region R 1 , after which the fifth resist pattern P 5 is removed with the chemical such as SPM.
- the sixth resist pattern P 6 is formed by the photolithography method.
- the sixth resist pattern P 6 covers the first region R 1 wherein the n-MOS transistor is formed and exposes the second region R 2 wherein the p-MOS transistor is formed.
- ion doping is performed to form the source regions 1 c and the drain regions 1 d in the element region 1 B formed in the second region R 2 , after which the sixth resist pattern P 6 is removed with the chemical solution such as SPM.
- an interlayer insulator 16 is deposited over the element regions 1 A and 1 B, the sidewall insulators 15 and the oxide films 5 by HDP-CVD.
- contact holes leading to the source regions 1 c or the drain regions 1 d are formed by the magnetron RIE (reactive ion etching) through the interlayer insulator 16 .
- barrier metal such as TiN is filled within the contact holes by CVD.
- tungsten (W) is deposited on the barrier metal by CVD; thereby contacts made from tungsten (W) are buried inside of the contact hole.
- contacts 17 electrically connected with the source regions 1 c and the drain regions 1 d are completed.
- the principle processes of the method of manufacturing the semiconductor device has finished.
- the oxide films 5 formed in the second region R 2 are preliminary thinned in the first embodiment. Therefore, where the oxide films 7 are removed with the chemical such as HF after the well/channel implementation, the difference in height between the oxide films 5 in the first region R 1 and those in the second region R 2 can be eliminated.
- the antireflection film 10 is coated by spin coating.
- the oxide films in the first region R 1 and those in the second region R 2 differ in height
- the surface of the polysilicon film 9 deposited thereon becomes uneven, and hence the antireflection film 10 deposited thereon is uneven. Consequently, the pattern widths of the resist patterns 11 a vary piece by piece, and thus line widths of the gate electrodes 13 vary piece by piece.
- variation of the oxide films 5 in height between the first region R 1 and the second region R 2 is avoidable in the first embodiment, thus the overall surface of the polysilicon film 9 can be leveled roughly.
- the thickness of the antireflection film 10 coated on the polysilicon film 9 becomes even, and therefore the line widths of the gate electrodes 13 can be even.
- the difference in level between the element region 1 A formed in the first region R 1 and the oxide films 5 formed in the first region R 1 and the difference between the element region 1 B formed in the second region R 2 and the oxide films 5 formed in the second region 1 B can be eliminated simultaneously as per FIG. 22 by adjusting the thickness of the stopper film, i.e., the thickness of the silicon nitride film 3 in polishing the oxide films 5 (refer to FIG. 5 ).
- the widths of the element regions 1 A and 1 B are different, even there is no difference in height between the oxide films 5 in the first region R 1 and those in the second region R 2 , the thickness of the antireflection film 10 could become uneven due to the effect of a viscosity or wettability of the antireflection film 10 .
- the line width of the gate electrode 13 could not be even.
- the oxide films 5 formed in the second region R 2 are thinned with the chemical solution such as HF prior to the elimination of the oxide films 7 .
- the etching rates of the oxide film 5 becomes adverse in the first region R 1 and the second region R 2 .
- the etching rate of the oxide film 5 formed in the second region R 2 becomes greater than that of in the first region R 1 .
- the oxide films 5 formed in the first region R 1 should be thinned prior to removing the oxide film 7 .
- the oxide films 5 formed in the first region R 1 are etched using the first resist pattern P 1 used in said well and channel implementations as a mask.
- a plurality of transistors can be formed in each region.
- n-MOS transistor and the p-MOS transistor In the first embodiment, implementing two types of transistors, i.e., combined use of the n-MOS transistor and the p-MOS transistor, has been presented. However, where the type of ion, the accelerating voltage or dosage used in the well/channel implementation differ from the combination mentioned above, a combination of n-MOS transistor and n-MOS transistor, or p-MOS transistor and p-MOS transistor can be used, or further, three or more types of transistors can be used together.
- the oxide films 5 formed in either of the first region R 1 or the second region R 2 are lower than the element region 1 A or 1 B
- the oxide films 5 can be higher than the element region 1 A or 1 B, or the same by adjusting the thickness of the stopper film, i.e., the thickness of the silicon nitride film 3 , in polishing the oxide films 5 (refer to FIG. 5 ).
- the upper portion of the element 1 A and 1 B i.e., the surfaces of the element 1 A, 1 B and the ridges of the silicon trench 1 T are covered with the oxide film 5 so that the deterioration of the transistor performance caused by leak current and so on can be prevented.
- the oxide films 5 formed in the first region R 1 or the second region R 2 are etched by using the chemical solution such as HF after completing the well/channel implementation to either the first region R 1 or the second region R 2 .
- the oxide films 5 can be etched using chemical solution such as HF after completing both well and channel implementations to both first region R 1 and second region R 2 .
- the code R 3 denotes the third region wherein the third transistor is formed and the code 1 C denotes an element region formed in said third region R 3 .
- the prior embodiment illustrates that “when the oxide films 7 are removed with chemical solution such as HF, the oxide films 5 formed in the first region R 1 are etched by ⁇ and the oxide films 5 formed in the second region R 2 are etched ⁇ ( ⁇ ) and the oxide films 5 formed in the third region R 3 are etched ⁇ ( ⁇ ), as per FIG. 25 , firstly the seventh resist pattern P 7 is formed by the lithography method.
- the seventh resist pattern P 7 covers the first region R 1 , and exposes the second region R 2 and the third region R 3 .
- the oxide films 5 formed in the second region R 2 and the third region R 3 are etched by ⁇ .
- the seventh resist pattern P 7 is an inversion pattern of the first resist pattern P 1 used in the well implementation and the channel implementation to the first region R 1 .
- the resist material of the first resist pattern P 1 as negative resist and the resist material of the seventh resist pattern P 7 as a positive resist
- the first resist pattern P 1 and the seventh pattern P 7 can be formed by using a common reticle.
- the oxide films 5 in the first region R 1 , the second region R 2 and the third region R 3 could differ in height significantly after removing the oxide films 7 .
- the eighth resist pattern P 8 can be formed by the lithography method as per FIG. 27 if needed.
- the eighth resist pattern P 8 covers the first and the second region R 1 and R 2 and exposes only the third region R 3 .
- the oxide film formed in the third region R 3 is etched by ⁇ using the chemical solution such as HF.
- the oxide films 5 formed in the first, second and third region (R 1 , R 2 and R 3 ) can be equalized in height as per FIG. 28 .
- the oxide films 5 are etched with the chemical solution such as HF before removing the oxide films 7 , however, for example, after removing the oxide films 7 , the oxide films 5 can be etched using the chemical solution such as HF.
- the thickness of the gate insulator of the n-MOS transistor and that of the gate insulator of the p-MOS transistor is equal.
- the gate insulators can be formed simultaneously in the element region 1 A formed in the first region R 1 and the element region 1 B formed in the second region R 2 .
- the thicknesses of the gate insulators in the first region R 1 and the second region R 2 could differ.
- the gate insulator of the high-voltage-resistant transistor is thicker than that of the low-voltage-resistant transistor, so that where implementing both low-voltage- and high-voltage-resistant transistors, the gate insulators should be formed respectively in the first region R 1 and the second region R 2 .
- silicon oxide films 20 are formed on the element region 1 A existing in the first region R 1 and the element region 1 B existing in the first region R 2 .
- the thickness of the silicon oxide films 20 should be the same thickness of the gate insulator of the high-voltage-resistant transistor formed in the second region R 2 .
- the thickness of the gate insulator of the high-voltage-resistant transistor is defined as 10 nm.
- the second region R 2 is covered with a resist 18 , and then the silicon oxide films 20 formed in the first region R 1 are removed by wet etching using the chemical solution such as HF. Thereafter, using the resist 18 as a mask, silicon oxide films 21 are formed in the element region 1 A existing in the first region R 1 .
- the thickness of the silicon oxide films 21 is the same thickness of the gate insulator film of the low-voltage-resistant transistor formed in the first region R 1 .
- the thickness of the gate insulator of the low-voltage-resistant transistor is defined as 1 nm.
- the number of the etchings with the chemical solution of the first region R 1 differs from that of the second region.
- the oxide films 5 formed in the first region R 1 wherein the low-voltage-resistant transistor is formed will be thinner than the oxide films 5 formed in the second region R 2 wherein the high-voltage-resistant transistor is formed by the number of the chemical etching of the silicon oxide films 20 .
- the oxide films 5 formed in the first region R 1 is thinner than those in the second region R 2 by one chemical etching with HF.
- the oxide films 5 in both first region R 1 and second region R 2 are equal in height at the time when the silicon oxide films 20 are formed as per FIG. 29 , the oxide films 5 have a variation in height as per FIG. 30 after completing the gate insulators for the low- and high-voltage-resistant transistors.
- the oxide films 5 formed in the second region R 2 is etched using the chemical solution such as HF.
- the oxide films 5 formed in the second region R 2 are etched by ⁇ preliminary.
- the difference of the oxide films 5 in the first region R 1 and the second region R 2 in height can be avoidable as per FIG. 32 . Therefore, the oxide films 5 are etched preliminary inasmuch as that the number of times of chemical etching using HF to the first region R 1 is different from that to the second region in this example.
- oxide film 30 is deposited over the oxide films 5 and the oxide films 7 by the HDP-CVD as per FIG. 33 .
- the thickness of the oxide film 30 is defined as 100-200 nm here.
- the oxide film 30 is used, however, TEOS (tetra ethyl ortho silicate) can be used as an alternative.
- the oxide film 30 is polished to the thickness of approximately 50-100 nm, to level its surfaces.
- an antireflection film 31 and then photoresists 32 are coated on the surface of the oxide film 30 by the spin coating. Thereafter, patterning the photoresists 32 by the photolithography method, the ninth resist pattern P 9 is formed on the antireflection film 31 .
- the ninth resist pattern P 9 exposes the regions where the element regions 1 A and 1 B exist, and covers the regions where the oxide films 5 exist.
- the antireflection film 31 and the oxide film 30 are removed by the dry etching.
- the dry etching is used to expose the surfaces of the oxide films 30 .
- the wet etching can be used in conjunction with the dry etching.
- the oxide film 30 deposited on the oxide films 7 can be etched to the thickness of approximately 10-30 nm by the dry etching and then the residual oxide film 30 on the surfaces of oxide films 7 can be removed by the wet etching using the chemical solution such as HF as per FIG. 38 .
- the ninth resist pattern P 9 and the antireflection film 31 can be removed.
- the oxide films 7 are removed by the wet etching using the chemical solution such as HF.
- the oxide film 30 deposited over the oxide films 5 are etched due to the wet etching.
- the oxide film 30 is formed after the well/channel implementation so that the etching rates of the oxide film 30 are equal in the first region R 1 and the second region R 2 .
- the chemical solution such as HF is used to remove the oxide films 7 after the well/channel implementation, the oxide film 30 is level in both first and second region (R 1 and R 2 ).
- the case is where the surfaces of the oxide films 5 are higher than those of the element regions 1 A and 1 B at the point of removing the oxide films 7 .
- the surfaces of the oxide films 5 can be lower than those in the element regions 1 A and 1 B at the point of removing the oxide films 7 . If the surfaces of the oxide films 5 are lower than those of the element regions 1 A and 1 B, the etching rates of the oxide film 30 in the first region R 1 and the second region R 2 are the same even where the oxide film 30 is etched to the same height of the surfaces of the element regions 1 A and 1 B. Therefore, as per FIG. 41 , the difference between the element region 1 A formed in the first region R 1 and the oxide films 5 formed in the first region R 1 can be readily eliminated together with the difference between the element region 1 B formed in the second region R 2 and the oxide films 5 formed in the second region R 2 .
- the oxide film 30 covers the surfaces of the element regions 1 A and 1 B, the deterioration of the transistors performances such as leak current can be avoided.
- the two types of the oxide films are deposited within the trench 1 T, viz., the oxide films 5 and the oxide films 30 having the lower ion concentration compared to the oxide film 5 bury the trench 1 T.
Abstract
A method of manufacturing a semiconductor device includes the steps of forming a trench on a semiconductor substrate to define a first and a second element regions; burying a first oxide film in the trench; forming a second oxide film on surfaces of the first and second element regions; performing a first ion doping using a first mask which is exposing a first region containing the first element region and a part of the first oxide; performing a second ion doping using a second mask which is exposing a second region containing the second element region and a part of the first oxide film; and removing the second oxide film formed in the first element region and the second element region by etching, and the first oxide film is selectively thinned using the first or second mask after performing the first or second ion doping.
Description
- This application is a divisional application of U.S. application Ser. No. 12/053,089, filed Mar. 21, 2008, which is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2007-90775, filed on Mar. 30, 2007, the entire contents of which are incorporated herein by reference.
- This invention relates to a method of manufacturing a semiconductor device on which a plurality of types of transistors are mounted and the semiconductor device
- In a manufacturing process of a semiconductor device including transistors, i.e., MOS transistors, oxide films (hereinafter referred to as “sacrifice oxide film”) may be deposited on surfaces of element regions in order to prevent damage to a semiconductor substrate by well implementation or channel implementation.
- The sacrifice oxide film is removed with chemical solution, i.e., hydrofluoric acid (HF) prior to forming a gate insulator. However, a chemical solution such as HF also etches the oxide film for demarcation of the element regions (hereinafter referred as to “buried oxide film”), thus the buried oxide film differs in height after removing the sacrifice oxide film compared to before removing the sacrifice oxide film.
- Japanese Laid-open Patent Publication 2001-24055 discloses a planarization technology for the buried oxide film, i.e., a method for leveling the buried oxide film protruded from the surface of the element region to the element region's height. With this approach, firstly, an oxide film (hereinafter referred as to “thermal oxidized film”) is formed on the surface of the element region by thermal oxidation method. Then, the buried oxide film and the thermal oxidized film are coated with photoresist. Thereafter, the thermal oxidized film is exposed by etching the photoresist and the buried oxide film at an even rate. Next, the buried oxide film and the thermal oxidized film are etched by wet etching at the even rate to expose the element regions. Thus the buried oxide film is leveled to the element region in height.
- The etching rate of the buried oxide film with the chemical solution such as HF differs according to the type of implemented ion, an amount of the ion's atomic weight or implementation dosage. As such, where plural types of transistors are implemented together, the etching rates of the buried oxide film vary by region of a semiconductor substrate. Thus, where the sacrificed oxide film is removed with the chemical solution such as HF after well/channel implementation, the surface of the buried oxide film may be unleveled.
- According to an aspect of an embodiment, a method of manufacturing a semiconductor device includes the steps of: forming a trench on a semiconductor substrate to define a first element region and a second element region; burying a first oxide film in said trench; forming a second oxide film on surfaces of said first and second element regions; performing a first ion doping using a first mask which is exposing a first region containing said first element region and a part of said first oxide; performing a second ion doping using a second mask which is exposing a second region containing said second element region and a part of said first oxide film; and removing said second oxide film formed in said first element region and said second element region by etching, wherein said first oxide film is selectively thinned using said first or second mask after performing said first or second ion doping.
- According to an another aspect of an embodiment, a method of manufacturing a semiconductor, comprising the steps of: forming a trench on a semiconductor substrate to define a plurality of element regions; burying a first oxide film in said trench; forming a second oxide on surfaces of said plurality of element regions; performing ion doping to said plurality of element regions; forming a third oxide film on said first oxide film after performing ion doping to said element regions; and removing said second oxide film by etching after forming said third oxide on said first oxide.
- According to a further aspect of an embodiment, a semiconductor device, comprising: a semiconductor substrate where a plurality of element regions are defined with a trench on a surface of said semiconductor substrate; an oxide film buried in said trench; a gate insulator film formed on a surface of a plurality of said element regions; a gate electrode formed on a surface of said gate insulator film, wherein at least a part of said oxide film includes a first layer and a second layer deposited on said first layer with lower density of an ion compared to the first layer.
-
FIGS. 1-24 are illustrations showing the process of manufacturing the semiconductor device in the first embodiment. -
FIGS. 25-32 are illustrations showing the process of manufacturing the semiconductor device in a variation of the first embodiment. -
FIGS. 33-41 are illustrations showing the process of manufacturing the semiconductor device in a variation of the second embodiment. - [A method of manufacturing a semiconductor device]
- Referring to
FIGS. 1-24 , the method of manufacturing the semiconductor device in the first embodiment will be discussed precisely here. InFIGS. 1-24 , the left side of a vertical wavy line is the first region R1 wherein the first transistor is formed and the right side of the vertical wavy line is the second region R2 wherein the second transistor is formed. In the first embodiment, the first transistor is defined as n-MOS transistor and the second transistor is defined as p-MOS transistor. - As per
FIG. 1 , firstly, anoxide film 2 is formed on asilicon substrate 1 by thermal oxidation method. A thickness of theoxide film 2 is defined as 10 nm here. Then, asilicon nitride film 3 is deposited by CVD (chemical vapor deposition) method. A thickness of thesilicon nitride film 3 is defined as 60-120 nm here. Next, a resist pattern (not illustrated) coats thesilicon nitride film 3 by photolithography method. Thereafter, thesilicon nitride film 3 and theoxide film 2 are etched using said resist pattern as a mask. After etching thesilicon nitride film 3 and theoxide film 2, the resist pattern is removed. - Then, as per
FIG. 2 , using thesilicon nitride film 3 as a mask, thesilicon substrate 1 is etched by RIE (reactive ion etching), therebysilicon trench 1T are formed on thesilicon substrate 1. Thesilicon trench 1T defines a plurality ofelement regions silicon substrate 1. Theelement regions silicon trench 1T is defined as 200-350 nm here. If necessary, anoxide film 4 can be formed inside of thesilicon trench 1T by the thermal oxidation method as perFIG. 3 . A thickness of theoxide film 4 is defined on the order of 5 nm here. - Next, as per
FIG. 4 , anoxide film 5 is deposited on thesilicon trench 1T and thesilicon nitride film 3 by, i.e., HDP-CVD (high density plasma chemical vapor deposition), thereby theoxide film 5 is filled in thesilicon trench 1T. - Then, as per
FIG. 5 , theoxide film 5 is polished by CMP (chemical mechanical polishing). In the first embodiment, using thesilicon nitride film 3 as a stopper film, theoxide film 5 is polished until saidsilicon nitride film 3 is about 60 nm in thickness. - Then, as per
FIG. 6 , using a chemical solution such as phosphoric acid (H3PO4), thesilicon nitride film 3 is removed by wet etching. Since thesilicon nitride film 3 is removed, theoxide 5 is higher than theelement regions oxide 2 is removed by wet etching, and then anoxide film 7 is formed on the surfaces of theelement regions silicon substrate 1 by high-temperature anneal at temperatures of 800-1000 degree C., i.e. thermal oxidation method. Theoxide film 7 formed by the thermal oxidation method has a denser constitution than theoxide film 5 formed by the HDP-CVD. Therefore, an etching rate of theoxide film 7 with the chemical such as HF is lower than that of theoxide film 5. A thickness of theoxide film 7 is defined as 5-20 nm here. Theoxide film 7 is a substantially a sacrifice oxide film, therefore it is removed in a later process with the chemical such as HF. Next, as perFIG. 7 , the first resist pattern P1 is formed on thesilicon substrate 1 by the photolithography method. The first resister pattern P1 exposes the first region R1 wherein an n-MOS transistor is formed and covers the second region R2 wherein a p-MOS transistor is formed. Using the first resist pattern P1 as a mask, the well implementation and then the channel implementation are done in sequence. - In the first embodiment, 5.0×1013−1.0×1014 cm2 dosage of, i.e., B (boron ion) is doped with the accelerating voltage of 100-300 kev in the well implementation. Subsequently, 1.0×1011−1.0×1014 cm2 of, i.e., B (boron ion) is doped with the accelerating voltage of 5−50 kev, or alternatively, 1.0×1011−1.0×1014 cm2 dosage of In (indium ion) is doped with the accelerating voltage of 20-200 kev in the channel implementation. In the ion implementations, the
oxide film 5 formed in the first region R1 are doped with the ion such as B or In as with theelement region 1A, thus the etching rate of theoxide film 5 with the chemical such as HF rises. - Then, as per
FIG. 8 , using sulfuric-peroxide-mixture (hereinafter referred to as “SPM”), the first resist pattern P1 is stripped by wet etching. Alternatively, a mixed solution of ammonia and hydrogen peroxide (hereinafter referred to as “ammonia-peroxide-mixture” or “APM”) can be used. Thereafter, the second resist pattern P2 is formed on thesilicon substrate 1 by the photolithography method. The second resist pattern P2 covers the first region R1 wherein the n-MOS transistor is formed and exposes the second region R2 wherein the p-MOS transistor is formed. Then, using the second resist pattern P2 as a mask, the well implementation and then the channel implementation are subsequently done. - In the first embodiment, 5.0×1012−1.0×1014 cm2 dosage of P (phosphorus ion) is doped with the voltage of 200-900 kev in the well implementation. Subsequently, 1.0×1011−1.0×1014 cm2 dosage of P (phosphorus ion) or As (arsenic ion) is doped with the accelerating voltage of 20-200 kev in the channel implementation. In the ion implementations, the
oxide film 5 formed in the second region R2 are doped with the ion such as P or As as with theelement region 1B, thereby raised the etching rate of theoxide film 5 with the chemical such as HF. In this regard, the atomic weight of As doped into theoxide film 5 in the second region R2 is smaller than that of In doped into theoxide film 5 in first region R1, thus the etching rate of theoxide film 5 formed in the second region R2 is lower than that of theoxide film 5 formed in the first region R1. Here, the dosage of the ion is not taken into account, however, the etching rate of thoseoxide film 5 fluctuate with the dosage the ions. - In the first embodiment, as per
FIG. 9 , using the second resist pattern P2 as a mask, theoxide film 5 formed in the second region R2 are etched by the wet etching using the chemical solution such as HF. - E.g., from prior experiment, it is proven that “where the
oxide film 7 are removed with the chemical such as HF, theoxide film 5 in the first region R1 are etched by a and theoxide film 5 in the second region R2 are etched by β(<α)”, theoxide film 5 in the second region R2 should be thinned by α−β. Thus, the heights of theoxide film 5 in the first region R1 and the second region R2 can be equalized after removing theoxide film 7. Thereby the variation of theoxide film 5 in height in both the first region R1 and the second region R2 can be avoided. Again, theoxide film 7 has a lower etching rate with the chemical such as HF compared to that of theoxide film 7. Therefore, if the chemical such as HF is used to thin theoxide film 5, theoxide 7 is not etched. - Next, as per
FIG. 10 , using a chemical such as SPM, the second resist pattern P2 is stripped by wet etching. Alternatively, APM can be used instead of the SPM. Since theoxide film 5 in the second region R2 is etched, theoxide film 5 in the first region R1 differs from those in the second region R2 in height. Thereby theoxide film 5 formed in the first region R1 is higher than those in the second region R2. - Then, as per
FIG. 11 , using the chemical such as HF, theoxide film 7 is removed by wet etching. In the wet etching, theoxide film 5 formed in the first region R1 and the second region R2 is etched at the different etching rates. In the first embodiment, since theoxide film 5 in the second region R2 is thinned preliminary in consideration of the difference between said etching rates, theoxide films 5 in both the first and second regions are equal in height after removing theoxide films 7. Thus, difference in height between theoxide films 5 in both first and second regions can be avoided. - Then, as per
FIG. 12 ,oxide films 8 are formed on the surfaces of theelement regions oxide film 8 is defined as 1 nm here. Thereafter, apolysilicon film 9 is deposited over theoxide films 5 and theoxide films 8 by the CVD. A thickness of thepolysilicon film 9 is defined as 100-150 nm here. - Next, as per
FIG. 13 , anantireflection film 10 and then aphotoresist film 11 are coated on the surface of thepolysilicon film 9 in sequence by the spin coating process. Thereafter, thephotoresist film 11 is patterned and then resistpattern 11 a is formed on the surface of theantireflection film 10. - Then, as per
FIG. 14 , using the resistpattern 11 a as a mask, theantireflection film 10, thepolysilicion film 9 and theoxide films 8 are etched and thengate insulators 12 andgate electrodes 13 are formed on theelement regions gate insulators 12 and thegate electrodes 13, the resistpatterns 11 a and theantireflection films 10 are removed. - Next, as per
FIG. 15 , the third resist pattern P3 is formed by photolithography. The third resist pattern P3 exposes the first region R1 wherein the n-MOS transistor is formed and covers the second region R2 wherein the p-MOS transistor is formed. Using thegate electrodes 13 and the third resist pattern P3 as masks, ion doping is performed to form source extension regions la anddrain extension regions 1 b in theelement region 1A formed in the first region R1, after which the third resist pattern P3 is removed with the chemical such as SPM. - Next, as per
FIG. 16 , the fourth resist pattern P4 is formed by photolithography. The fourth resist pattern P4 covers the first region R1 wherein the n-MOS transistor is formed and exposes the second region R2 wherein the p-MOS transistor is formed. Using thegate electrodes 13 and the fourth resist pattern P4 as masks, ion doping is performed to form thesource extension regions 1 a and thedrain extension regions 1 b in theelement region 1B formed in the second region R2, after which the fourth resist pattern P4 is removed with the chemical such as SPM. - Then, as per
FIG. 17 , the oxidized silicon film is formed over theoxide films 5, theelement region 1A/1B and thegate electrodes 13. Thereafter, the oxidized silicon film is etched anisotropically to formsidewall insulators 15 on both sides of thegate electrodes 13. The thickness of thesidewall insulator 15 is defined as 90 nm here. - Next, as per
FIG. 18 , the fifth resist pattern P5 is formed by the photolithography method. The fifth resist pattern P5 exposes the first region R1 wherein the n-MOS transistor is formed and coats the second region R2 wherein the p-MOS transistor is formed. Using thegate electrodes 13, thesidewall insulators 15 and the fifth resist pattern P5 as masks, ion doping is performed to formsource regions 1 c anddrain regions 1 d in theelement region 1A formed in the first region R1, after which the fifth resist pattern P5 is removed with the chemical such as SPM. - Then, as per
FIG. 19 , the sixth resist pattern P6 is formed by the photolithography method. The sixth resist pattern P6 covers the first region R1 wherein the n-MOS transistor is formed and exposes the second region R2 wherein the p-MOS transistor is formed. Using thegate electrodes 13, thesidewall insulators 15 and the sixth resist pattern P6 as masks, ion doping is performed to form thesource regions 1 c and thedrain regions 1 d in theelement region 1B formed in the second region R2, after which the sixth resist pattern P6 is removed with the chemical solution such as SPM. - Then as per
FIG. 20 , aninterlayer insulator 16 is deposited over theelement regions sidewall insulators 15 and theoxide films 5 by HDP-CVD. - Next, as per
FIG. 21 , contact holes leading to thesource regions 1 c or thedrain regions 1 d are formed by the magnetron RIE (reactive ion etching) through theinterlayer insulator 16. Then barrier metal such as TiN is filled within the contact holes by CVD. Thereafter, tungsten (W) is deposited on the barrier metal by CVD; thereby contacts made from tungsten (W) are buried inside of the contact hole. Thuscontacts 17 electrically connected with thesource regions 1 c and thedrain regions 1 d are completed. As described above, the principle processes of the method of manufacturing the semiconductor device has finished. - As described above, inasmuch as the etching rate of the
oxide film 5 rises with the chemical such as HF due to the ion implementation, theoxide films 5 formed in the second region R2 are preliminary thinned in the first embodiment. Therefore, where theoxide films 7 are removed with the chemical such as HF after the well/channel implementation, the difference in height between theoxide films 5 in the first region R1 and those in the second region R2 can be eliminated. - Conventionally, the
antireflection film 10 is coated by spin coating. Thus, where the oxide films in the first region R1 and those in the second region R2 differ in height, the surface of thepolysilicon film 9 deposited thereon becomes uneven, and hence theantireflection film 10 deposited thereon is uneven. Consequently, the pattern widths of the resistpatterns 11 a vary piece by piece, and thus line widths of thegate electrodes 13 vary piece by piece. However, variation of theoxide films 5 in height between the first region R1 and the second region R2 is avoidable in the first embodiment, thus the overall surface of thepolysilicon film 9 can be leveled roughly. Thus the thickness of theantireflection film 10 coated on thepolysilicon film 9 becomes even, and therefore the line widths of thegate electrodes 13 can be even. - Further, since the unevenness in height between the
oxide films 5 in the first region and the second region is avoidable, the difference in level between theelement region 1A formed in the first region R1 and theoxide films 5 formed in the first region R1 and the difference between theelement region 1B formed in the second region R2 and theoxide films 5 formed in thesecond region 1B can be eliminated simultaneously as perFIG. 22 by adjusting the thickness of the stopper film, i.e., the thickness of thesilicon nitride film 3 in polishing the oxide films 5 (refer toFIG. 5 ). - For example, where the widths of the
element regions oxide films 5 in the first region R1 and those in the second region R2, the thickness of theantireflection film 10 could become uneven due to the effect of a viscosity or wettability of theantireflection film 10. Hence, where there is no difference between theoxide films 5 in the first region R1 and those in the second region R2, the line width of thegate electrode 13 could not be even. However, with this embodiment, it is possible to eliminate the difference in height between theelement region 1A and theoxide films 5 together with the difference between theelement region 1B and theoxide films 5, so that the thickness of theantireflection film 10 can be even regardless of its viscosity or wettability, thereby the line width of thegate electrodes 13 is even. - In the first embodiment, having regard to the condition that the etching rate of the
oxide film 5 formed in the first region R1 is greater than that of in the second region R2, theoxide films 5 formed in the second region R2 are thinned with the chemical solution such as HF prior to the elimination of theoxide films 7. However, when forming the p-MOS transistor in the first region R1 in conjunction with forming the n-MOS transistor in the second region R2, the etching rates of theoxide film 5 becomes adverse in the first region R1 and the second region R2. In other words, the etching rate of theoxide film 5 formed in the second region R2 becomes greater than that of in the first region R1. Thus, theoxide films 5 formed in the first region R1 should be thinned prior to removing theoxide film 7. In this regard, after the well and the channel implementations to theelement region 1A formed in the first region R1 as perFIG. 23 , theoxide films 5 formed in the first region R1 are etched using the first resist pattern P1 used in said well and channel implementations as a mask. In addition, a plurality of transistors can be formed in each region. - In the first embodiment, implementing two types of transistors, i.e., combined use of the n-MOS transistor and the p-MOS transistor, has been presented. However, where the type of ion, the accelerating voltage or dosage used in the well/channel implementation differ from the combination mentioned above, a combination of n-MOS transistor and n-MOS transistor, or p-MOS transistor and p-MOS transistor can be used, or further, three or more types of transistors can be used together.
- Furthermore, where it is proven that the
oxide films 5 formed in either of the first region R1 or the second region R2 are lower than theelement region oxide films 5 can be higher than theelement region silicon nitride film 3, in polishing the oxide films 5 (refer toFIG. 5 ). Thus, the upper portion of theelement element silicon trench 1T are covered with theoxide film 5 so that the deterioration of the transistor performance caused by leak current and so on can be prevented. - As previously described, in the first embodiment, the
oxide films 5 formed in the first region R1 or the second region R2 are etched by using the chemical solution such as HF after completing the well/channel implementation to either the first region R1 or the second region R2. However, for example, theoxide films 5 can be etched using chemical solution such as HF after completing both well and channel implementations to both first region R1 and second region R2. - Hereinafter, forming three types of transistors, i.e., the 1 st- 3 rd transistors, on the
silicon substrate 1 in this variation will be discussed. InFIG. 25-28 , the code R3 denotes the third region wherein the third transistor is formed and thecode 1C denotes an element region formed in said third region R3. - Where the prior embodiment illustrates that “when the
oxide films 7 are removed with chemical solution such as HF, theoxide films 5 formed in the first region R1 are etched by α and theoxide films 5 formed in the second region R2 are etched β(<α) and theoxide films 5 formed in the third region R3 are etched γ(<β), as perFIG. 25 , firstly the seventh resist pattern P7 is formed by the lithography method. The seventh resist pattern P7 covers the first region R1, and exposes the second region R2 and the third region R3. Using the seventh resist pattern P7 as a mask, theoxide films 5 formed in the second region R2 and the third region R3 are etched by α−β. Thus, the heights of theoxide films 5 in both first region R1 and second region R2 can be equalized after removing theoxide films 7 as perFIG. 26 . The seventh resist pattern P7 is an inversion pattern of the first resist pattern P1 used in the well implementation and the channel implementation to the first region R1. Thus where using the resist material of the first resist pattern P1 as negative resist and the resist material of the seventh resist pattern P7 as a positive resist, or conversely, the resist material of the first resist pattern P1 as a positive resist and the resist material of the seventh resist pattern P7 as a negative resist, the first resist pattern P1 and the seventh pattern P7 can be formed by using a common reticle. - Yet thinning the
oxide films 5 formed in the second region R2 and the third region R3 by α−β, theoxide films 5 in the first region R1, the second region R2 and the third region R3 could differ in height significantly after removing theoxide films 7. In such case, the eighth resist pattern P8 can be formed by the lithography method as perFIG. 27 if needed. The eighth resist pattern P8 covers the first and the second region R1 and R2 and exposes only the third region R3. Then using the eighth resist pattern P8 as a mask, the oxide film formed in the third region R3 is etched by α−β−γ using the chemical solution such as HF. With this approach, theoxide films 5 formed in the first, second and third region (R1, R2 and R3) can be equalized in height as perFIG. 28 . - In this variation, the
oxide films 5 are etched with the chemical solution such as HF before removing theoxide films 7, however, for example, after removing theoxide films 7, theoxide films 5 can be etched using the chemical solution such as HF. - As described above, in the first embodiment, the thickness of the gate insulator of the n-MOS transistor and that of the gate insulator of the p-MOS transistor is equal. Thus, the gate insulators can be formed simultaneously in the
element region 1A formed in the first region R1 and theelement region 1B formed in the second region R2. However, where forming a high-voltage-resistant transistor in any of the first, second or third region (R1, R2 or R3) and forming low-voltage-resistant transistors (core transistor) in other regions, the thicknesses of the gate insulators in the first region R1 and the second region R2 could differ. The gate insulator of the high-voltage-resistant transistor is thicker than that of the low-voltage-resistant transistor, so that where implementing both low-voltage- and high-voltage-resistant transistors, the gate insulators should be formed respectively in the first region R1 and the second region R2. - Hereinafter, forming the low-voltage-resistant transistor in the first region R1 and the high-voltage-resistant transistor in the second region R2, i.e., forming multigate transistors will be described.
- After removing the
oxide films 7 formed in theelement regions FIG. 29 ,silicon oxide films 20 are formed on theelement region 1A existing in the first region R1 and theelement region 1B existing in the first region R2. The thickness of thesilicon oxide films 20 should be the same thickness of the gate insulator of the high-voltage-resistant transistor formed in the second region R2. Here, the thickness of the gate insulator of the high-voltage-resistant transistor is defined as 10 nm. - Then, as per
FIG. 30 , the second region R2 is covered with a resist 18, and then thesilicon oxide films 20 formed in the first region R1 are removed by wet etching using the chemical solution such as HF. Thereafter, using the resist 18 as a mask,silicon oxide films 21 are formed in theelement region 1A existing in the first region R1. The thickness of thesilicon oxide films 21 is the same thickness of the gate insulator film of the low-voltage-resistant transistor formed in the first region R1. Here, the thickness of the gate insulator of the low-voltage-resistant transistor is defined as 1 nm. - As describe above, to form the low-voltage-resistant transistor in the first region R1 and the high-voltage-resistant transistor in the second region R2, the number of the etchings with the chemical solution of the first region R1 differs from that of the second region. Hence, the
oxide films 5 formed in the first region R1 wherein the low-voltage-resistant transistor is formed will be thinner than theoxide films 5 formed in the second region R2 wherein the high-voltage-resistant transistor is formed by the number of the chemical etching of thesilicon oxide films 20. In other words, theoxide films 5 formed in the first region R1 is thinner than those in the second region R2 by one chemical etching with HF. Thus, even where theoxide films 5 in both first region R1 and second region R2 are equal in height at the time when thesilicon oxide films 20 are formed as perFIG. 29 , theoxide films 5 have a variation in height as perFIG. 30 after completing the gate insulators for the low- and high-voltage-resistant transistors. - For that reason, as per
FIG. 31 , prior to forming thesilicon oxide films 20, the first region R1 wherein the low-voltage-resistant transistor is formed is covered with a resistpattern 19, then theoxide films 5 formed in the second region R2 is etched using the chemical solution such as HF. For example, where the condition that theoxide films 5 formed in the first region R1 are etched by δ by one chemical etching using the chemical solution such as HF, then theoxide films 5 formed in the second region R2 are etched by δ preliminary. Thus, where the chemical solution such as HF is provided onto the first region R1 in the forming process of the low- and high-voltage-resistant transistors, the difference of theoxide films 5 in the first region R1 and the second region R2 in height can be avoidable as perFIG. 32 . Therefore, theoxide films 5 are etched preliminary inasmuch as that the number of times of chemical etching using HF to the first region R1 is different from that to the second region in this example. - [Method of manufacturing a semiconductor device in the second embodiment]
- Referring to
FIG. 33-41 , the method of manufacturing the semiconductor device in the second embodiment will be discussed concretely. After finishing the well and the channel implementations to theelement regions oxide film 30 is deposited over theoxide films 5 and theoxide films 7 by the HDP-CVD as perFIG. 33 . The thickness of theoxide film 30 is defined as 100-200 nm here. In the second embodiment, theoxide film 30 is used, however, TEOS (tetra ethyl ortho silicate) can be used as an alternative. - Next, as per
FIG. 34 , theoxide film 30 is polished to the thickness of approximately 50-100 nm, to level its surfaces. - Then, as per
FIG. 35 , anantireflection film 31 and then photoresists 32 are coated on the surface of theoxide film 30 by the spin coating. Thereafter, patterning thephotoresists 32 by the photolithography method, the ninth resist pattern P9 is formed on theantireflection film 31. The ninth resist pattern P9 exposes the regions where theelement regions oxide films 5 exist. - Thereafter, as per
FIG. 36 , using the ninth resist pattern P9 as a mask, theantireflection film 31 and theoxide film 30 are removed by the dry etching. Thus, the surfaces of theoxide films 7 are exposed. In the second embodiment, the dry etching is used to expose the surfaces of theoxide films 30. However, alternatively, the wet etching can be used in conjunction with the dry etching. Thus, as perFIG. 37 , theoxide film 30 deposited on theoxide films 7 can be etched to the thickness of approximately 10-30 nm by the dry etching and then theresidual oxide film 30 on the surfaces ofoxide films 7 can be removed by the wet etching using the chemical solution such as HF as perFIG. 38 . After exposing theoxide films 7, the ninth resist pattern P9 and theantireflection film 31 can be removed. - Then, as per
FIG. 39 , theoxide films 7 are removed by the wet etching using the chemical solution such as HF. In this process, theoxide film 30 deposited over theoxide films 5 are etched due to the wet etching. However, theoxide film 30 is formed after the well/channel implementation so that the etching rates of theoxide film 30 are equal in the first region R1 and the second region R2. Thus, when the chemical solution such as HF is used to remove theoxide films 7 after the well/channel implementation, theoxide film 30 is level in both first and second region (R1 and R2). - In the second embodiment, the case is where the surfaces of the
oxide films 5 are higher than those of theelement regions oxide films 7. - However for example, as per
FIG. 40 , the surfaces of theoxide films 5 can be lower than those in theelement regions oxide films 7. If the surfaces of theoxide films 5 are lower than those of theelement regions oxide film 30 in the first region R1 and the second region R2 are the same even where theoxide film 30 is etched to the same height of the surfaces of theelement regions FIG. 41 , the difference between theelement region 1A formed in the first region R1 and theoxide films 5 formed in the first region R1 can be readily eliminated together with the difference between theelement region 1B formed in the second region R2 and theoxide films 5 formed in the second region R2. Furthermore, theoxide film 30 covers the surfaces of theelement regions trench 1T, viz., theoxide films 5 and theoxide films 30 having the lower ion concentration compared to theoxide film 5 bury thetrench 1T.
Claims (3)
1. A semiconductor device, comprising:
a semiconductor substrate where a plurality of element regions are defined with a trench on a surface of said semiconductor substrate;
an oxide film buried in said trench;
a gate insulator film formed on a surface of a plurality of said element regions;
a gate electrode formed on a surface of said gate insulator film,
wherein at least a part of said oxide film includes a first layer and a second layer deposited on said first layer with lower density of an ion compared to the first layer.
2. The semiconductor device according to claim 1 , wherein:
a height of said oxide film from the surface of said element region to the surface of said oxide film is equal.
3. The semiconductor device according to claim 1 , wherein:
an upper surface of said oxide film and an upper surface of said element regions are level to each other.
Priority Applications (1)
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US13/232,402 US20120001265A1 (en) | 2007-03-30 | 2011-09-14 | Method of manufacturing semiconductor device which a plurality of types of transistors are mounted |
Applications Claiming Priority (4)
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JP2007090775A JP5446068B2 (en) | 2007-03-30 | 2007-03-30 | Manufacturing method of semiconductor device |
JP2007-090775 | 2007-03-30 | ||
US12/053,089 US8039358B2 (en) | 2007-03-30 | 2008-03-21 | Method of manufacturing semiconductor device on which a plurality of types of transistors are mounted |
US13/232,402 US20120001265A1 (en) | 2007-03-30 | 2011-09-14 | Method of manufacturing semiconductor device which a plurality of types of transistors are mounted |
Related Parent Applications (1)
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US12/053,089 Division US8039358B2 (en) | 2007-03-30 | 2008-03-21 | Method of manufacturing semiconductor device on which a plurality of types of transistors are mounted |
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US20120001265A1 true US20120001265A1 (en) | 2012-01-05 |
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Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
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US12/053,089 Expired - Fee Related US8039358B2 (en) | 2007-03-30 | 2008-03-21 | Method of manufacturing semiconductor device on which a plurality of types of transistors are mounted |
US13/232,402 Abandoned US20120001265A1 (en) | 2007-03-30 | 2011-09-14 | Method of manufacturing semiconductor device which a plurality of types of transistors are mounted |
Family Applications Before (1)
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US12/053,089 Expired - Fee Related US8039358B2 (en) | 2007-03-30 | 2008-03-21 | Method of manufacturing semiconductor device on which a plurality of types of transistors are mounted |
Country Status (4)
Country | Link |
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US (2) | US8039358B2 (en) |
JP (1) | JP5446068B2 (en) |
KR (2) | KR101047379B1 (en) |
TW (1) | TWI382494B (en) |
Families Citing this family (3)
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JP5401797B2 (en) * | 2008-02-06 | 2014-01-29 | 富士通セミコンダクター株式会社 | Semiconductor device manufacturing method and semiconductor device manufacturing system |
JP5319240B2 (en) * | 2008-10-30 | 2013-10-16 | 富士通株式会社 | Manufacturing method of semiconductor device |
KR101666403B1 (en) * | 2010-06-09 | 2016-10-17 | 삼성전자 주식회사 | Fabricating method of semiconductor device |
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- 2008-03-21 TW TW097110028A patent/TWI382494B/en not_active IP Right Cessation
- 2008-03-28 KR KR1020080028928A patent/KR101047379B1/en active IP Right Grant
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2010
- 2010-06-14 KR KR1020100056228A patent/KR101043304B1/en active IP Right Grant
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Also Published As
Publication number | Publication date |
---|---|
KR101043304B1 (en) | 2011-06-22 |
KR101047379B1 (en) | 2011-07-07 |
TWI382494B (en) | 2013-01-11 |
US20080237812A1 (en) | 2008-10-02 |
US8039358B2 (en) | 2011-10-18 |
KR20100077134A (en) | 2010-07-07 |
JP2008251800A (en) | 2008-10-16 |
TW200910516A (en) | 2009-03-01 |
KR20080089253A (en) | 2008-10-06 |
JP5446068B2 (en) | 2014-03-19 |
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