KR20040069401A - Method for protecting loss of isolation layer in semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent loss of an isolation layer by forming a capping nitride layer on the isolation layer. CONSTITUTION: A trench is formed by selectively etching a substrate(21) of a field region. An isolation layer is formed by filling an HDP oxide layer(26) in the trench. A capping nitride layer(27) is formed on the isolation layer so as to prevent loss of the HDP oxide layer. Then, a gate insulating layer(29) and a gate electrode(30) are sequentially formed on the substrate of an active region. Then, the capping nitride layer is removed.

Description

Method for manufacturing a semiconductor device preventing the loss of the device isolation layer {Method for protecting loss of isolation layer in semiconductor device}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a semiconductor device having improved characteristics of a device by applying a capping nitride film on an isolation layer to prevent damage to a field oxide film generated in a subsequent process. It relates to a method for manufacturing a device.

When fabricating a semiconductor device, an element isolation film is formed to electrically isolate the device. As a method of forming such a device isolation layer, a local trench method using a thermal oxide film (Local Oxidation of Silicon: LOCOS) and a shallow trench isolation method (STI) using a trench structure which is advantageous for integration are used. This is applied a lot.

The trench trench isolation (STI) process is a process instability factor such as deterioration of the field oxide film due to the reduction of design rules of the semiconductor device, and the reduction of the active area due to the bird's beak. It is emerging as a device isolation process that can fundamentally solve the same problem, and it is a promising technology to be applied to an ultra-high density semiconductor device manufacturing process of 1G DRAM or 4G DRAM level.

A process of forming a trench isolation layer according to the prior art will be described with reference to FIGS. 1A to 1F. First, as shown in FIG. 1A, a surface oxide film 12 and a surface nitride film 13 are stacked on a substrate 11. Next, a photoresist film 14 is formed on the surface nitride film 13 and patterned to expose a predetermined surface of the surface nitride film 13.

Using the patterned photosensitive film 14, the exposed surface nitride film 14 and the surface oxide film 13 are sequentially etched to expose the surface of the substrate 11. Next, the photosensitive film 14 and the surface nitride film 13 are exposed. ) Is used as an etching barrier to form a trench structure by etching the substrate 11 to a predetermined depth (STI etching).

Next, after removing the photoresist layer 14, a thermal oxide layer on the sidewalls and the bottom surface of the trench structure is used to compensate for substrate damage due to micro trenches and plasma etching generated in the STI etching process as shown in FIG. 1B. 15).

Next, as shown in FIG. 1C, a trench structure is embedded with an isolation layer to separate the device into an active region and a field region. In recent years, an excellent high density plasma (HDP) oxide film 16 having a stepped coating is used. It is widely used as a separator. When the HDP oxide film is used as the device isolation film, the trench structure is filled with the HDP oxide film 16, and then a thermal process for increasing the density of the HDP oxide film 16 is performed.

Since the HDP oxide layer 16 is not only formed by filling the trench structure, but also thickly deposited on the active region, an etching process using an appropriate mask is performed to remove the HDP oxide layer formed on the active region, thereby reducing the step difference.

Subsequently, chemical vapor deposition (CMP) is applied to form a stable device isolation film 16, wherein the surface nitride film 13 serves as an etch stop layer of chemical mechanical polishing. That is, chemical mechanical polishing is performed until the surface nitride film 13 is exposed to planarize the surface of the HDP oxide film 16 as shown in FIG. 1C.

Next, as illustrated in FIG. 1D, the surface nitride film 13 used as the etch stop layer in the CMP process is removed by a wet etching method using phosphoric acid. Next, in order to perform the gate forming process, the remaining surface oxide film 12 is removed by a wet etching method using HF.

After such a process, a series of ion implantation processes for forming an element are performed, and then a process for forming a gate electrode is performed. That is, after forming the gate insulating film 17 on the substrate 11 from which the surface oxide film has been removed and laminating the gate polysilicon 18 on the gate insulating film 17, the etching process using a mask is performed to perform the gate Pattern the electrode. FIG. 1E is a view showing a gate electrode formed of a gate insulating film 17 and a gate polysilicon 18 formed on a substrate.

Conventionally, in the etching process for patterning the gate electrode, since the field region in which the device isolation film is formed is also exposed to the etching process, the device isolation film 16 embedded in the trench structure also has the disadvantage of being etched.

After forming the gate electrode as described above, a series of ion implantation processes are performed, and then a process of forming spacers on both sidewalls of the gate electrode is performed. As shown in FIG. 1F, the spacer oxide layer 19 and the spacer nitride layer 20 are sequentially stacked on the substrate 11 including the gate electrode, and then blanket dry etching is performed. Thus, spacers are formed on both sidewalls of the gate electrode.

In the related art, since the field region in which the blanket dry etching device isolation layer is formed is exposed, the device isolation layer 16 filling the trench structure is also etched and the device isolation layer 16 is lost.

After forming the spacers as described above, an ion implantation process for forming source / drain regions is performed, followed by a process for forming silicide.

In semiconductor devices, there are regions in which silicides are to be formed, while in the semiconductor devices, there are regions in which silicides should not be formed. Therefore, in order to selectively form the silicide, the silicide forming process may be selectively performed by first forming the silicide barrier layer on the entire structure, and then selectively removing only the silicide barrier layer existing in the region where the silicide is to be formed. Can be.

The etching process for selectively removing the silicide prevention layer is also performed by blanket dry etching, and the field region is exposed. Therefore, even in this case, there is a disadvantage in that the HDP oxide film having the trench structure embedded is etched and lost.

In addition to the etching process described above, in the cleaning process performed essentially in various process steps, since the HDP oxide embedded with the trench structure is often lost, a method of preventing the same is required.

When the HDP oxide film used as the device isolation film is lost, a leakage current occurs at the interface between the field region and the active region, thereby degrading the characteristics of the device, or at the interface between the field region and the active region when silicide is formed. There was a disadvantage that the silicide was formed thin. In addition, in the contact etching process, the contact hits the field area and adversely affects the active area.

The present invention is to solve the above problems, to provide a semiconductor device manufacturing method that prevents the deterioration of device characteristics by forming a capping nitride film on the trench device isolation film to minimize the loss of the device isolation film in a subsequent process. For the purpose.

1A to 1F are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the prior art;

2A through 2J are cross-sectional views illustrating a process of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

21 substrate 22 surface oxide film

23 surface nitride film 24 first mask

25: thermal oxide film 26: HDP oxide film

27 capping nitride film 28 second mask

29 gate insulating film 30 gate electrode

31 oxide film for spacer 32 nitride film for spacer

The present invention for achieving the above object, the step of forming a trench by etching a portion of the semiconductor substrate in the field region deep; Filling an oxide-based film as an isolation layer in the trench; Forming a capping nitride film only on the device isolation film in order to prevent damage to the device isolation film in a subsequent process; Proceeding to a subsequent process; And removing the capping nitride film.

In addition, the present invention may include forming a trench by partially etching the semiconductor substrate in the field region; Filling an oxide-based film as an isolation layer in the trench; Forming a capping nitride film only on the device isolation film in order to prevent damage to the device isolation film in a subsequent process; Patterning a gate electrode on the semiconductor substrate in an active region; Forming spacers on both sidewalls of the gate electrode; Forming a silicide film in a predetermined region on the semiconductor substrate; And removing the capping nitride film.

The present invention prevents deterioration of device characteristics by applying a capping nitride layer on the trench isolation layer to minimize the loss of the isolation layer in a subsequent etching or cleaning process.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention.

2A through 2J are cross-sectional views illustrating a process of fabricating a semiconductor device in accordance with an embodiment of the present invention. A method of manufacturing a semiconductor device in accordance with an embodiment of the present invention will be described with reference thereto.

Referring to FIG. 2A, first, the surface oxide film 22 is deposited on the substrate 21 to a thickness of about 100 GPa, and then the surface nitride film 23 to serve as an etch stop layer in a subsequent CMP process is about 2000 GPa. It is formed by laminating on the surface oxide film 22.

Next, the photoresist film 24 is coated on the surface nitride film 23 and patterned to form a first mask 24 exposing a predetermined surface of the surface nitride film 23. A positive photoresist film is used as the photoresist film 24, and a reticle used to pattern the photoresist film 24 is also used in a subsequent process, which will be described later.

By using the patterned first mask 24, the exposed surface nitride film 24 and the surface oxide film 23 are sequentially etched to expose a predetermined surface of the substrate 21. Next, using the first mask 24 and the surface nitride film 23 as an etching barrier, the substrate 21 is etched to a certain depth to form a trench structure (STI etching). The first mask 24 is then removed.

Next, as shown in FIG. 2B, the surface oxide film 22 is recessed by about 100 kPa using the wet etching method, and the surface nitride film 23 is recessed by about 500 kPa by the wet etching method using phosphoric acid. .

The reason why the surface oxide film 22 and the surface nitride film 23 are recessed is that the interface between the active area and the field area is covered with an isolation layer to effectively solve the problems occurring at the interface between the active area and the field area. In order to solve the problem, the surface oxide film 22 and the surface nitride film 23 may be formed as in the prior art without recess.

Subsequently, a thermal oxide layer 25 is formed on the sidewalls and the bottom of the trench structure to compensate for damage due to micro trenches and plasma etching generated in the STI etching process.

Next, in order to separate the device into the active region and the field region, the trench structure is embedded with a high density plasma (HDP) oxide layer 26, and then a thermal process for increasing the density of the HDP oxide layer 26 is performed. Perform. Since the HDP oxide layer 26 not only fills the trench structure but is also thickly deposited on the active region, an etching process using an appropriate mask is performed to remove the HDP oxide layer formed on the active region, thereby reducing the step difference.

Subsequently, chemical vapor deposition (CMP) is applied to form a stable device isolation layer 26, wherein the surface nitride layer 23 serves as an etch stop layer of chemical mechanical polishing. That is, the surface of the HDP oxide film 26 is planarized by performing chemical mechanical polishing until the surface nitride film 23 remains about 600 kPa.

In one embodiment of the present invention, an HDP oxide film is used as a device isolation film to fill a trench structure, but other types of oxide films may be used as the device isolation film. Next, as shown in Figure 2d, the surface nitride film 13 used as an etch stop layer in the CMP process is removed by a wet etching method using phosphoric acid.

Subsequently, as shown in FIG. 2E, a capping nitride film 27 is formed to a thickness of 400 to 600 kPa on the entire structure including the HDP oxide film 26. As shown in FIG. Next, a negative photoresist 28 is applied onto the capping nitride film 27 formed on the entire structure.

The negative photoresist is used to form a second mask for selectively removing the capping nitride film 27, and the negative photoresist is patterned with a second mask 28 covering only the HDP oxide film 26 formed in the field region. That is, since the negative photoresist has a property of remaining only the exposed portion and removing the unexposed portion, the negative photoresist is used on the field region by using the reticle used to pattern the photoresist film 24 of FIG. 2A as it is. Only the negative photoresist formed is exposed by exposure, and the negative photoresist formed on the active region is removed.

Subsequently, the capping nitride layer 27 is selectively removed by applying a wet etching method using the remaining second mask 28 as shown in FIG. 2E. Then, as shown in FIG. 2F, the capping nitride layer 27 is removed. Except for the covered capping nitride layer 27, the remaining capping nitride layer 27 formed on the active region is removed. Next, the remaining second mask 28 is removed.

Next, in order to perform the gate forming process, the surface oxide film 22 remaining on the substrate is removed by a wet etching method using HF. The removal of the surface oxide film 22 in this manner is illustrated in FIG. 2F.

After such a process, a series of ion implantation processes for forming an element are performed, and then a process for forming a gate electrode is performed. That is, the gate insulating film 29 is formed on the active region, and the gate polysilicon 30 is laminated on the entire structure including the gate insulating film 29. In this case, the gate polysilicon 30 is also formed on the capping nitride layer 27 located in the field region.

After the gate polysilicon is formed in this manner, an etching process using a mask is performed to pattern the gate electrode. FIG. 2E shows a state in which a gate electrode composed of a gate insulating film 27 and a gate polysilicon 28 is formed on a substrate.

Conventionally, in the etching process for patterning the gate electrode, since the field portion is also exposed, the HDP oxide layer 26 embedded in the trench structure also has the disadvantage of being etched, but in one embodiment of the present invention, the HDP oxide layer 26 is used. Since the capping nitride film 27 is formed on it, the loss of the HDP oxide film 26 can be prevented.

That is, the gate polysilicon formed in the field region is removed during the etching process for gate patterning, and the etching stops at the capping nitride layer 27. This is because the etching selectivity of the gate polysilicon 30 and the capping nitride layer 27 is high, and when the gate polysilicon 30 formed in the field region is etched, the etching stops naturally. FIG. 2G illustrates the gate electrode patterned in this manner. FIG.

After forming the gate electrode as described above, a series of ion implantation processes are performed, and then a process of forming spacers on both sidewalls of the gate electrode is performed. The spacer is formed by sequentially stacking a spacer oxide film and a spacer nitride film on a substrate including a gate electrode, and then performing blanket dry etching to form spacers on both sidewalls of the gate electrode.

This will be described below. First, as shown in FIG. 2H, a spacer oxide film 31 is formed on the substrate 21 including the gate electrodes 29 and 30 to a thickness of about 150 Å. At this time, since the capping nitride film 27 is formed at the top of the field region, the spacer oxide film 31 is not formed on the capping nitride film 27 but is formed only on the active region.

Next, as shown in FIG. 2I, a spacer nitride film 32 is formed on the upper portion of the capping nitride film 27 and the spacer oxide film 31 to a thickness of about 800 mm 3. In this case, since the capping nitride layer 27 and the spacer nitride layer 32 are formed of the same nitride layer, the spacer nitride layer 32 may be formed on the capping nitride layer 27.

Since the capping nitride film 27 is formed to have a thick thickness of about 400 to 600 micrometers from the beginning, the capping nitride film 27 is etched to some extent while protecting the device isolation layer 26 during various subsequent processes. It has a thickness.

As such, when the nitride nitride film 32 for spacers having a thickness of 800 GPa is formed on the capping nitride film 27 having a thickness of 200 GPa or more, a nitride film having a total thickness of 1000 GPa or more is formed in the field region. This is shown in Fig. 2i.

Next, a blanket dry etching for forming a spacer is performed. Through the blanket dry etching, the spacer nitride film 32 and the spacer oxide film 31 are removed in the active region, thereby forming a spacer on the sidewall of the gate electrode as shown in FIG. 2J.

In the related art, since the blanket dry etching field part is exposed, the HDP oxide layer 26 is lost. However, in the exemplary embodiment of the present invention, since the nitride layer is formed to have a thickness of 1000 μm or more on the field region, Even if all of the spacer nitride films 32 formed in the field region are etched and removed, 200 nm or more of the nitride film remains in the field region. Thus, the remaining nitride layer protects the HDP oxide layer 26 from the blanket dry etching.

That is, while the spacer oxide film 31 in the active region is etched through the blanket dry etching, the nitride film remaining in the field region has a high selectivity, so the etching is not easy, and the HDP oxide layer 26 filling the trench structure is not etched. Protects.

After forming the spacers as described above, an ion implantation process for forming source / drain regions is performed, followed by a process for forming silicide.

In semiconductor devices, there are regions in which silicides are to be formed, while in the semiconductor devices, there are regions in which silicides should not be formed. Therefore, in order to selectively form the silicide in this manner, a silicide prevention layer (not shown), which is an oxide-based layer, is first formed to a thickness of about 1000 상 에 on the entire structure, and only the silicide prevention layer existing in the region where silicide is to be formed is selectively removed, This is done.

Since the silicide prevention film is also an oxide film series, the silicide prevention film is not formed in the field region where the capping nitride film remains, and the silicide prevention film is formed only in the active region.

The etching process for selectively removing the silicide prevention layer also proceeds to a blanket dry etching, and the capping nitride layer existing on the field region protects the device isolation layer 26 from the blanket dry etching process.

In addition to the etching process described above, in the cleaning process performed essentially in various process steps, the device isolation layer 26 is prevented from being lost due to the presence of the capping nitride layer 27 covering the device isolation layer 26 embedded in the trench. can do.

In the exemplary embodiment of the present invention, the gate electrode patterning process, the spacer forming process, and the silicide forming process are exemplified. In addition, the capping nitride film formed in the field region is removed by wet etching after all the processes that cause damage to the device isolation film are performed. do.

According to the present invention, by applying a capping nitride layer on the trench isolation layer, the loss of the isolation layer can be prevented to improve the characteristics of the semiconductor device, and also corresponds to the boundary between the field region and the active region. Covering the end with the device isolation film can contribute to the improvement of device characteristics.

As described above, the present invention is not limited to the above-described embodiments and the accompanying drawings, and the present invention may be variously substituted, modified, and changed without departing from the spirit of the present invention. It will be apparent to those of ordinary skill in Esau.

The present invention as described above can prevent the loss of the trench device isolation film that can occur in a number of processes has the effect of preventing the deterioration of the characteristics of the semiconductor device.

Claims (6)

Etching a portion of the semiconductor substrate in the field region to form a trench; Filling an oxide-based film as an isolation layer in the trench; Forming a capping nitride film only on the device isolation film in order to prevent damage to the device isolation film in a subsequent process; Proceeding to a subsequent process; And Removing the capping nitride layer Method of manufacturing a semiconductor device comprising a. Etching a portion of the semiconductor substrate in the field region to form a trench; Filling an oxide-based film as an isolation layer in the trench; Forming a capping nitride film only on the device isolation film in order to prevent damage to the device isolation film in a subsequent process; Patterning a gate electrode on the semiconductor substrate in an active region; Forming spacers on both sidewalls of the gate electrode; Forming a silicide film in a predetermined region on the semiconductor substrate; And Removing the capping nitride layer Method of manufacturing a semiconductor device comprising a. The method according to claim 1 or 2, Forming a capping nitride film only on the device isolation film, Forming a capping nitride film on the substrate including the device isolation film; Applying and patterning a negative photoresist on the capping nitride layer to form a mask covering only the capping nitride layer corresponding to the device isolation layer; Removing the capping nitride layer using the mask to leave a capping nitride layer only on the device isolation layer Method for producing a semiconductor device, characterized in that further comprises. The method of claim 3, wherein In the step of forming a capping nitride film on the substrate including the device isolation film, The capping nitride film is a manufacturing method of a semiconductor device, characterized in that formed to have a thickness of 400 ~ 600Å. The method of claim 2, Forming spacers on both sidewalls of the gate electrode, Forming an oxide film for a spacer on a substrate including an active region and a gate electrode by a thermal process; Forming a spacer nitride film on the device isolation layer and on the spacer oxide film; Performing spacer etching to form spacers on both sidewalls of the gate electrode Method for producing a semiconductor device, characterized in that further comprises. The method of claim 2, Forming silicide in a predetermined region on the substrate, Forming an oxide suicide preventing film on the substrate; And Removing the silicide prevention layer in the region where silicide is to be formed by an entire surface etching process Method of manufacturing a semiconductor device further comprising.