US20110163459A1 - Method for manufacturing a stacked semiconductor package, and stacked semiconductor package - Google Patents
Method for manufacturing a stacked semiconductor package, and stacked semiconductor package Download PDFInfo
- Publication number
- US20110163459A1 US20110163459A1 US13/051,179 US201113051179A US2011163459A1 US 20110163459 A1 US20110163459 A1 US 20110163459A1 US 201113051179 A US201113051179 A US 201113051179A US 2011163459 A1 US2011163459 A1 US 2011163459A1
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- semiconductor chips
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Definitions
- the semiconductor chips are electrically connected with a board by means of wiring and the semiconductor chips are electrically connected with one another by means of wiring.
- the wires to be used are shaped in loop so as to prevent unnecessary electric connection with other parts (such as the corner of each semiconductor chip) except the electrodes and the occurrence of leak current. As a result, the total thickness of the semiconductor package is increased.
- the semiconductor chips are electrically connected with one another by a wiring layer formed at the side of the stacking structure of the semiconductor chips (e.g., refer to JP-A2004-63569 (KOKAI)).
- a wiring layer formed at the side of the stacking structure of the semiconductor chips
- an insulating layer is formed between the side of the stacking structure and the wiring layer so as to form the electric insulation between the side of the stacking structure and the wiring layer.
- the insulating layer is formed per semiconductor chip. Concretely, the insulating layer is formed at the side of each semiconductor chip. Therefore, it is required that the forming process of the insulating layer is carried out for all of the semiconductor chips to be stacked. Since the number of the forming process of the insulating layer is increased as the number of the semiconductor chips to be stacked is increased, the manufacturing process of the stacked semiconductor package becomes complicated as a whole so as to increase the manufacturing cost of the stacked semiconductor package.
- the insulating layer is made of a thermosetting resin, it is required that the assembly under construction including the board is thermally treated as a whole. As a result, the assembly suffers from the thermal treatment several times so that the board and/or one or more of the semiconductor chips may be warped and the characteristics of one or more of the semiconductor chips may be changed.
- the adjacent ones of the semiconductor chips are bonded with one another with adhesive.
- the adhesive may be peeled off by the several thermal treatments so that the adjacent ones of the semiconductor chips are imperfectly bonded with one another.
- An aspect of the present invention relates to a method for manufacturing a stacked semiconductor package where a plurality of semiconductor chips are stacked on a substrate, including: forming insulating layers at portions of a wafer corresponding to sides of the plurality of semiconductor chips when the plurality of semiconductor chips are in the wafer;
- processing the wafer so as to obtain the plurality of semiconductor chips subsequently stacking the plurality of semiconductor chips on the substrate such that the insulating layers formed at the sides of the plurality of semiconductor chips are respectively positioned at the same side as one another; and forming a wiring over the insulating layers formed at the sides of the plurality of semiconductor chips so that the plurality of semiconductor chips are electrically connected with one another and one or more of the plurality of semiconductor chips are electrically connected with the substrate.
- Another aspect of the present invention relates to a stacked semiconductor package, including: a substrate; a plurality of semiconductor chips subsequently formed on the substrate and having respective insulating layers at sides thereof such that the insulating layers of the plurality of semiconductor chips are positioned at the same side as one another; and a wiring formed over the insulating layers at the sides of the plurality of semiconductor chips so that the plurality of semiconductor chips are electrically connected with one another and one or more of the plurality of semiconductor chips is electrically connected with the substrate.
- FIGS. 1 to 4 , 6 , 7 and 8 are cross sectional views showing a first step in the forming method of a stacked semiconductor package according to an embodiment.
- FIG. 5 is a cross sectional view showing a step modified from the step shown in FIG. 4 .
- FIG. 9 is a cross sectional view showing a step modified from the step shown in FIG. 8 .
- FIGS. 10 and 11 are cross sectional views showing a stacked semiconductor package according to an embodiment.
- FIGS. 12 to 14 are cross sectional views showing a first step in the forming method of a stacked semiconductor package according to a second embodiment.
- FIG. 15 is a cross sectional view showing a step after the step shown in FIG. 14 .
- the insulating layer is formed per semiconductor chip. Concretely, the insulating layer is formed at the side of each semiconductor chip. Therefore, it is required that the forming process of the insulating layer is carried out for all of the semiconductor chips to be stacked. Since the number of the forming process of the insulating layer is increased as the number of the semiconductor chips to be stacked is increased, the manufacturing process of the stacked semiconductor package becomes complicated as a whole so as to increase the manufacturing cost of the stacked semiconductor package.
- the insulating layer is made of a thermosetting resin, it is required that the assembly under construction including the board is thermally treated as a whole. As a result, the assembly suffers from the thermal treatment several times so that the board and/or one or more of the semiconductor chips may be warped and the characteristics of one or more of the semiconductor chips may be changed.
- the adjacent ones of the semiconductor chips are bonded with one another with adhesive.
- the adhesive may be peeled off by the several thermal treatments so that the adjacent ones of the semiconductor chips are imperfectly bonded with one another.
- FIGS. 1 to 9 relate to the manufacturing process of a stacked semiconductor device according to a first embodiment.
- attention is paid to a portion of a wafer so as to clarify the distinctive features of the first embodiment.
- the portion of the wafer to which attention is paid is enlargedly depicted.
- electrodes 11 are formed of electric conductor such as aluminum on a wafer 10 made of, e.g., silicon, and first trenches 10 A are formed at the area except the electrodes 11 of the wafer 10 by means of so-called dicing before grinding (DBG) so as not to penetrate the wafer 10 .
- DSG dicing before grinding
- insulating resins 12 are formed by ink-jet or printing so as to embed the first trenches 10 A.
- the diameter of the forefront of the nozzle is set to a predetermined size so that the insulating resin 12 is discharged for the first trenches 10 A.
- the printing method a mask with a pattern in accordance with the shapes and sizes of the first trenches 10 A and the desired pattern to be formed is prepared, and the insulating resins 12 are printed and formed via the mask so as to embed the first trenches 10 A.
- a part of the insulating resin 12 is provided on a top surface of the wafer with the elements being exposed.
- As the insulating resin 12 may be exemplified thermoplastic resin and UV cured resin.
- dicing process is carried out for the insulating resins 12 formed in the first trenches 10 A to form second trenches 12 A reaching to the wafer 10 throughout the insulating resins 12 , respectively.
- the remaining insulating resins 12 after the second trenches 12 A are formed constitutes the insulating layers at the sides of each semiconductor chip, the second trenches 12 A are formed so that the insulating layer can be formed as designed.
- the second trenches 12 A are formed in V-shape.
- the sides 12 B of the remaining insulating resins 12 are tapered by the formation of the second trenches 12 A so that the rising angles of the sides 12 B becomes relatively small.
- the remaining insulating resins 12 constitute the insulating layers at the sides of the semiconductor chips and the lower portions 12 C of the insulating resins 12 constitute the lower edge portions of the insulating layers of the semiconductor chip (refer to, FIGS. 8 and 9 ).
- That the rising angles of the insulating resins 12 are small means that the contacting angle ⁇ of the insulating layer of the upper semiconductor chip for the lower semiconductor chip is small (refer to, FIGS. 10 and 11 ). As a result, the insulating layer of the upper semiconductor chip is smoothly contacted with the lower semiconductor chip.
- the wiring layers are formed over the insulating layers of the sides of the semiconductor chips, the wiring layers can not be disconnected between the upper semiconductor chip and the lower semiconductor chip.
- the wires can not be directly contacted with the semiconductor chips (particularly, the edges of the semiconductor chips) by the formation of the wiring layers. As a result, the manageability of the wires can be simplified.
- the second trenches 12 A may be formed in another shape except the V-shape shown in FIG. 3 as occasion demands.
- the second trenches 12 A may be formed so that the insulating resins 12 remain only at respective either sides of the first trenches 10 A.
- the insulating resins 12 remain at both sides of the first trenches 10 A, respectively, so that both sides of the resultant semiconductor chip are covered with the corresponding insulating layers.
- the second trenches 12 A are formed so that the insulating resins 12 are formed at respective either sides of the first trenches 10 A as shown in FIG. 4 , either side of the resultant semiconductor chip is covered with the corresponding insulating layer.
- the second trenches 12 of V-shape as shown in FIG. 3 are effective in the case where a plurality of semiconductor chips with respective different semiconductor chips are stacked subsequently and the second trenches 12 of V-shape as shown in FIG. 4 are effective in the case where a plurality of semiconductor chips are stacked slidably.
- the second trenches 12 A are formed so as to penetrate through the insulating resins 12 , but it is required that the depths of the second trenches 12 are set to predetermined depths enough to cut off and divide the wafer 10 into the semiconductor chips.
- a protective tape 15 is attached to the surface of the wafer 10 and the rear surface of the wafer 10 is grinded so as to thin the wafer 10 in a manner that the second trenches 12 A are opened as shown in FIG. 6 . In this way, the wafer 10 is divided into the semiconductor chips.
- an adhesive film 16 is attached to the rear surface of the wafer 10 (divided semiconductor chips), and by cutting the adhesive film 16 , the semiconductor chip(s) as shown in FIG. 8 can be obtained.
- the resultant semiconductor chip can be formed as shown in FIG. 9 .
- FIG. 10 is a cross sectional view showing a stacked semiconductor package formed by stacking the semiconductor chips as shown in FIG. 8 .
- FIG. 11 is a cross sectional view showing a stacked semiconductor package formed by stacking the semiconductor chips as shown in FIG. 9 .
- a first semiconductor chip 22 is stacked on a board 21 via an adhesive layer 27
- a second semiconductor chip 23 is stacked on the center area of the main surface of the first semiconductor chip 22 via an adhesive layer 28 .
- the insulating layers 24 made of the remaining insulating resins 12 are formed at both sides of the first semiconductor chip 22
- the insulating layers 25 made of the remaining insulating resins 12 are formed at both sides of the second semiconductor chip 23 .
- Apart of the insulating layers 24 and 25 is provided on a top surface of the first semiconductor chips 22 and 23 , respectively.
- the insulating layer 24 is elongated from a top surface of the first chip 22 to a top surface of the board 21 via a side of the first chip 22 and the adhesive layer 27 .
- the insulating layer 25 is elongated from a top surface of the second chip 23 to a top surface of the first chip 22 via a side of the second chip 23 and the adhesive layer 27 .
- wiring layers 26 are formed so as to cover the insulating layers 24 and 25 in a manner that electrodes 21 A formed on the board 21 are electrically connected with electrodes 22 A and 23 A formed on the semiconductor chips 22 and 23 , respectively.
- the first semiconductor chip 22 is stacked on the board 21 via the adhesive layer 27 and the second semiconductor chip 23 is stacked and shifted on the main surface of the first semiconductor chip 22 so as to expose the end portion of the first semiconductor chip 22 .
- the insulating layer 24 made of the remaining insulating resin 12 is formed at either side of the first semiconductor chip 22
- the insulating layer 25 made of the remaining insulating resin 12 is formed at either side of the second semiconductor chip 23 in the same side as the insulating layer 24 .
- wiring layers 26 are formed so as to cover the insulating layers 24 and 25 in a manner that the electrodes 21 A on the board 21 are electrically connected with the electrodes 22 A and 23 A on the semiconductor chips 22 and 23 , respectively.
- the insulating layers 24 and 25 for electrically insulating between the wiring layers 26 and the semiconductor chips 22 , 23 are formed before the semiconductor chips 22 and 23 are formed at the wafer processing process as described above. Namely, since the insulating layers 24 and 25 are formed at the wafer processing process for forming the semiconductor chips 22 and 23 , the manufacturing efficiency of the semiconductor chips 22 and 23 can be enhanced.
- the stacked semiconductor package 20 can be thinned as a whole.
- bonding wires which forms an arc, may be employed to electrically connect between the board 21 and the semiconductor chips 22 , 23 .
- FIGS. 12 to 15 relate to the manufacturing process of a stacked semiconductor device according to a second embodiment.
- attention is paid to a portion of a wafer so as to clarify the distinctive features of the first embodiment.
- the portion of the wafer to which attention is paid is enlargedly depicted.
- electrodes 31 are formed of electric conductor such as copper on a wafer 30 made of, e.g., silicon, and first trenches 30 A are formed at the area except the electrodes 31 of the wafer 30 by RIE (reactive ion etching) or laser processing so as not to penetrate the wafer 30 .
- RIE reactive ion etching
- a photosensitive member is applied onto the surface of the wafer 30 to form a photosensitive layer 32 so as to embed the first trenches 30 A.
- the photosensitive member can be made of well known material such as photosensitive resin typified by polyimide or resist.
- a mask with a pattern in accordance with the shapes and sizes of the first trenches 30 A and the desired pattern to be formed is prepared so that the photosensitive layer 32 is exposed and developed to form second trenches 32 A at the photosensitive layer 32 .
- the second trenches 32 A are formed so that the photosensitive layer 32 remains at both sides of the first trenches 30 A, respectively.
- the second trenches 32 A may be formed at respective either sides of the first trenches 30 A, as shown in FIG. 15 .
- the second trenches 32 A are formed as shown in FIG. 14 , since the photosensitive layer 32 remains at both sides of the first trenches 30 A,respectively, insulating layers are formed at both sides of each of the resultant semiconductor chips to be stacked. In the case that the second trenches 32 A are formed as shown in FIG. 15 , since the photosensitive layer 32 remains at respective either sides of the first trenches 30 A, insulating layers are formed at respective either sides of the resultant semiconductor chips to be stacked.
- the second trenches 12 as shown in FIG. 14 are effective in the case where a plurality of semiconductor chips with respective different semiconductor chips are stacked subsequently and the second trenches 12 as shown in FIG. 15 are effective in the case where a plurality of semiconductor chips are stacked slidably.
- the first trenches 30 A are shaped in inverted trapezoid.
- the rising angles of the remaining photosensitive layer 32 along the side walls of the first trenches 30 A become relatively small, respectively, originated from the (inverted trapezoid) shapes of the first trenches 30 A.
- the remaining photosensitive layer 32 constitutes the insulating layer(s) of the semiconductor chip as it is, and the lower portions 30 C of the photosensitive layer 32 constitute the lower edge portion(s) of the insulating layer(s) of the semiconductor chip ( FIGS. 8 and 9 ).
- That the rising angles of the remaining photosensitive layer 32 along the side walls of the first trenches 30 A are small means that the contacting angle ⁇ of the insulating layer of the upper semiconductor chip for the lower semiconductor chip is small ( FIGS. 10 and 11 ). As a result, the insulating layer of the upper semiconductor chip is smoothly contacted with the lower semiconductor chip.
- the wiring layers are formed over the insulating layers of the sides of the semiconductor chips, the wiring layers can not be disconnected between the upper semiconductor chip and the lower semiconductor chip.
- the wires can not be directly contacted with the semiconductor chips (particularly, the edges of the semiconductor chips) by the formation of the wiring layers. As a result, the manageability of the wires can be simplified.
- the first trenches 30 A may have another shape except the inverted trapezoid shape shown in FIG. 12 as occasion demands.
- a protective tape is attached to the surface of the wafer 30 and the rear surface of the wafer 30 is grinded so as to thin the wafer 30 in a manner that the second trenches 32 A are opened in the same manner as FIGS. 5 to 9 .
- the wafer 30 is divided into the semiconductor chips.
- An adhesive film is attached to the rear surface of the wafer 30 (divided semiconductor chips), and by cutting the adhesive film, the semiconductor chip(s) can be obtained.
- the stacked semiconductor package as shown in FIG. 10 can be formed through the step shown in FIG. 14
- the stacked semiconductor package as shown in FIG. 11 can be formed through the step shown in FIG. 15 .
- the stacked semiconductor package according to the second embodiment can exhibit the same function/effects as the stacked semiconductor package according to the first embodiment.
- the second trenches 12 A or 32 A are formed in addition to the first trenches 10 A or 30 A so as to divide the wafer into the semiconductor chips, and then, opened by grinding the rear surface of the wafer.
- laser irradiation may be conducted for the insulating resins 12 and photosensitive layer 32 formed in the first trenches 10 A and 30 A, respectively, so as to divide the wafer into the semiconductor chips, after the first trenches 10 A and 30 A are embedded by the insulating resins 12 and the photosensitive layer 32 , respectively.
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Abstract
A method for manufacturing a stacked semiconductor package where a plurality of semiconductor chips are stacked on a substrate, including: forming insulating layers at portions of a wafer corresponding to sides of the plurality of semiconductor chips when the plurality of semiconductor chips are in the wafer; processing the wafer so as to obtain the plurality of semiconductor chips; subsequently stacking the plurality of semiconductor chips on the substrate such that the insulating layers formed at the sides of the plurality of semiconductor chips are respectively positioned at the same side as one another; and forming a wiring over the insulating layers formed at the sides of the plurality of semiconductor chips so that the plurality of semiconductor chips are electrically connected with one another and one or more of the plurality of semiconductor chips are electrically connected with the substrate.
Description
- This application is a Division of application Ser. No. 12/249,025 filed on Oct. 10, 2008, which is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2007-266307, filed on Oct. 12, 2007; the entire contents of both of which are incorporated herein by reference.
- Various attempts are made so as to satisfy the requirements of increasing the capacity of a semiconductor memory and developing the function of the semiconductor memory. With the increase of the capacitor of the semiconductor memory, a plurality of thinner semiconductor chips are prepared and stacked so as to increase of the total capacity of the semiconductor memory in addition to the increase of the capacity of the semiconductor chip constituting the semiconductor memory. With the development of the semiconductor memory, a plurality of semiconductor chips with respective different functions are prepared and stacked to realize a semiconductor memory which can exhibit different functions.
- In a conventional stacked semiconductor package where a plurality of semiconductor chips are stacked as described above, one or more of the semiconductor chips are electrically connected with a board by means of wiring and the semiconductor chips are electrically connected with one another by means of wiring. In the wiring electric connection, however, the wires to be used are shaped in loop so as to prevent unnecessary electric connection with other parts (such as the corner of each semiconductor chip) except the electrodes and the occurrence of leak current. As a result, the total thickness of the semiconductor package is increased.
- In this point of view, it is proposed that the semiconductor chips are electrically connected with one another by a wiring layer formed at the side of the stacking structure of the semiconductor chips (e.g., refer to JP-A2004-63569 (KOKAI)). In this case, however, in order to prevent the electric connection between other parts of the semiconductor chips except the electrodes thereof, particularly between the side of the stacking structure of the semiconductor chips and the wiring layer, an insulating layer is formed between the side of the stacking structure and the wiring layer so as to form the electric insulation between the side of the stacking structure and the wiring layer.
- However, after the semiconductor chips are stacked, the insulating layer is formed per semiconductor chip. Concretely, the insulating layer is formed at the side of each semiconductor chip. Therefore, it is required that the forming process of the insulating layer is carried out for all of the semiconductor chips to be stacked. Since the number of the forming process of the insulating layer is increased as the number of the semiconductor chips to be stacked is increased, the manufacturing process of the stacked semiconductor package becomes complicated as a whole so as to increase the manufacturing cost of the stacked semiconductor package.
- Moreover, since the insulating layer is made of a thermosetting resin, it is required that the assembly under construction including the board is thermally treated as a whole. As a result, the assembly suffers from the thermal treatment several times so that the board and/or one or more of the semiconductor chips may be warped and the characteristics of one or more of the semiconductor chips may be changed.
- In the stacking of the semiconductor chips, the adjacent ones of the semiconductor chips are bonded with one another with adhesive. In this case, however, the adhesive may be peeled off by the several thermal treatments so that the adjacent ones of the semiconductor chips are imperfectly bonded with one another.
- An aspect of the present invention relates to a method for manufacturing a stacked semiconductor package where a plurality of semiconductor chips are stacked on a substrate, including: forming insulating layers at portions of a wafer corresponding to sides of the plurality of semiconductor chips when the plurality of semiconductor chips are in the wafer;
- processing the wafer so as to obtain the plurality of semiconductor chips; subsequently stacking the plurality of semiconductor chips on the substrate such that the insulating layers formed at the sides of the plurality of semiconductor chips are respectively positioned at the same side as one another; and forming a wiring over the insulating layers formed at the sides of the plurality of semiconductor chips so that the plurality of semiconductor chips are electrically connected with one another and one or more of the plurality of semiconductor chips are electrically connected with the substrate.
- Another aspect of the present invention relates to a stacked semiconductor package, including: a substrate; a plurality of semiconductor chips subsequently formed on the substrate and having respective insulating layers at sides thereof such that the insulating layers of the plurality of semiconductor chips are positioned at the same side as one another; and a wiring formed over the insulating layers at the sides of the plurality of semiconductor chips so that the plurality of semiconductor chips are electrically connected with one another and one or more of the plurality of semiconductor chips is electrically connected with the substrate.
-
FIGS. 1 to 4 , 6, 7 and 8 are cross sectional views showing a first step in the forming method of a stacked semiconductor package according to an embodiment. -
FIG. 5 is a cross sectional view showing a step modified from the step shown inFIG. 4 . -
FIG. 9 is a cross sectional view showing a step modified from the step shown inFIG. 8 . -
FIGS. 10 and 11 are cross sectional views showing a stacked semiconductor package according to an embodiment. -
FIGS. 12 to 14 are cross sectional views showing a first step in the forming method of a stacked semiconductor package according to a second embodiment. -
FIG. 15 is a cross sectional view showing a step after the step shown inFIG. 14 . - Some embodiments will be described with reference to the drawings.
- In a conventional method for manufacturing stacked semiconductor chips, after the semiconductor chips are stacked, the insulating layer is formed per semiconductor chip. Concretely, the insulating layer is formed at the side of each semiconductor chip. Therefore, it is required that the forming process of the insulating layer is carried out for all of the semiconductor chips to be stacked. Since the number of the forming process of the insulating layer is increased as the number of the semiconductor chips to be stacked is increased, the manufacturing process of the stacked semiconductor package becomes complicated as a whole so as to increase the manufacturing cost of the stacked semiconductor package.
- Moreover, since the insulating layer is made of a thermosetting resin, it is required that the assembly under construction including the board is thermally treated as a whole. As a result, the assembly suffers from the thermal treatment several times so that the board and/or one or more of the semiconductor chips may be warped and the characteristics of one or more of the semiconductor chips may be changed.
- In the stacking of the semiconductor chips, the adjacent ones of the semiconductor chips are bonded with one another with adhesive. In this case, however, the adhesive may be peeled off by the several thermal treatments so that the adjacent ones of the semiconductor chips are imperfectly bonded with one another.
-
FIGS. 1 to 9 relate to the manufacturing process of a stacked semiconductor device according to a first embodiment. In the drawings, attention is paid to a portion of a wafer so as to clarify the distinctive features of the first embodiment. The portion of the wafer to which attention is paid is enlargedly depicted. - As shown in
FIG. 1 ,electrodes 11 are formed of electric conductor such as aluminum on awafer 10 made of, e.g., silicon, andfirst trenches 10A are formed at the area except theelectrodes 11 of thewafer 10 by means of so-called dicing before grinding (DBG) so as not to penetrate thewafer 10. - As shown in
FIG. 2 , insulatingresins 12 are formed by ink-jet or printing so as to embed thefirst trenches 10A. In the use of the ink-jet method, the diameter of the forefront of the nozzle is set to a predetermined size so that theinsulating resin 12 is discharged for thefirst trenches 10A. In the use of the printing method, a mask with a pattern in accordance with the shapes and sizes of thefirst trenches 10A and the desired pattern to be formed is prepared, and theinsulating resins 12 are printed and formed via the mask so as to embed thefirst trenches 10A. A part of theinsulating resin 12 is provided on a top surface of the wafer with the elements being exposed. - As the
insulating resin 12 may be exemplified thermoplastic resin and UV cured resin. - As shown in
FIG. 3 , dicing process is carried out for the insulatingresins 12 formed in thefirst trenches 10A to formsecond trenches 12A reaching to thewafer 10 throughout theinsulating resins 12, respectively. Herein, since the remaininginsulating resins 12 after thesecond trenches 12A are formed constitutes the insulating layers at the sides of each semiconductor chip, thesecond trenches 12A are formed so that the insulating layer can be formed as designed. - In
FIG. 3 , thesecond trenches 12A are formed in V-shape. In this case, thesides 12B of the remaininginsulating resins 12 are tapered by the formation of thesecond trenches 12A so that the rising angles of thesides 12B becomes relatively small. As described above, the remaininginsulating resins 12 constitute the insulating layers at the sides of the semiconductor chips and thelower portions 12C of theinsulating resins 12 constitute the lower edge portions of the insulating layers of the semiconductor chip (refer to,FIGS. 8 and 9 ). - That the rising angles of the
insulating resins 12 are small means that the contacting angle θ of the insulating layer of the upper semiconductor chip for the lower semiconductor chip is small (refer to,FIGS. 10 and 11 ). As a result, the insulating layer of the upper semiconductor chip is smoothly contacted with the lower semiconductor chip. - Therefore, even though the wiring layers are formed over the insulating layers of the sides of the semiconductor chips, the wiring layers can not be disconnected between the upper semiconductor chip and the lower semiconductor chip.
- In this embodiment, since the sides of the semiconductor chip are covered with the insulating layers, respectively, even though the semiconductor chips are electrically connected with one another by means of wire bonding, the wires can not be directly contacted with the semiconductor chips (particularly, the edges of the semiconductor chips) by the formation of the wiring layers. As a result, the manageability of the wires can be simplified.
- The
second trenches 12A may be formed in another shape except the V-shape shown inFIG. 3 as occasion demands. For example, as shown inFIG. 4 , thesecond trenches 12A may be formed so that theinsulating resins 12 remain only at respective either sides of thefirst trenches 10A. When thesecond trenches 12A are formed in V-shape as shown inFIG. 3 , theinsulating resins 12 remain at both sides of thefirst trenches 10A, respectively, so that both sides of the resultant semiconductor chip are covered with the corresponding insulating layers. In contrast, when thesecond trenches 12A are formed so that theinsulating resins 12 are formed at respective either sides of thefirst trenches 10A as shown inFIG. 4 , either side of the resultant semiconductor chip is covered with the corresponding insulating layer. - In the former case, electric connection can be realized at both sides of the stacked semiconductor chips. In the latter case, electric connection can be realized at either side of the stacked semiconductor chips. Therefore, the
second trenches 12 of V-shape as shown inFIG. 3 are effective in the case where a plurality of semiconductor chips with respective different semiconductor chips are stacked subsequently and thesecond trenches 12 of V-shape as shown inFIG. 4 are effective in the case where a plurality of semiconductor chips are stacked slidably. The concrete embodiment will be described below. - It is not always required that the
second trenches 12A are formed so as to penetrate through the insulatingresins 12, but it is required that the depths of thesecond trenches 12 are set to predetermined depths enough to cut off and divide thewafer 10 into the semiconductor chips. - As shown in
FIG. 5 , aprotective tape 15 is attached to the surface of thewafer 10 and the rear surface of thewafer 10 is grinded so as to thin thewafer 10 in a manner that thesecond trenches 12A are opened as shown inFIG. 6 . In this way, thewafer 10 is divided into the semiconductor chips. - As shown in
FIG. 7 , for example, anadhesive film 16 is attached to the rear surface of the wafer 10 (divided semiconductor chips), and by cutting theadhesive film 16, the semiconductor chip(s) as shown inFIG. 8 can be obtained. Herein, when thesecond trenches 12A are formed as shown inFIG. 4 , the resultant semiconductor chip can be formed as shown inFIG. 9 . -
FIG. 10 is a cross sectional view showing a stacked semiconductor package formed by stacking the semiconductor chips as shown inFIG. 8 .FIG. 11 is a cross sectional view showing a stacked semiconductor package formed by stacking the semiconductor chips as shown inFIG. 9 . - In the stacked
semiconductor package 20 shown inFIG. 10 , afirst semiconductor chip 22 is stacked on aboard 21 via anadhesive layer 27, and asecond semiconductor chip 23 is stacked on the center area of the main surface of thefirst semiconductor chip 22 via anadhesive layer 28. Then, the insulatinglayers 24 made of the remaining insulatingresins 12 are formed at both sides of thefirst semiconductor chip 22, and the insulatinglayers 25 made of the remaining insulatingresins 12 are formed at both sides of thesecond semiconductor chip 23. Apart of the insulatinglayers first semiconductor chips layer 24 is elongated from a top surface of thefirst chip 22 to a top surface of theboard 21 via a side of thefirst chip 22 and theadhesive layer 27. The insulatinglayer 25 is elongated from a top surface of thesecond chip 23 to a top surface of thefirst chip 22 via a side of thesecond chip 23 and theadhesive layer 27. - Moreover, wiring layers 26 are formed so as to cover the insulating
layers electrodes 21A formed on theboard 21 are electrically connected withelectrodes - On the other hand, in the stacked
semiconductor package 20 shown inFIG. 11 , thefirst semiconductor chip 22 is stacked on theboard 21 via theadhesive layer 27 and thesecond semiconductor chip 23 is stacked and shifted on the main surface of thefirst semiconductor chip 22 so as to expose the end portion of thefirst semiconductor chip 22. Moreover, the insulatinglayer 24 made of the remaining insulatingresin 12 is formed at either side of thefirst semiconductor chip 22, and the insulatinglayer 25 made of the remaining insulatingresin 12 is formed at either side of thesecond semiconductor chip 23 in the same side as the insulatinglayer 24. - Then, wiring layers 26 are formed so as to cover the insulating
layers electrodes 21A on theboard 21 are electrically connected with theelectrodes - In the stacked
semiconductor package 20 shown in FIG. 10 or 11, the insulatinglayers layers - Moreover, since no thermal treatment is required when the insulating
layers board 21 and the semiconductor chips 22, 23 and the characteristic changes of the semiconductor chips 22, 23 due to the thermal treatment can be prevented. Then, the peeling-off of theadhesive layers 27 and/or 28 due to the thermal treatment can be prevented so that thesemiconductor chip 22 can be sufficiently bonded with thesemiconductor chip 23 and thesemiconductor chip 22 can be sufficiently bonded with theboard 21. - In this embodiment, since the electric conduction between the
board 21 and the semiconductor chips 22, 23 can be realized by the wiring layers 26 under the condition that the insulatinglayers semiconductor package 20 can be thinned as a whole. - Instead of the wiring layers 26 shown in
FIGS. 10 and 11 , bonding wires, which forms an arc, may be employed to electrically connect between theboard 21 and the semiconductor chips 22, 23. -
FIGS. 12 to 15 relate to the manufacturing process of a stacked semiconductor device according to a second embodiment. In the drawings, attention is paid to a portion of a wafer so as to clarify the distinctive features of the first embodiment. The portion of the wafer to which attention is paid is enlargedly depicted. - As shown in
FIG. 12 ,electrodes 31 are formed of electric conductor such as copper on awafer 30 made of, e.g., silicon, andfirst trenches 30A are formed at the area except theelectrodes 31 of thewafer 30 by RIE (reactive ion etching) or laser processing so as not to penetrate thewafer 30. - As shown in
FIG. 13 , a photosensitive member is applied onto the surface of thewafer 30 to form aphotosensitive layer 32 so as to embed thefirst trenches 30A. The photosensitive member can be made of well known material such as photosensitive resin typified by polyimide or resist. - As shown in
FIG. 14 , a mask with a pattern in accordance with the shapes and sizes of thefirst trenches 30A and the desired pattern to be formed is prepared so that thephotosensitive layer 32 is exposed and developed to formsecond trenches 32A at thephotosensitive layer 32. - In
FIG. 14 , thesecond trenches 32A are formed so that thephotosensitive layer 32 remains at both sides of thefirst trenches 30A, respectively. However, thesecond trenches 32A may be formed at respective either sides of thefirst trenches 30A, as shown inFIG. 15 . - In the case that the
second trenches 32A are formed as shown inFIG. 14 , since thephotosensitive layer 32 remains at both sides of thefirst trenches 30A,respectively, insulating layers are formed at both sides of each of the resultant semiconductor chips to be stacked. In the case that thesecond trenches 32A are formed as shown inFIG. 15 , since thephotosensitive layer 32 remains at respective either sides of thefirst trenches 30A, insulating layers are formed at respective either sides of the resultant semiconductor chips to be stacked. - In the former case, electric connection can be realized at both sides of the stacked semiconductor chips. In the latter case, electric connection can be realized at either side of the stacked semiconductor chips. Therefore, the
second trenches 12 as shown inFIG. 14 are effective in the case where a plurality of semiconductor chips with respective different semiconductor chips are stacked subsequently and thesecond trenches 12 as shown inFIG. 15 are effective in the case where a plurality of semiconductor chips are stacked slidably. - In
FIG. 12 , thefirst trenches 30A are shaped in inverted trapezoid. In this case, the rising angles of the remainingphotosensitive layer 32 along the side walls of thefirst trenches 30A become relatively small, respectively, originated from the (inverted trapezoid) shapes of thefirst trenches 30A. As described above, the remainingphotosensitive layer 32 constitutes the insulating layer(s) of the semiconductor chip as it is, and thelower portions 30C of thephotosensitive layer 32 constitute the lower edge portion(s) of the insulating layer(s) of the semiconductor chip (FIGS. 8 and 9 ). - That the rising angles of the remaining
photosensitive layer 32 along the side walls of thefirst trenches 30A are small means that the contacting angle θ of the insulating layer of the upper semiconductor chip for the lower semiconductor chip is small (FIGS. 10 and 11 ). As a result, the insulating layer of the upper semiconductor chip is smoothly contacted with the lower semiconductor chip. - Therefore, even though the wiring layers are formed over the insulating layers of the sides of the semiconductor chips, the wiring layers can not be disconnected between the upper semiconductor chip and the lower semiconductor chip.
- In this embodiment, since the sides of the semiconductor chip are covered with the insulating layers, respectively, even though the semiconductor chips are electrically connected with one another by means of wire bonding, the wires can not be directly contacted with the semiconductor chips (particularly, the edges of the semiconductor chips) by the formation of the wiring layers. As a result, the manageability of the wires can be simplified.
- The
first trenches 30A may have another shape except the inverted trapezoid shape shown inFIG. 12 as occasion demands. - Then, a protective tape is attached to the surface of the
wafer 30 and the rear surface of thewafer 30 is grinded so as to thin thewafer 30 in a manner that thesecond trenches 32A are opened in the same manner asFIGS. 5 to 9 . In this way, thewafer 30 is divided into the semiconductor chips. An adhesive film is attached to the rear surface of the wafer 30 (divided semiconductor chips), and by cutting the adhesive film, the semiconductor chip(s) can be obtained. - As described above, the stacked semiconductor package as shown in
FIG. 10 can be formed through the step shown inFIG. 14 , and the stacked semiconductor package as shown inFIG. 11 can be formed through the step shown inFIG. 15 . As a result, the stacked semiconductor package according to the second embodiment can exhibit the same function/effects as the stacked semiconductor package according to the first embodiment. - Although the present invention was described in detail with reference to the above examples, this invention is not limited to the above disclosure and every kind of variation and modification may be made without departing from the scope of the invention.
- For example, in the embodiments, the
second trenches first trenches second trenches resins 12 andphotosensitive layer 32 formed in thefirst trenches first trenches resins 12 and thephotosensitive layer 32, respectively.
Claims (5)
1. A stacked semiconductor package, comprising:
a substrate;
a plurality of semiconductor chips subsequently formed on the substrate and having respective insulating layers at sides thereof such that the insulating layers of the plurality of semiconductor chips are positioned at the same side as one another; and
a wiring formed over the insulating layers at the sides of the plurality of semiconductor chips so that the plurality of semiconductor chips are electrically connected with one another and one or more of the plurality of semiconductor chips is electrically connected with the substrate.
2. The stacked semiconductor package as set forth in claim 1 , wherein the insulating layers are formed at both sides of the corresponding semiconductor chips and the wiring conducts the electric connection for the plurality of semiconductor chips and the substrate via the insulating layers.
3. The stacked semiconductor package as set forth in claim 1 , wherein a thickness of the insulating layer at the side thereof is greater than a thickness of the insulating layer at a top thereof.
4. The stacked semiconductor package as set forth in claim 1 , wherein the insulating layer is elongated from a top of the semiconductor chip to a side thereof.
5. The stacked semiconductor package as set forth in claim 1 , wherein the semiconductor chip includes a tapered portion at the side thereof with the insulating layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US13/051,179 US20110163459A1 (en) | 2007-10-12 | 2011-03-18 | Method for manufacturing a stacked semiconductor package, and stacked semiconductor package |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
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JP2007-266307 | 2007-10-12 | ||
JP2007266307A JP2009094432A (en) | 2007-10-12 | 2007-10-12 | Method for manufacturing stacked semiconductor package |
US12/249,025 US7932162B2 (en) | 2007-10-12 | 2008-10-10 | Method for manufacturing a stacked semiconductor package, and stacked semiconductor package |
US13/051,179 US20110163459A1 (en) | 2007-10-12 | 2011-03-18 | Method for manufacturing a stacked semiconductor package, and stacked semiconductor package |
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US12/249,025 Division US7932162B2 (en) | 2007-10-12 | 2008-10-10 | Method for manufacturing a stacked semiconductor package, and stacked semiconductor package |
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US12/249,025 Expired - Fee Related US7932162B2 (en) | 2007-10-12 | 2008-10-10 | Method for manufacturing a stacked semiconductor package, and stacked semiconductor package |
US13/051,179 Abandoned US20110163459A1 (en) | 2007-10-12 | 2011-03-18 | Method for manufacturing a stacked semiconductor package, and stacked semiconductor package |
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US (2) | US7932162B2 (en) |
JP (1) | JP2009094432A (en) |
KR (1) | KR101018556B1 (en) |
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JP5126002B2 (en) * | 2008-11-11 | 2013-01-23 | セイコーエプソン株式会社 | Semiconductor device and manufacturing method of semiconductor device |
JP2010283204A (en) * | 2009-06-05 | 2010-12-16 | Toshiba Corp | Method of manufacturing semiconductor device |
JP2012023259A (en) * | 2010-07-16 | 2012-02-02 | Casio Comput Co Ltd | Semiconductor device and method for manufacturing the same |
JP5289484B2 (en) * | 2011-03-04 | 2013-09-11 | 株式会社東芝 | Manufacturing method of stacked semiconductor device |
KR20140011687A (en) * | 2012-07-18 | 2014-01-29 | 삼성전자주식회사 | Semiconductor package and method for fabricating the same |
CN106717135B (en) * | 2014-09-24 | 2019-09-27 | 皇家飞利浦有限公司 | Printed circuit board and printed circuit board arrangement |
KR102420125B1 (en) | 2015-12-10 | 2022-07-13 | 삼성전자주식회사 | Semiconductor package and method of fabricating the same |
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Also Published As
Publication number | Publication date |
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JP2009094432A (en) | 2009-04-30 |
KR101018556B1 (en) | 2011-03-03 |
US7932162B2 (en) | 2011-04-26 |
US20090096110A1 (en) | 2009-04-16 |
KR20090037831A (en) | 2009-04-16 |
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