US20100133647A1 - Semiconductor devices and semiconductor device manufacturing methods - Google Patents

Semiconductor devices and semiconductor device manufacturing methods Download PDF

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Publication number
US20100133647A1
US20100133647A1 US12/591,718 US59171809A US2010133647A1 US 20100133647 A1 US20100133647 A1 US 20100133647A1 US 59171809 A US59171809 A US 59171809A US 2010133647 A1 US2010133647 A1 US 2010133647A1
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well
region
conductive type
forming
substrate
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Won-joo Kim
Sang-Moo Choi
Tae-Hee Lee
Yoon-dong Park
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHOI, SANG-MOO, KIM, WON-JOO, LEE, TAE-HEE, PARK, YOON-DONG
Publication of US20100133647A1 publication Critical patent/US20100133647A1/en
Priority to US13/412,248 priority Critical patent/US8541841B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells

Definitions

  • the inventive concepts relate to semiconductor devices and semiconductor device manufacturing methods, and more particularly, to semiconductor device manufacturing methods capable of forming memory cells having a localized silicon on insulator (SOI) structure, the SOI structure localized to one or more regions by using selective etching methods.
  • SOI silicon on insulator
  • a one-transistor (1-T) dynamic random access memory is a memory implemented by using a single transistor without including a capacitor.
  • the 1-T DRAM can be manufactured by performing a simple process and has an improved sensing margin.
  • the 1-T DRAM should be implemented on an SOI wafer and manufacturing costs increase due to the increased cost of an SOI wafer. Also, since SOI wafer properties are not yet completely verified, the 1-T DRAM cannot be manufactured as a stand-alone type and should be manufactured as an embedded type.
  • the inventive concepts provide semiconductor device manufacturing methods capable of forming a memory cell having a silicon on insulator (SOI) structure in one or more localized regions of a bulk substrate by using selective etching.
  • SOI silicon on insulator
  • methods of manufacturing semiconductor devices including forming one or more floating body patterns in a region of a bulk substrate, dividing the region of the bulk substrate into a lower bulk substrate region and a floating body region by etching lower regions of the one or more floating body patterns and filling a region between the floating body region and the lower bulk substrate region with an insulating material.
  • the methods including forming a well in a bulk substrate of a first conductive type and forming a silicon on insulator (SOI) structure in the well.
  • the forming of the SOI structure may include forming one or more floating body patterns in the well, dividing the well into a lower well, region and a floating body region by etching lower regions of the one or more floating body patterns and filling a region between the floating body region and the lower well region with an insulating material.
  • a plurality of wells may be formed including a second well of a second conductive type in the bulk substrate of the first conductive type and forming a third well of the first conductive type in the second well of the second conductive type.
  • the forming of the well may include forming the well of the first conductive type in the second well.
  • the forming of the SOI structure may include forming the SOI structure in the well of the first conductive type.
  • a semiconductor device including forming a plurality of wells in a first region of a bulk substrate of a first conductive type and forming a silicon on insulator (SOI) structure including a portion of the bulk substrate, in which the plurality of wells are not formed.
  • the forming of the SOI structure may include forming one or more floating body patterns in the portion of the bulk substrate, in which the plurality of wells are not formed; dividing the portion of the bulk substrate, in which the plurality of wells are not formed, into a substrate region and a floating body region by etching lower portions of the one or more floating body patterns; and filling a portion between the floating body region and the substrate region with an insulating material.
  • semiconductor devices including a substrate region of a first conductive type bulk substrate, an insulating region in the substrate region and a floating body region on the insulating region and separated from the substrate region by the insulating region, the floating body region and the substrate region including materials having similar characteristics.
  • semiconductor devices including a localized silicon on insulator (SOI) structure including a substrate region of a first conductive type bulk substrate, a well in the substrate region, an insulating region in the well, and a floating body region on the insulating region and separated from the well by the insulating region, the floating body region and the well including materials having similar characteristics.
  • SOI silicon on insulator
  • semiconductor devices including a localized silicon on insulator (SOI) structure including a first substrate region of a first conductive type bulk substrate, a plurality of wells in the first substrate region, an insulating region in a second substrate region of the bulk substrate and a floating body region on the insulating region and separated from the second substrate region by the insulating region, the second substrate region and the floating body region including materials having similar characteristics.
  • SOI silicon on insulator
  • FIGS. 1-11 represent non-limiting, example embodiments as described herein.
  • FIG. 1 is a cross-sectional diagram of a semiconductor device according to example embodiments of the inventive concepts
  • FIGS. 2A-2C are cross-sectional diagrams illustrating a method of manufacturing the semiconductor device shown in FIG. 1 according to example embodiments of the inventive concepts;
  • FIGS. 3A-3G are perspective diagrams illustrating a method of forming a silicon on insulator (SOI) structure according to example embodiments of the inventive concepts
  • FIG. 4 is a cross-sectional diagram of a semiconductor device according to example embodiments of the inventive concepts.
  • FIG. 5 is a cross-sectional diagram of a semiconductor device according to example embodiments of the inventive concepts.
  • FIG. 6 is a cross-sectional diagram of a semiconductor device according to example embodiments of the inventive concepts.
  • FIG. 7 is a cross-sectional diagram of a semiconductor device according to example embodiments of the inventive concepts.
  • FIGS. 8A-8G are perspective diagrams illustrating a method of forming an SOI structure according to example embodiments of the inventive concepts
  • FIGS. 9A-9F are perspective diagrams illustrating a method of forming an SOI structure according to example embodiments of the inventive concepts.
  • FIG. 10 is a cross-sectional diagram of a semiconductor device according to a comparative example of the inventive concepts.
  • FIG. 11 is a cross-sectional view of a semiconductor device according to a comparative example of the inventive concepts.
  • Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown.
  • Example embodiments may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those of ordinary skill in the art.
  • the thicknesses of layers and regions are exaggerated for clarity.
  • Like reference numerals in the drawings denote like elements, and thus their description will be omitted.
  • first”, “second”, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of example embodiments of the inventive concepts.
  • spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
  • Example embodiments of the inventive concepts are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of example embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region illustrated as a rectangle may have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region.
  • a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.
  • the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments of the inventive concepts.
  • FIG. 1 is a cross-sectional diagram of a semiconductor device according to example embodiments of the inventive concepts.
  • the semiconductor device may include a substrate region 110 , first through third wells 120 , 130 , and 140 , and a silicon on insulator (SOI) structure 150 .
  • the SOI structure may be in the third well 140 .
  • the SOI structure 150 may include an insulating region 170 and body regions 181 , 182 , and 183 .
  • the insulating region 170 and the body regions 181 , 182 , and 183 may be formed by, for example, selectively etching an upper region of the third well 140 .
  • the third well 140 and the body regions 181 , 182 , and 183 may be of materials having similar characteristics.
  • the SOI structure 150 in the third well 140 may be separated from components in the first and second wells 120 and 130 , different bias voltages may be applied to the SOI structure and the components in the first and second wells 120 and 130 .
  • Memory cells e.g., one-transistor (1-T) dynamic random access memory (DRAM) cells
  • driving circuits for driving the memory cells may be on the first and second wells 120 and 130 .
  • the memory cells on the third well 140 may be electrically separated from the driving circuits on the first and second wells 120 and 130 .
  • Different bias voltages may be applied to the memory cells and the driving circuits. Table 1 shows examples of applicable bias voltages. If the bias voltages shown in Table 1 are applied, a PNP latch phenomenon may be prevented and/or reduced.
  • a p-channel metal-oxide semiconductor (PMOS) transistor 161 may be on the first well 120 and an n-channel metal-oxide semiconductor (NMOS) transistor 162 may on the second well 130 .
  • 1T-DRAM cells 191 - 197 may be on the third well 140 .
  • the PMOS transistor 161 and the NMOS transistor 162 may be peripheral circuits for driving the 1T-DRAM cells 191 - 197 .
  • the 1T-DRAM cells 191 - 197 and the peripheral circuits may be driven by applying different bias voltages to the first through third wells 120 , 130 , and 140 . For example, as shown in Table 1, a negative back bias voltage may be applied to the substrate region 110 .
  • the substrate region 110 and the second and third wells 130 and 140 are shown as p-type, and the first well 120 is shown as n-type in FIG. 1 , example embodiments of the inventive concepts are not limited thereto.
  • FIGS. 2A-2C are cross-sectional diagrams for describing a method of manufacturing the semiconductor device illustrated in FIG. 1 according to example embodiments of the inventive concepts.
  • the n-type first well 120 may be formed in the p-type substrate region 110 .
  • the p-type second and third wells 130 and 140 may be formed in the first well 120 .
  • the second and third wells 130 and 140 may be formed in two side regions of the first well 120 so as not to be adjacent to each other.
  • an SOI structure may be formed in the third well 140 .
  • the insulating region 170 and the body regions 181 - 183 may be formed by using a selective etching method (e.g., a selective etching method according to example embodiments described with respect to FIG. 3 ).
  • a selective etching method e.g., a selective etching method according to example embodiments described with respect to FIG. 3 .
  • a PMOS transistor may be formed on the first well 120 and an NMOS transistor may be formed on the second well 130 .
  • 1T-DRAM cells 191 - 197 may be formed on the third well 140 .
  • FIGS. 3A-3G are perspective diagrams for describing a method of forming an SOI structure according to example embodiments of the inventive concepts.
  • two side regions of a semiconductor substrate may be patterned from a top surface of the semiconductor substrate.
  • the semiconductor substrate may be a bulk substrate formed from a bulk wafer.
  • a body line pattern 350 may be formed between the patterned regions and a substrate region 310 may be under the body line pattern 350 .
  • insulating films 330 may be formed by filling the patterned regions with an insulating material. As a result, the insulating films 330 may be on both side surfaces of the body line pattern 350 .
  • the body line pattern 350 and the insulating films 330 may be patterned in a Z direction to form a plurality of body patterns 350 ′ and a plurality of insulating patterns 330 ′.
  • the patterning may be performed from top surfaces of the body line pattern 350 and the insulating films 330 .
  • the body line pattern 350 illustrated in FIGS. 3A and 3B may be different from the body patterns 350 ′ illustrated in FIG. 3C .
  • the bulk substrate may be patterned in a major axis direction (e.g., Y direction) so as to form the body line pattern 350 that extends in the Y direction.
  • a major axis direction e.g., Y direction
  • the two side regions of the body line pattern 350 may be filled with the insulating films 330 .
  • the body line pattern 350 and the insulating films 330 may be patterned in a major axis direction (e.g., Z direction) that is perpendicular to the Y direction in which the body line pattern 350 extends, so as to form the body patterns 350 ′ that extend in the Z direction.
  • a height of the body patterns 350 ′ illustrated in FIG. 3C may be less than the height of the body line pattern 350 illustrated in FIGS. 3A and 3B .
  • top surface regions 380 of the body line pattern 350 and the insulating films 330 which are not desired to be patterned, may be masked and regions which are not masked may be patterned.
  • side surfaces 384 of the patterned regions may be masked and the bottom surfaces 386 may be exposed.
  • the side surfaces 384 may be masked with the bottom surfaces 386 and then the bottom surfaces 386 unmasked.
  • example embodiments of the inventive concepts are not limited thereto.
  • lower regions of the body patterns 350 ′ may be selectively etched through the bottom surfaces 386 which are exposed.
  • a bulk region under the body patterns 350 ′ may be etched through the bottom surfaces 386 by using, for example, a selective wet etching method or a selective dry etching method so as to expose a bottom surface 388 of the bulk region under the body patterns 350 ′.
  • the top surface regions 380 and the side surfaces 384 of the body patterns 350 ′ and the insulating patterns 330 ′ may be removed.
  • the body patterns 350 ′ may be completely separated from the substrate region 310 so as to form body regions 350 ′′.
  • the bulk substrate may be divided into the substrate region 310 and the body regions 350 ′′.
  • etched regions illustrated in FIG. 3F may be filled with the insulating material.
  • the etched bulk region under the body regions 350 ′′ and regions between the body regions 350 ′′ may be filled with an insulating material so as to form an insulating region 330 ′′.
  • the insulating region 330 ′′ may provide support for the body regions 350 ′′.
  • the substrate region 310 , the insulating region 330 ′′, and the body regions 350 ′′ may respectively correspond to the third well 140 , the insulating region 170 , and the body regions 181 , 182 , and 183 illustrated in FIG. 1 .
  • the method illustrated in FIGS. 3A-3G may be used to form a plurality of body regions on a semiconductor substrate. For example, the method may be used to form the body regions 181 , 182 , and 183 of the semiconductor device illustrated in FIG. 1 .
  • regions of a bulk substrate may be etched in parallel in the first direction similarly to FIG. 3A , so as to form a plurality of body line patterns 350 which extend in the Y direction. Regions between the plurality of body line patterns 350 may be filled with the insulating films 330 similarly to FIG. 3B .
  • the bulk substrate may be etched in the Z direction that is perpendicular to the Y direction in which the plurality of body line patterns 350 extend, so as to form body patterns 350 ′ that extend in parallel in the Z direction similarly to FIG. 3C . Side surfaces of the body patterns 350 ′ may be masked similarly to FIG. 3D .
  • a bulk region under the body patterns 350 ′ may be etched through a bottom surface between the body patterns 350 ′ which are not masked similarly to FIG. 3F .
  • the etched bulk region under the body patterns 350 ′ and regions between the body patterns 350 ′ may be filled with an insulating material similarly to FIG. 3G .
  • FIG. 4 is a cross-sectional diagram of a semiconductor device according to example embodiments of the inventive concepts.
  • the semiconductor device may include a substrate region 410 , first and second wells 420 and 430 , and an SOI structure 440 .
  • the SOI structure 440 may be in the substrate region 410 .
  • FIG. 4 may be different from FIG. 1 in that the SOI structure 440 may be in the substrate region 410 in FIG. 4 , while the SOI structure 150 may be in the third well 140 in FIG. 1 .
  • the SOI structure 440 may include an insulating region 470 and body regions 481 and 482 .
  • the insulating region 470 and the body regions 481 and 482 may be formed by selectively etching an upper region of the substrate region 410 .
  • the substrate region 410 and the body regions 481 and 482 may be of materials having similar characteristics.
  • a PMOS transistor 461 may be on the first well 420 and an NMOS transistor 462 may be on the second well 430 .
  • 1T-DRAM cells 491 - 493 and 494 - 495 may be on the substrate region 410 .
  • the PMOS transistor 461 and the NMOS transistor 462 may be peripheral circuits for driving the 1T-DRAM cells 491 - 493 and 494 - 495 .
  • the 1T-DRAM cells 491 - 495 , and the peripheral circuits (the PMOS transistor 461 and the NMOS transistor 462 ) may be driven by applying different bias voltages to the substrate region 410 , the first well 420 and the second well 430 .
  • FIG. 5 is a cross-sectional diagram of a semiconductor device according to example embodiments of the inventive concepts.
  • the semiconductor device may include a substrate region 510 , first and second wells 520 and 530 , and an SOI structure 540 .
  • the SOI structure 540 may be in the second well 530 .
  • FIG. 5 may be different from FIG. 4 in that the SOI structure 540 may be in the second well 530 in FIG. 5 while the SOI structure 440 may be in the substrate region 410 in FIG. 4 .
  • the SOI structure 540 may include an insulating region 570 and body regions 581 and 582 .
  • FIG. 7 is a cross-sectional diagram of a semiconductor device according to example embodiments of the inventive concepts.
  • the semiconductor device may include a substrate region 710 , first through third wells 720 , 730 , and 740 , and an SOI structure 750 .
  • the SOI structure 750 may be in the substrate region 710 .
  • the SOI structure 750 may include an insulating region 770 and body regions 781 and 782 .
  • the insulating region 770 and the body regions 781 and 782 may be formed by selectively etching an upper region of the substrate region 710 .
  • the first well 720 may separate the substrate region 710 from the second and third wells 730 and 740 .
  • NMOS transistors 762 and 763 may be on the second well 730 and a PMOS transistor 761 may be on the third well 740 .
  • 1T-DRAM cells 791 - 795 may be on the substrate region 710 .
  • Different bias voltages may be applied to the substrate region 710 and the first through third wells 720 , 730 , and 740 through voltage reception units 751 - 754 .
  • Table 3 may show examples of applicable bias voltages. For example, a positive back bias voltage may be applied to the substrate region 710 . If the bias voltages shown in Table 3 are applied, a PNP latch phenomenon and an NPN latch phenomenon may be prevented and/or reduced.
  • FIGS. 8A-8G are perspective diagrams for describing a method of forming an SOI structure according to example embodiments of the inventive concepts.
  • a bulk substrate may be etched in a major axis direction (e.g., in a Y direction) so as to form a body line pattern 850 that extends in the Y direction.
  • a body line pattern 850 may be filled with insulating films 830 .
  • Processes in FIGS. 8A and 8B are identical to the processes in FIGS. 3A and 3B and detailed descriptions thereof will be omitted. Referring to FIG.
  • the body line pattern 850 is patterned in a Z direction that is perpendicular to the Y direction in which the body line pattern 850 extends, so as to form a plurality of body patterns 850 ′ that extend in the second direction.
  • the insulating films 830 may not be patterned.
  • the patterning may be performed from a top surface of the body line pattern 350 .
  • top surface regions 880 of the body patterns 850 and the insulating films 830 which are not desired to be patterned, may be masked and regions which are not masked may be patterned.
  • side surfaces 884 and bottom surfaces (not shown) of the patterned regions may be masked and then the bottom surfaces may be exposed.
  • lower regions of the body patterns 850 ′ may be selectively etched through the bottom surfaces which are exposed, so as to expose a bottom surface 888 of a bulk region under the body patterns 850 ′.
  • the top surface regions 880 and the side surfaces 884 of the body patterns 850 ′ and the insulating films 830 may be exposed.
  • etched regions illustrated in FIG. 8F may be filled with the insulating material.
  • the SOI structure illustrated in FIG. 8G may be identical to the SOI structure illustrated in FIG. 3G .
  • FIGS. 9A-9F are perspective diagrams for describing a method of forming an SOI structure according to example embodiments of the inventive concepts.
  • insulating films 930 may be formed in a bulk substrate.
  • the insulating films 930 may be inserted onto a substrate region 910 that is a bottom region of the bulk substrate.
  • the bulk substrate may be etched in a minor axis direction (e.g., Z direction) so as to form a plurality of body line patterns 950 that extend in the minor axis direction. Regions between the body line patterns 950 may be filled with the insulating films 930 .
  • regions of the bulk substrate on sides of the insulating films 930 are referred to as the body line patterns 950 and the remaining region of the bulk substrate is referred to as the substrate region 910 .
  • FIG. 10 is a cross-sectional diagram of a semiconductor device according to a comparative example embodiment of the inventive concepts.
  • an insulating region 1070 and a silicon region 1090 may be on a bulk substrate and wells 1020 , 1030 , and 1040 may be formed by using well implants.
  • FIGS. 10 , 11020 , 11030 , and 11040 represent example paths of the well implants. Because the wells 1020 , 1030 , and 1040 may be formed by using the well implants in FIG. 10 , if the insulating region 1070 and the silicon region 1090 are thick, the wells 1020 , 1030 , and 1040 may not be appropriately formed. The insulating region 1070 and the silicon region 1090 may be damaged.
  • an SOI structure may be formed by selectively etching an upper region of a well (or a substrate region, not shown), the well (or the substrate region) and a body region of the SOI structure may be formed of materials having similar characteristics.
  • the silicon region 1090 is epitaxially grown on the substrate region that is formed under the well, the silicon region 1090 and the substrate region may not be formed of materials having similar characteristics.
  • FIG. 11 is a cross-sectional diagram of a semiconductor device according to a comparative example embodiment of the inventive concepts.
  • wells 1120 , 1130 , and 1140 may be formed in a bulk substrate and then an insulating region 1171 may be formed on the wells 1120 , 1130 , and 1140 .
  • An insulating region 1172 and a silicon region 1190 may be bonded to the insulating region 1171 by using a wafer bonding method.

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  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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US8835278B2 (en) 2010-11-18 2014-09-16 Imec Method for forming a buried dielectric layer underneath a semiconductor fin
US20150122973A1 (en) * 2013-11-06 2015-05-07 Samsung Electronics Co., Ltd. Sensing pixel and image sensor including the same
US9110233B2 (en) 2012-01-02 2015-08-18 Samsung Electronics Co., Ltd. Semiconductor devices
US20170047796A1 (en) * 2014-04-17 2017-02-16 Valeo Equipements Electriques Moteur Electrical machine stator with optimised notch filling, and corresponding method for production of the said stator

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US8835278B2 (en) 2010-11-18 2014-09-16 Imec Method for forming a buried dielectric layer underneath a semiconductor fin
US9110233B2 (en) 2012-01-02 2015-08-18 Samsung Electronics Co., Ltd. Semiconductor devices
US9316789B2 (en) 2012-01-02 2016-04-19 Samsung Electronics Co., Ltd. Semiconductor devices and methods of manufacturing the same
US20150122973A1 (en) * 2013-11-06 2015-05-07 Samsung Electronics Co., Ltd. Sensing pixel and image sensor including the same
US9711675B2 (en) * 2013-11-06 2017-07-18 Samsung Electronics Co., Ltd. Sensing pixel and image sensor including the same
US20170047796A1 (en) * 2014-04-17 2017-02-16 Valeo Equipements Electriques Moteur Electrical machine stator with optimised notch filling, and corresponding method for production of the said stator

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US8541841B2 (en) 2013-09-24
CN103531537A (zh) 2014-01-22
CN101752304A (zh) 2010-06-23
JP2010130027A (ja) 2010-06-10
JP5520583B2 (ja) 2014-06-11
US20120161277A1 (en) 2012-06-28

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