US20100052183A1 - Microfeature workpiece substrates having through-substrate vias, and associated methods of formation - Google Patents

Microfeature workpiece substrates having through-substrate vias, and associated methods of formation Download PDF

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US20100052183A1
US20100052183A1 US12615518 US61551809A US2010052183A1 US 20100052183 A1 US20100052183 A1 US 20100052183A1 US 12615518 US12615518 US 12615518 US 61551809 A US61551809 A US 61551809A US 2010052183 A1 US2010052183 A1 US 2010052183A1
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bond
support substrate
conductive
conductive layer
sites
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US12615518
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Teck Kheng Lee
Andrew Chong Pei Lim
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Micron Technology Inc
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Micron Technology Inc
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    • HELECTRICITY
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486Via connections through the substrate with or without pins
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    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L2224/16237Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
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    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
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    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/181Encapsulation

Abstract

Microfeature workpiece substrates having through-substrate vias, and associated methods of formation are disclosed. A method in accordance with one embodiment for forming a support substrate for carrying microfeature dies includes exposing a support substrate to an electrolyte, with the support substrate having a first side with a first conductive layer, a second side opposite the first side with a second conductive layer, and a conductive path extending through the support substrate from the first conductive layer to the second conductive layer. The method can further include forming a bond pad at a bond site of the first conductive layer by disposing at least one conductive bond pad material at the bond site, wherein disposing the at least one conductive bond pad material can include passing an electrical current between the first and second conductive layers via the conductive path, while the substrate is exposed to the electrolyte.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is a divisional of U.S. application Ser. No. 11/218,352, filed Sep. 1, 2005, now U.S. Pat. No. 7,622,377, which is incorporated herein by reference in its entirety.
  • TECHNICAL FIELD
  • The present invention is directed generally toward microfeature workpiece substrates having through-substrate vias, and associated methods of formation.
  • BACKGROUND
  • Packaged microelectronic assemblies, such as memory chips and microprocessor chips, typically include a microelectronic die mounted to a substrate (e.g., an interposer board) and encased in a plastic protective covering. The die includes functional features, such as memory cells, processor circuits, and interconnecting circuitry. The die also typically includes die bond pads that are electrically coupled to the functional features. The bond pads are coupled to corresponding first bond pads on the substrate (e.g., with wirebonds), and this connection is protected with the plastic protective covering. The first substrate bond pads can be coupled to second substrate bond pads on an opposite surface of the substrate via pathways that are internal to the substrate. The second bond pads can in turn be connected to external devices, for example, using solder balls. Accordingly, the substrate can have one or more layers of conductive material (e.g., copper) that is etched or otherwise configured to form the first substrate bond pads and the second substrate bond pads.
  • In a typical operation, the substrate bond pads are built up in an electrolytic plating operation using a bus formed from the conductive layers to transmit electrical current to the bond pads. One drawback with the bus is that it can act as an antenna and can accordingly create extraneous signals, which may interfere with the operation of the microelectronic die. Accordingly, several techniques have been developed for forming bond pads on a substrate without requiring that a bus remain in the substrate. While these techniques have met with at least some success, they have also been subject to several drawbacks. These drawbacks can include undercutting the conductive material at the bond pads and/or difficulty in obtaining very fine pitch spacing between adjacent bond pads. As the size of microelectronic dies continues to decrease, and performance demands on the microelectronic dies continues to increase, these drawbacks can in some cases place undesirable design and/or performance limitations on the microelectronic dies.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIGS. 1A-1F illustrate an initial series of steps for forming a substrate without a permanent bus, in accordance with an embodiment of the invention.
  • FIGS. 2A-2D illustrate subsequent steps for forming the substrate initially shown in FIGS. 1A-1F.
  • FIG. 3 is an enlarged illustration of a portion of a substrate configured in accordance with an embodiment of the invention, shown coupled to a microfeature workpiece and an external device.
  • FIG. 4 illustrates a packaged microelectronic device having a substrate coupled to an external device in accordance with an embodiment of the invention.
  • FIG. 5 illustrates a packaged microelectronic device having a substrate coupled to an external device in accordance with another embodiment of the invention.
  • DETAILED DESCRIPTION A. Introduction
  • Microfeature workpiece substrates having through-substrate vias, and associated methods of formation are described below. In particular aspects, the through-substrate vias can allow the formation of bond pads on one surface without requiring a bus at that surface. Instead, electrical current for forming the bond pads in an electrolytic process can be provided by a conductive path that extends through the via. A method for forming a support substrate for carrying microfeature dies in accordance with one aspect of the invention includes exposing a substrate to an electrolyte, wherein the substrate has a first side with a first conductive layer, a second side opposite the first side with a second conductive layer, and a conductive path extending through the substrate from the first conductive layer to the second conductive layer. The method can further include forming a bond pad at a bond site of the first conductive layer by disposing at least one conductive bond pad material at the bond site. The process of disposing the at least one conductive bond pad material can include passing an electrical current between the first and second conductive layers via the conductive path, while the substrate is exposed to the electrolyte.
  • In further particular aspects, the method can include patterning the first conductive layer to form a bond site, and applying bond pad material to the bond site after patterning the first conductive layer. In still another aspect, the method can include applying an at least generally non-removable protective coating over the first conductive layer, preventing the protective coating from covering the bond site (or removing the protective coating from the bond site) and applying bond pad material to the bond site after applying the protective coating.
  • In yet another aspect, the method can include forming a bond pad at a first bond site of the first conductive layer and at a second bond site of the second conductive layer. This process can further include (a) placing a removable protective coating over the second conductive layer, (b) preventing the removable protective coating from covering the second bond site or removing the protective coating from the second bond site, and (c) applying conductive material to the first and second bond sites simultaneously, after performing processes (a) and (b). The method can still further include (d) removing the removable protective coating from the second conductive layer, and (e) patterning the second conductive layer by removing a portion of the second conductive layer while leaving the second bond site electrically coupled to the first bond site via the conductive path.
  • In still further aspects, the invention can include a microelectronic system comprising a substrate configured to carry a microfeature die, with the substrate having a first surface with a first conductive layer and a second surface facing opposite from the first surface and having a second conductive layer. The first conductive layer can have multiple first bond sites, and the second conductive layer can have multiple second bond sites. The system can further comprise conductive bond pad material positioned at the first bond sites to form first bond pads, with the first bond pads being separated from each other by a first average spacing, and with the bond pad material extending around an edge of the first conductive layer at the first bond sites. Conductive bond pad material can also be positioned at the second bond sites to form second bond pads, with the first and second bond pads being electrically coupled with conductive pathways extending through the substrate. The second bond pads can be separated from each other by a second average spacing greater than the first average spacing. The bond pad material can have a different arrangement at the second bond sites than at the first bond sites. For example, the bond pad material at the second bond site can be spaced apart from an edge of the second conductive layer at the second bond sites.
  • As used herein, the terms “microfeature workpiece” and “workpiece” refer to substrates on and/or in which microelectronic devices are integrally formed. Typical microelectronic devices include microelectronic circuits or components, thin-film recording heads, data storage elements, microfluidic devices and other products. Micromachines and micromechanical devices are included within this definition because they are manufactured using much of the same technology that is used in the fabrication of integrated circuits. The microfeature workpiece can be a semiconductive piece (e.g., doped silicon wafers or gallium arsenide wafers) nonconductive pieces (e.g., various ceramic substrates) or conductive pieces. In some cases, the workpieces are generally round, and in other cases, the workpieces have other shapes, including rectilinear shapes.
  • The term “support substrate” is used generally herein to refer to a support member that carries the microfeature workpiece and provides an interface between the microfeature workpiece and external devices to which the microfeature workpiece may be electrically coupled. Accordingly, the term “support substrate” can include, but is not limited to, interposer boards, printed circuit boards, and/or other structures that can provide physical support and/or electrical connections for the microfeature workpiece and that generally do not include integrated semiconductor features.
  • B. Support Substrates and Associated Methods of Formation
  • FIGS. 1A-2D illustrate a series of process steps that may be performed to produce a support substrate having features in accordance with several embodiments of the invention. Referring first to FIG. 1A, the support substrate 110 can include a core material 113 having a first side or surface 111 a and a second side or surface 111 b facing opposite from the first surface 111 a. A first conductive layer 112 a can be positioned against the first surface 111 a, and a second conductive layer 112 b can be positioned against the second surface 111 b. The substrate 110 can include a printed circuit board, with the core 113 including a ceramic material, and the first and second conductive layers 112 a, 112 b including generally planar layers of copper. In other embodiments, these components can have different compositions and/or arrangements.
  • Referring next to FIG. 1B, a via 114 can be formed to extend through the core 113 and through the first and second conductive layers 112 a, 112 b. As shown in FIG. 1C, the via 114 can be coated with a third conductive layer 112 c to form a conductive path 115 that electrically connects the first conductive layer 112 a and the second conductive layer 112 b. The third conductive layer 112 c can be formed using a conventional combination of electroless and electrolytic plating techniques. For example, an electroless technique can be used to apply a seed layer to the walls of the via 114, and an electrolytic technique can be used to add thickness to the seed layer, forming the overall structure of the third conductive layer 112 c.
  • In FIG. 1D, the first conductive layer 112 a can be patterned to remove the bulk of the first conductive layer 112 a, with the exception of at least one first bond site 130 a located adjacent to the first surface 111 a of the core material 113. For purposes of illustration, only one first bond site 130 a is shown in FIGS. 1D-2D and described in the associated text. However, it will be understood by those of ordinary skill in the art that the support substrate 110 can include additional first bond sites 130 a at other locations, within and/or transverse to the plane of FIG. 1D. In any of these embodiments, for at least some of the first bond sites 130 a, no electrical connection exists between the first bond site 130 a and other first bond sites located at the first surface 111 a after the patterning process has been completed. In particular, each first bond site 130 a can be electrically independent of other features at the first surface 111 a. Accordingly, the first conductive layer 112 a need not include an electrically conductive bus. Instead, as will be described later, electrical current for carrying out manufacturing processes at the first bond site 130 a can be provided by the second conductive layer 112 b and the conductive path 115.
  • The first bond site 130 a can be formed using any of a variety of conventional patterning techniques. Such techniques can include disposing a layer of photoresist or another protective coating on the first conductive layer 112 a, patterning the photoresist to remove portions of the photoresist over portions of the first conductive layer 112 a that do not correspond to the first bond site 130 a, and then exposing the first conductive layer 112 a to an etchant that removes all or generally all of the first conductive layer 112 a except at the location corresponding to the first bond site 130 a.
  • Referring next to FIG. 1E, a first protective coating 140 a can be disposed over the first surface 111 a and the first conductive layer 112 a, except over the first bond site 130 a. In a particular aspect of this embodiment, the first protective coating 140 a can include a soldermask or other material that remains permanently attached to the support substrate 110 after processing. For example, the first protective coating 140 a can include a soldermask material that is patterned in a manner generally similar to that described above with reference to FIG. 1D, but which is then treated (e.g., by exposure to radiation, heat, or another energy source) to form a generally permanent coating. As used herein, the term “at least generally permanent” refers to a material that remains with the support substrate 110 after processing, and that is not removed (or at least not entirely removed) during the manufacturing process and/or prior to coupling the support substrate 110 to a microfeature die or other device for an end-user.
  • As is also shown in FIG. 1E, the first protective coating 140 a can be applied so that a gap 117 exists between a first conductive layer edge 116 a and the first protective coating 140 a. As described in greater detail below with reference to FIG. 2A, the gap 117 can allow for a more extensive application of bond pad material at the first bond site 130 a.
  • Referring next to FIG. 1F, a second protective coating 140 b can be applied to the second conductive layer 112 b. The second protective coating 140 b can be patterned in a manner generally similar to that described above to expose or keep exposed a second bond site 130 b. Unlike the first protective coating 140 a, however, the second protective coating 140 b can be completely removed during subsequent processing steps. Accordingly, the second protective coating 140 b can include a dry film or other patternable, removable material. For purposes of illustration, the second bond site 130 b is shown more or less directly beneath the first bond site 130 a; however, in many cases, the second bond site 130 b can be positioned further away from the via 114. This can result in larger spacings (e.g., coarser pitch) between adjacent second bond sites 130 b than between adjacent first bond sites 130 a.
  • FIGS. 2A-2D illustrate process steps for providing additional conductive material at the first bond site 130 a and the second bond site 130 b (referred to collectively as bond sites 130). The additional conductive material applied to the bond sites 130 can provide for enhanced electrical connectivity between the bond sites 130 and the structures to which the bond sites are electrically coupled. In the case of the first bond site 130 a, the coupling can be to a microelectronic die that the support substrate 110 carries and is packaged with. In the case of the second bond site 130 b, the connection can be to an external device.
  • Beginning with FIG. 2A, the support substrate 110 can be disposed in an electrolyte 118, and a cathode 119 can be applied to the second conductive layer 112 b. One or more anodes 120 can be positioned in electrical communication with the electrolyte 118 to complete the electrical circuit used for electrolytically applying material to the first bond sites 130. The differences in electrical potential between the anode 120 and cathode 119 provides for the current flow. At this point, the second conductive layer 112 b can be generally continuous over the second surface 111 b of the support substrate 110, with the exception of local discontinuities at the vias 114. Accordingly, the second conductive layer 112 b can provide a highly conductive, low resistance link to the second bond site 130 b. The second conductive layer 112 b can also provide a highly conductive, low resistance link to the first bond site 130 a, via the conductive path 115 formed by the third conductive layer 112 c extending through the via 114.
  • During the electrolytic process, a first bond pad material 131 a can be applied to the first bond site 130 a and can form a first bond pad 137 a. A second bond pad material 131 b can be applied to the second bond site 130 b to form a second bond pad 137 b. The first and second bond pad materials 131 a, 131 b are referred to collectively as bond pad material 131. The bond pad material 131 can include a single constituent or a composite of constituents. For example, in one embodiment, the bond pad material 131 can include both nickel and gold, arranged in layers with a nickel layer 135 placed adjacent to the underlying conductive layer 112 a, 112 b, and with a gold layer 136 positioned against the nickel layer 135. In other embodiments, the bond pad material 131 can include composites of different conductive materials, or a single layer of a homogenous material. In any of these embodiments, the first bond pad material 131 a can at least partially fill the gap 117 between the first protective coating 140 a and the edge 116 of the first conductive layer 112 a. The presence of the gap 117 can allow the first bond pad material 131 a to wrap around the edge 116 a of the first conductive layer 112 a. In particular, the first bond pad material 131 a need not be offset away from the edge 116 a of the first conductive layer 112 a. This feature can be enabled by (a) patterning the first conductive layer 112 a before applying the first bond pad material 131 a, and (b) using a soldermask or similar material for the first protective coating 140 a. As a result, the first bond site 130 a can have a relatively large amount of first bond pad material 131 a accessible for electrical coupling, even though the first bond site 130 a itself may be relatively small to allow for close spacing between adjacent first bond sites 130 a.
  • After the bond pad material 131 has been applied to the bond sites 130, the second protective coating 140 b can be removed from the second conductive layer 112 b. Afterwards, the second conductive layer 112 b can be patterned to remove conductive material other than that located at the second bond site 130 b. Referring now to FIG. 2B, a third protective coating 140 c can be disposed over the second conductive layer 112 b, and can then be patterned to protect the second bond site 130 b and the conductive path 115 through the via 114. Accordingly, the third protective coating 140 c can include a temporary or otherwise removable, patternable material (e.g., a dry film, generally similar to the second protective coating 140 b described above). In a particular aspect of this embodiment, the third protective coating 140 c can extend around an edge 132 of the second bond pad material 131 b to protect the entire volume of the second bond pad material 131 b. As a result, the portion of the second conductive layer 112 b of the second bond site 130 b can be protected from being undercut when adjacent portions of the second conductive layer 112 b are removed.
  • Referring next to FIG. 2C, portions of the second conductive layer 112 b surrounding the second bond site 130 b can be removed (e.g., via an etching process), after which the third protective coating 140 c itself can also be removed. The second bond site 130 b can include an offset 133 between an edge 132 of the second bond pad material 131 b, and an edge 116 b of the second conductive material 112 b. The formation of this offset 133 results from the fact that the third protective coating 140 c was placed around the edge 132 during the process described above with reference to FIG. 2B. This offset 133 can result in a slight increase in the overall size of the second bond site 130 b (particularly in comparison to the first bond site 130 a). However, this increase in size is not expected to create undesirable increases in the spacing between adjacent second bond sites 130 b, because, on the second surface 112 b of the substrate 110, bond site spacing is not as critical. In particular, the second bond sites 130 b are intended to align with corresponding bond pads of external devices, which typically do not have bond pad pitch requirements as stringent as those for microfeature workpieces that are attached to the first bond sites 130 a.
  • In FIG. 2D, a fourth protective coating 140 d is applied to the second surface 111 b to provide for an at least generally permanent covering over the portions of the substrate 110 adjacent to the second bond site 130 b. Accordingly, the fourth protective coating 140 d can include a solder mask material that is either applied to (and then removed from) the second bond site 130 b, or prevented from adhering to the second bond site 130 b with an appropriate removable masking material. The support substrate 110 is now available for coupling to microfeature workpieces, and subsequently to external devices.
  • C. Support Substrates and Associated Installations
  • FIG. 3 is an enlarged, partially schematic illustration of a portion of the substrate 110, coupled to both a microfeature workpiece 150 and an external device 160. In one aspect of this embodiment, the substrate 110 can be coupled to the microfeature workpiece 150 via a first conductive coupler 134 a (e.g., a small solder ball) that extends between the first pad 137 a and a corresponding bond pad 337 a of the microfeature workpiece 150. The substrate 110 can be coupled to the external device 160 with a second conductive coupler 134 b (e.g., a larger solder ball) that extends between the second bond pad 137 b and a corresponding bond pad 337 b of the external device 160. The external device 160 can include a printed circuitboard or other device that is in electrical communication with the microfeature workpiece 150 by virtue of the interposed substrate 110.
  • FIG. 4 is an overall view illustrating the microfeature workpiece 150 positioned on the support substrate 110 and surrounded by an encapsulant 152 to form a packaged microelectronic device 151. This arrangement, typically referred to as a flip chip arrangement, includes a relatively fine pitch between the first bond pads 137 a to accommodate the relatively close spacing of the corresponding bond pads 337 a on the microfeature workpiece 150, and a coarser spacing of the second bond pads 137 b. As discussed above, the second bond pads 137 b typically need not be as closely spaced as the first bond pads 137 a because the pitch requirements of the bond pads 337 b on external device 160 are generally not as stringent as the pitch requirements of the microfeature workpiece 150.
  • In other embodiments, support substrates generally similar to those described above can be used in other arrangements. For example, referring now to FIG. 5, a support substrate 510 can be configured to support a microfeature workpiece 550 in a chip-on-board (COB) arrangement. Accordingly, the microfeature workpiece 550 can be electrically coupled to the support substrate 510 with first conductive couplers 554 a that include wirebonds extending between the first bond pads 137 a of the support substrate 510, and corresponding bond sites 537 a on an upper surface of the microfeature workpiece 550. Second conductive couplers 534 b (which can include solder balls) can extend between the second bond pads 137 b and corresponding bond pads 537 b of the external device 160. An encapsulant 552 can be positioned around the microfeature workpiece 550 and the support substrate 510 to form the packaged microelectronic device 551. In still other embodiments, the support substrate 510 can be configured to support microfeature workpieces in accordance with other configurations and/or arrangements.
  • One feature of embodiments of the support substrates and associated manufacturing methods described above is that the conductive bond pad material 131 a can be applied to the first bond site 130 a without the need for a bus at the first surface of the support substrate 110. Instead, electrical power for applying the first bond pad material 130 a can be provided by applying current to the second conductive layer 112 b and using the conductive path 115 provided by the via 114 to conduct electrical current to the first bond site 130 a. An advantage of this arrangement is that the first bond pad 137 a can be formed without a bus and accordingly, the potentially negative effects associated with a bus (e.g., extraneous signals that may result when the bus acts as an antenna), may be eliminated.
  • Another feature of embodiments of the support substrate described above is that the first bond pad material 131 a can cover not only the outwardly facing surface of the first conductive material 112 a at the first bond site 130 a, but can also cover the adjacent edge 116. An advantage of this arrangement is that it can eliminate or at least reduce the likelihood that subsequent etching processes will undercut the first conductive layer 112 a at the edge 116, by virtue of the protection afforded by the first bond pad material 131 a at this location. As a result, the physical and electrical characteristics of the first bond pad 137 a can be more robust than corresponding bond pads formed by other methods.
  • Another feature of embodiments of the support substrate described above is that the first bond material 131 a is not offset from the edge of the first conductive layer 112 a immediately below (unlike the second bond pad material 130 b, which is offset from the edge of the corresponding second conductive layer 112 b by an offset 133). An advantage of this arrangement is that it can provide for a greater surface area of highly conductive material at the first bond site 130 a than would be available if the first bond pad material 131 a were offset from the underlying first conductive layer 112 a. This can allow the overall size of the first bond site 130 a to be reduced (because the available area at the first bond site 130 a is more effectively utilized) and can accordingly allow adjacent first bond pads 137 a to be spaced more closely together. An advantage of this arrangement is that it can allow for electrical connections (via solder balls or other structures) to corresponding microfeature workpieces that have very fine bond pad pitch spacings.
  • From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the invention. For example, in some embodiments, the bond sites can have arrangements different than those described above. Many of the Figures illustrate features of the disclosed embodiments in a schematic fashion. Accordingly, many of these features may have dimensions and/or relative dimensions that are different than those illustrated in the Figures. Aspects of the invention described in the context of particular embodiments may be combined or eliminated in other embodiments. Further, while advantages associated with certain embodiments of the invention have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments need necessarily exhibit such advantages to fall within the scope of the invention. Accordingly, the invention is not limited, except as by the appended claims.

Claims (9)

  1. 1. A microelectronic system, comprising:
    a support substrate configured to carry a microfeature die, the support substrate having a first surface with a first conductive layer having multiple first bond sites, and a second surface facing opposite from the first surface, the second surface having a second conductive layer with multiple second bond sites;
    conductive bond pad material positioned at the first bond sites to form first bond pads, the first bond pads being separated from each other by a first average spacing, the bond pad material extending around an edge of the first conductive layer at the first bond sites;
    conductive bond pad material positioned at the second bond sites to form second bond pads, the first and second bond pads being electrically coupled with conductive pathways extending through the support substrate, the second bond pads being separated from each other by a second average spacing greater than the first average spacing, the bond pad material having a different arrangement at the second bond sites than at the first bond sites.
  2. 2. The system of claim 1 wherein the bond pad material at the second bond sites is spaced apart from an edge of the second conductive layer at the second bond sites.
  3. 3. The system of claim 1, further comprising conductive couplers attached to the second bond pad sites.
  4. 4. The system of claim 1, further comprising:
    a microfeature die carried by the support substrate and electrically coupled to the first bond pads of the support substrate; and
    an external device electrically coupled to the second bond pads of the support substrate.
  5. 5. The system of claim 1, further comprising a microfeature die carried by the support substrate and electrically coupled to the first bond pads of the support substrate.
  6. 6. A microelectronic system, comprising:
    a support substrate configured to carry a microfeature die, the support substrate having a first surface with a first conductive layer having multiple first bond sites, and a second surface facing opposite from the first surface, the second surface having a second conductive layer with multiple second bond sites;
    conductive bond pad material positioned at the first bond pad sites to form first bond pads, the first bond pads being separated from each other by a first average spacing, the bond pad material extending around an edge of the first conductive layer at the first bond sites;
    conductive bond pad material positioned at the second bond pad sites to form second bond pads, the first and second bond pads being electrically coupled with conductive pathways extending through the support substrate, the second bond pads being separated from each other by a second average spacing greater than the first average spacing, the bond pad material being offset laterally from an edge of the of the second conductive layer at the second bond sites;
    a first at least generally permanent protective coating positioned adjacent to the first bond pads; and
    a second at least generally permanent protective coating positioned on the second surface.
  7. 7. The system of claim 6, further comprising conductive couplers attached to the second bond pad sites.
  8. 8. The system of claim 6, further comprising:
    a microfeature die carried by the support substrate and electrically coupled to the first bond pads of the support substrate; and
    an external device electrically coupled to the second bond pads of the support substrate.
  9. 9. The system of claim 6, further comprising a microfeature die carried by the support substrate and electrically coupled to the first bond pads of the support substrate.
US12615518 2005-09-01 2009-11-10 Microfeature workpiece substrates having through-substrate vias, and associated methods of formation Abandoned US20100052183A1 (en)

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Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7091124B2 (en) * 2003-11-13 2006-08-15 Micron Technology, Inc. Methods for forming vias in microelectronic devices, and methods for packaging microelectronic devices
US8084866B2 (en) 2003-12-10 2011-12-27 Micron Technology, Inc. Microelectronic devices and methods for filling vias in microelectronic devices
US20050247894A1 (en) 2004-05-05 2005-11-10 Watkins Charles M Systems and methods for forming apertures in microfeature workpieces
US7232754B2 (en) 2004-06-29 2007-06-19 Micron Technology, Inc. Microelectronic devices and methods for forming interconnects in microelectronic devices
US7083425B2 (en) 2004-08-27 2006-08-01 Micron Technology, Inc. Slanted vias for electrical circuits on circuit boards and other substrates
US7300857B2 (en) 2004-09-02 2007-11-27 Micron Technology, Inc. Through-wafer interconnects for photoimager and memory wafers
US7271482B2 (en) 2004-12-30 2007-09-18 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US7795134B2 (en) 2005-06-28 2010-09-14 Micron Technology, Inc. Conductive interconnect structures and formation methods using supercritical fluids
US7262134B2 (en) 2005-09-01 2007-08-28 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7863187B2 (en) 2005-09-01 2011-01-04 Micron Technology, Inc. Microfeature workpieces and methods for forming interconnects in microfeature workpieces
US7749899B2 (en) 2006-06-01 2010-07-06 Micron Technology, Inc. Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces
US7629249B2 (en) 2006-08-28 2009-12-08 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
US7902643B2 (en) 2006-08-31 2011-03-08 Micron Technology, Inc. Microfeature workpieces having interconnects and conductive backplanes, and associated systems and methods
US7791203B2 (en) 2007-07-12 2010-09-07 Micron Technology, Inc. Interconnects for packaged semiconductor devices and methods for manufacturing such devices
US7830018B2 (en) 2007-08-31 2010-11-09 Micron Technology, Inc. Partitioned through-layer via and associated systems and methods
US7884015B2 (en) 2007-12-06 2011-02-08 Micron Technology, Inc. Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
US8084854B2 (en) 2007-12-28 2011-12-27 Micron Technology, Inc. Pass-through 3D interconnect for microelectronic dies and associated systems and methods
US8253230B2 (en) 2008-05-15 2012-08-28 Micron Technology, Inc. Disabling electrical connections using pass-through 3D interconnects and associated systems and methods
US7932170B1 (en) * 2008-06-23 2011-04-26 Amkor Technology, Inc. Flip chip bump structure and fabrication method
US7969774B2 (en) 2009-03-10 2011-06-28 Micron Technology, Inc. Electronic devices formed of two or more substrates bonded together, electronic systems comprising electronic devices and methods of making electronic devices
JP5290215B2 (en) 2010-02-15 2013-09-18 ルネサスエレクトロニクス株式会社 Semiconductor device, a semiconductor package, interposer, and the interposer manufacturing method of
US8343781B2 (en) 2010-09-21 2013-01-01 International Business Machines Corporation Electrical mask inspection
US8973258B2 (en) * 2012-07-02 2015-03-10 Subtron Technology Co., Ltd. Manufacturing method of substrate structure
US9048410B2 (en) 2013-05-31 2015-06-02 Micron Technology, Inc. Memory devices comprising magnetic tracks individually comprising a plurality of magnetic domains having domain walls and methods of forming a memory device comprising magnetic tracks individually comprising a plurality of magnetic domains having domain walls
JP2015177382A (en) * 2014-03-15 2015-10-05 キヤノン株式会社 Device with element electrode connected with through-wiring, and manufacturing method thereof

Citations (100)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6180518B2 (en) *
US5481483A (en) * 1992-11-23 1996-01-02 Ford Motor Company Non-contact method of obtaining dimensional information about an object for comparing similar objects
US5485039A (en) * 1991-12-27 1996-01-16 Hitachi, Ltd. Semiconductor substrate having wiring conductors at a first main surface electrically connected to plural pins at a second main surface
US5496755A (en) * 1989-11-29 1996-03-05 Texas Instruments Incorporated Integrated circuit and method
US5593927A (en) * 1993-10-14 1997-01-14 Micron Technology, Inc. Method for packaging semiconductor dice
US5593913A (en) * 1993-09-28 1997-01-14 Sharp Kabushiki Kaisha Method of manufacturing solid state imaging device having high sensitivity and exhibiting high degree of light utilization
US5605783A (en) * 1995-01-06 1997-02-25 Eastman Kodak Company Pattern transfer techniques for fabrication of lenslet arrays for solid state imagers
US5614743A (en) * 1994-07-26 1997-03-25 Kabushiki Kaisha Toshiba Microwave integrated circuit (MIC) having a reactance element formed on a groove
US5708293A (en) * 1996-01-05 1998-01-13 Matsushita Electronics Corporation Lead frame and method of mounting semiconductor chip
US5718791A (en) * 1995-06-05 1998-02-17 R + S Stanztechnik Gmbh Method of laminating a trim panel and folding a cover sheet edge around the panel rim
US5723904A (en) * 1993-03-10 1998-03-03 Sumitomo Electric Industries, Ltd. Packaged semiconductor device suitable to be mounted and connected to microstrip line structure board
US5726493A (en) * 1994-06-13 1998-03-10 Fujitsu Limited Semiconductor device and semiconductor device unit having ball-grid-array type package structure
US5734555A (en) * 1994-03-30 1998-03-31 Intel Corporation Shared socket multi-chip module and/or piggyback pin grid array package
US5857963A (en) * 1996-07-17 1999-01-12 Welch Allyn, Inc. Tab imager assembly for use in an endoscope
US5861654A (en) * 1995-11-28 1999-01-19 Eastman Kodak Company Image sensor assembly
US5870289A (en) * 1994-12-15 1999-02-09 Hitachi, Ltd. Chip connection structure having diret through-hole connections through adhesive film and wiring substrate
US5870823A (en) * 1996-11-27 1999-02-16 International Business Machines Corporation Method of forming a multilayer electronic packaging substrate with integral cooling channels
US5877040A (en) * 1995-08-10 1999-03-02 Lg Semicon Co., Ltd. Method of making charge-coupled device with microlens
US6018249A (en) * 1997-12-11 2000-01-25 Micron Technolgoy, Inc. Test system with mechanical alignment for semiconductor chip scale packages and dice
US6020624A (en) * 1991-06-04 2000-02-01 Micron Technology, Inc. Semiconductor package with bi-substrate die
US6180518B1 (en) * 1999-10-29 2001-01-30 Lucent Technologies Inc. Method for forming vias in a low dielectric constant material
US6184465B1 (en) * 1998-11-12 2001-02-06 Micron Technology, Inc. Semiconductor package
US6184060B1 (en) * 1996-10-29 2001-02-06 Trusi Technologies Llc Integrated circuits and methods for their fabrication
US6188232B1 (en) * 1996-12-31 2001-02-13 Micron Technology, Inc. Temporary package, system, and method for testing semiconductor dice and chip scale packages
US6187615B1 (en) * 1998-08-28 2001-02-13 Samsung Electronics Co., Ltd. Chip scale packages and methods for manufacturing the chip scale packages at wafer level
US6191487B1 (en) * 1998-04-23 2001-02-20 Minco Technology Labs, Inc. Semiconductor and flip chip packages and method having a back-side connection
US6201304B1 (en) * 1995-12-19 2001-03-13 Micron Technology, Inc. Flip chip adaptor package for bare die
US6203539B1 (en) * 1993-05-07 2001-03-20 Visx, Incorporated Method and system for laser treatment of refractive errors using offset imaging
US20020005583A1 (en) * 2000-06-07 2002-01-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and fabrication process therefor
US20020006687A1 (en) * 2000-05-23 2002-01-17 Lam Ken M. Integrated IC chip package for electronic image sensor die
US6341009B1 (en) * 2000-02-24 2002-01-22 Quantronix Corporation Laser delivery system and method for photolithographic mask repair
US6344976B1 (en) * 1997-04-07 2002-02-05 Micron Technology, Inc. Interdigitated leads-over-chip lead frame device and method for supporting an integrated circuit die
US20020020898A1 (en) * 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6351027B1 (en) * 2000-02-29 2002-02-26 Agilent Technologies, Inc. Chip-mounted enclosure
US20020027293A1 (en) * 2001-06-28 2002-03-07 Fujitsu Limited Three dimensional semiconductor integrated circuit device and method for making the same
US6359328B1 (en) * 1998-12-31 2002-03-19 Intel Corporation Methods for making interconnects and diffusion barriers in integrated circuits
US6359254B1 (en) * 1999-09-30 2002-03-19 United Technologies Corporation Method for producing shaped hole in a structure
US6503780B1 (en) * 2000-07-05 2003-01-07 Amkor Technology, Inc. Wafer scale image sensor package fabrication method
US20030014895A1 (en) * 1999-10-08 2003-01-23 Lizotte Todd E. Control system for ablating high-density array of vias or indentation in surface of object
US6521530B2 (en) * 1998-11-13 2003-02-18 Fujitsu Limited Composite interposer and method for producing a composite interposer
US6521516B2 (en) * 2001-06-29 2003-02-18 Intel Corporation Process for local on-chip cooling of semiconductor devices using buried microchannels
US20030042564A1 (en) * 2000-12-04 2003-03-06 Fujitsu Limited Semiconductor device having an interconnecting post formed on an interposer within a sealing resin
US6534192B1 (en) * 1999-09-24 2003-03-18 Lucent Technologies Inc. Multi-purpose finish for printed wiring boards and method of manufacture of such boards
US6534863B2 (en) * 2001-02-09 2003-03-18 International Business Machines Corporation Common ball-limiting metallurgy for I/O sites
US20040004280A1 (en) * 2002-07-04 2004-01-08 Manabu Shibata Semiconductor device and system having semiconductor device mounted thereon
US6680459B2 (en) * 2001-06-22 2004-01-20 Nippei Toyama Corporation Laser beam machining apparatus and laser beam machining method
US20040012698A1 (en) * 2001-03-05 2004-01-22 Yasuo Suda Image pickup model and image pickup device
US20040018712A1 (en) * 2002-07-29 2004-01-29 Plas Hubert Vander Method of forming a through-substrate interconnect
US6686588B1 (en) * 2001-01-16 2004-02-03 Amkor Technology, Inc. Optical module with lens integral holder
US20040023469A1 (en) * 2001-03-21 2004-02-05 Canon Kabushiki Kaisha Semiconductor device and its manufacture method
US20040023447A1 (en) * 2002-08-02 2004-02-05 Semiconductor Energy Laboratory Co., Ltd. Organic thin film transistor and method of manufacturing the same, and semiconductor device having the organic thin film transistor
US20040038442A1 (en) * 2002-08-26 2004-02-26 Kinsman Larry D. Optically interactive device packages and methods of assembly
US6699787B2 (en) * 2001-06-14 2004-03-02 Shinko Electric Industries Co., Ltd. Semiconductor device and method of production of same
US20040043607A1 (en) * 2002-08-29 2004-03-04 Farnworth Warren M. Methods for creating electrophoretically insulated vias in semiconductive substrates and resulting structures
US20040041261A1 (en) * 2002-08-29 2004-03-04 Kinsman Larry D. Flip-chip image sensor packages and methods of fabrication
US6703310B2 (en) * 2001-06-14 2004-03-09 Shinko Electric Industries Co., Ltd. Semiconductor device and method of production of same
US20040046251A1 (en) * 2002-08-20 2004-03-11 Seung-Whan Lee Semiconductor contact structure and method of forming the same
US6708405B2 (en) * 2000-08-28 2004-03-23 Infineon Technologies Ag Method for producing an electrically conducting connection
US6838377B2 (en) * 2001-03-05 2005-01-04 Murata Manufacturing Co., Ltd. High frequency circuit chip and method of producing the same
US6841849B2 (en) * 2002-03-19 2005-01-11 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board and electronic instrument
US6844978B2 (en) * 1997-10-03 2005-01-18 Digital Optics Corp. Wafer level creation of multiple optical elements
US6847109B2 (en) * 2002-09-25 2005-01-25 Samsung Electronics Co., Ltd. Area array semiconductor package and 3-dimensional stack thereof
US20050026443A1 (en) * 2003-08-01 2005-02-03 Goo Ju-Seon Method for forming a silicon oxide layer using spin-on glass
US6852621B2 (en) * 2000-01-21 2005-02-08 Seiko Epson Corporation Semiconductor device and manufacturing method therefor, circuit board, and electronic equipment
US6856023B2 (en) * 2002-01-22 2005-02-15 Canon Kabushiki Kaisha Semiconductor device and method of manufacturing semiconductor device
US20050037608A1 (en) * 2003-08-13 2005-02-17 Ibm Deep filled vias
US6858891B2 (en) * 2002-03-06 2005-02-22 Micron Technology, Inc. Nanotube semiconductor devices and methods for making the same
US6982487B2 (en) * 2003-03-25 2006-01-03 Samsung Electronics Co., Ltd. Wafer level package and multi-package stack
US20060003566A1 (en) * 2004-06-30 2006-01-05 Ismail Emesh Methods and apparatuses for semiconductor fabrication utilizing through-wafer interconnects
US20060014313A1 (en) * 2004-07-16 2006-01-19 Hall Frank L Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US20060011809A1 (en) * 2004-07-19 2006-01-19 Farnworth Warren M Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers
US20060023107A1 (en) * 2004-08-02 2006-02-02 Bolken Todd O Microelectronic imagers with optics supports having threadless interfaces and methods for manufacturing such microelectronic imagers
US20060024856A1 (en) * 2004-07-28 2006-02-02 Derderian James M Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US20060035402A1 (en) * 2004-08-10 2006-02-16 Street Bret K Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US20060035415A1 (en) * 2004-08-16 2006-02-16 Wood Alan G Frame structure and semiconductor attach process for use therewith for fabrication of image sensor packages and the like, and resulting packages
US20060040421A1 (en) * 2004-08-19 2006-02-23 Farnworth Warren M Spacers for packaged microelectronic imagers and methods of making and using spacers for wafer-level packaging of imagers
US20060040428A1 (en) * 2004-08-19 2006-02-23 Johnson Mark S Conductive structures for microfeature devices and methods for fabricating microfeature devices
US20060038183A1 (en) * 2004-08-19 2006-02-23 Oliver Steven D Microelectronic imagers with curved image sensors and methods for manufacturing microelectronic imagers
US20060038272A1 (en) * 2004-08-17 2006-02-23 Texas Instruments Incorporated Stacked wafer scale package
US20070004079A1 (en) * 2005-06-30 2007-01-04 Geefay Frank S Method for making contact through via contact to an offset contactor inside a cap for the wafer level packaging of FBAR chips
US7164565B2 (en) * 2002-11-29 2007-01-16 Sigmatel, Inc. ESD protection circuit
US20070012655A1 (en) * 2005-07-15 2007-01-18 Samsung Electronics Co., Ltd. Micro-package, multi-stack micro-package, and manufacturing method therefor
US7166247B2 (en) * 2002-06-24 2007-01-23 Micron Technology, Inc. Foamed mechanical planarization pads made with supercritical fluid
US20070020805A1 (en) * 2002-02-20 2007-01-25 Kim Sarah E Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack
US20070020935A1 (en) * 2005-07-19 2007-01-25 Taylor Theodore M Process for enhancing solubility and reaction rates in supercritical fluids
US7170183B1 (en) * 2005-05-13 2007-01-30 Amkor Technology, Inc. Wafer level stacked package
US20070023121A1 (en) * 2005-07-29 2007-02-01 Freescale Semiconductor, Inc. Fabrication of three dimensional integrated circuit employing multiple die panels
US20070032061A1 (en) * 2005-08-05 2007-02-08 Farnworth Warren M Methods of forming through-wafer interconnects and structures resulting therefrom
US20070035033A1 (en) * 2005-05-26 2007-02-15 Volkan Ozguz Stackable tier structure comprising high density feedthrough
US20070037379A1 (en) * 2005-08-11 2007-02-15 Ziptronix 3D IC method and device
US20070042598A1 (en) * 2003-03-04 2007-02-22 Hyun-Mog Park Dielectric with sidewall passivating layer
US7183176B2 (en) * 2004-08-25 2007-02-27 Agency For Science, Technology And Research Method of forming through-wafer interconnects for vertical wafer level packaging
US7183653B2 (en) * 2003-12-17 2007-02-27 Intel Corporation Via including multiple electrical paths
US7317256B2 (en) * 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US20080006850A1 (en) * 2006-07-10 2008-01-10 Innovative Micro Technology System and method for forming through wafer vias using reverse pulse plating
US20080050911A1 (en) * 2006-08-28 2008-02-28 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
US20080050904A1 (en) * 2006-08-28 2008-02-28 Micron Technology, Inc. Methods for attaching microfeature dies to external devices
US20090007934A1 (en) * 2007-07-06 2009-01-08 Micron Technology, Inc. Systems and methods for exposing semiconductor workpieces to vapors for through-hole cleaning and/or other processes
US20090014859A1 (en) * 2007-07-12 2009-01-15 Micron Technology, Inc. Interconnects for packaged semiconductor devices and methods for manufacturing such devices
US7491582B2 (en) * 2004-08-31 2009-02-17 Seiko Epson Corporation Method for manufacturing semiconductor device and semiconductor device

Family Cites Families (139)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2821959A (en) 1956-03-29 1958-02-04 Bell Telephone Labor Inc Mass soldering of electrical assemblies
US3006318A (en) 1958-03-26 1961-10-31 Western Electric Co Apparatus for applying solder coatings to surfaces
DE1160831B (en) 1962-04-21 1964-01-09 Knapsack Ag Method and apparatus for the production of titanium nitride
US3865298A (en) 1973-08-14 1975-02-11 Atomic Energy Commission Solder leveling
US3902036A (en) 1974-05-02 1975-08-26 Western Electric Co Control system using multiplexed laser beams
US4040168A (en) 1975-11-24 1977-08-09 Rca Corporation Fabrication method for a dual gate field-effect transistor
US4368106A (en) 1980-10-27 1983-01-11 General Electric Company Implantation of electrical feed-through conductors
US5027184A (en) 1981-03-02 1991-06-25 Rockwell International Corporation NPN type lateral transistor with minimal substrate operation interference
US4756765A (en) 1982-01-26 1988-07-12 Avco Research Laboratory, Inc. Laser removal of poor thermally-conductive materials
US4534100A (en) 1982-06-28 1985-08-13 The United States Of America As Represented By The Secretary Of The Air Force Electrical method of making conductive paths in silicon
JPH0576778B2 (en) 1983-05-20 1993-10-25 Hitachi Ltd
FR2547519B1 (en) 1983-06-15 1987-07-03 Snecma Method and device for drilling by laser
US4581301A (en) 1984-04-10 1986-04-08 Michaelson Henry W Additive adhesive based process for the manufacture of printed circuit boards
US4984597B1 (en) 1984-05-21 1999-10-26 Cfmt Inc Apparatus for rinsing and drying surfaces
US4660063A (en) 1985-03-18 1987-04-21 General Electric Company Immersion type ISFET
US4627971A (en) 1985-04-22 1986-12-09 Alza Corporation Osmotic device with self-sealing passageway
US5026964A (en) 1986-02-28 1991-06-25 General Electric Company Optical breakthrough sensor for laser drill
US4768291A (en) 1987-03-12 1988-09-06 Monarch Technologies Corporation Apparatus for dry processing a semiconductor wafer
US5219344A (en) 1988-06-09 1993-06-15 Visx, Incorporated Methods and apparatus for laser sculpture of the cornea
DE3831141A1 (en) 1988-09-13 1990-03-22 Zeiss Carl Fa Method and apparatus for micro-surgery on the eye by laser radiation
FR2637151A1 (en) 1988-09-29 1990-03-30 Commissariat Energie Atomique Electrical connections Method of realization through a substrate
USRE36469E (en) 1988-09-30 1999-12-28 Micron Technology, Inc. Packaging for semiconductor logic devices
US4959705A (en) 1988-10-17 1990-09-25 Ford Microelectronics, Inc. Three metal personalization of application specific monolithic microwave integrated circuit
US5024966A (en) 1988-12-21 1991-06-18 At&T Bell Laboratories Method of forming a silicon-based semiconductor optical device mount
US4906314A (en) 1988-12-30 1990-03-06 Micron Technology, Inc. Process for simultaneously applying precut swatches of precured polyimide film to each semiconductor die on a wafer
JPH02257643A (en) 1989-03-29 1990-10-18 Mitsubishi Electric Corp Semiconductor device and its manufacture
US5145099A (en) 1990-07-13 1992-09-08 Micron Technology, Inc. Method for combining die attach and lead bond in the assembly of a semiconductor package
FR2665574B1 (en) 1990-08-03 1997-05-30 Thomson Composants Microondes Method for interconnection between an integrated circuit and a substrate circuit, and integrated circuitry adapted to this method.
JP2797684B2 (en) 1990-10-04 1998-09-17 ブラザー工業株式会社 Method and apparatus for manufacturing a nozzle
US5294568A (en) 1990-10-12 1994-03-15 Genus, Inc. Method of selective etching native oxide
US5130783A (en) 1991-03-04 1992-07-14 Texas Instruments Incorporated Flexible film semiconductor package
US5292686A (en) 1991-08-21 1994-03-08 Triquint Semiconductor, Inc. Method of forming substrate vias in a GaAs wafer
US5128831A (en) 1991-10-31 1992-07-07 Micron Technology, Inc. High-density electronic package comprising stacked sub-modules which are electrically interconnected by solder-filled vias
US5289631A (en) 1992-03-04 1994-03-01 Mcnc Method for testing, burn-in, and/or programming of integrated circuit chips
JPH05251717A (en) 1992-03-04 1993-09-28 Hitachi Ltd Semiconductor package and semiconductor module
US5233448A (en) 1992-05-04 1993-08-03 Industrial Technology Research Institute Method of manufacturing a liquid crystal display panel including photoconductive electrostatic protection
US5389738A (en) 1992-05-04 1995-02-14 Motorola, Inc. Tamperproof arrangement for an integrated circuit device
US5760834A (en) 1992-09-30 1998-06-02 Lsi Logic Electronic camera with binary lens element array
JP2833941B2 (en) 1992-10-09 1998-12-09 三菱電機株式会社 The solid-state imaging device and manufacturing method thereof
US5464960A (en) 1993-01-12 1995-11-07 Iatrotech, Inc. Laser calibration device
EP0683921B1 (en) 1993-02-04 2004-06-16 Cornell Research Foundation, Inc. Microstructures and single mask, single-crystal process for fabrication thereof
JPH06310547A (en) 1993-02-25 1994-11-04 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
JP2842132B2 (en) 1993-03-05 1998-12-24 松下電器産業株式会社 Optical device
US5447871A (en) 1993-03-05 1995-09-05 Goldstein; Edward F. Electrically conductive interconnection through a body of semiconductor material
JP3161142B2 (en) 1993-03-26 2001-04-25 ソニー株式会社 Semiconductor device
US5518956A (en) 1993-09-02 1996-05-21 General Electric Company Method of isolating vertical shorts in an electronic array using laser ablation
US5435887A (en) 1993-11-03 1995-07-25 Massachusetts Institute Of Technology Methods for the fabrication of microstructure arrays
US5378312A (en) 1993-12-07 1995-01-03 International Business Machines Corporation Process for fabricating a semiconductor structure having sidewalls
EP0775304B1 (en) 1993-12-10 2000-02-09 Amersham Pharmacia Biotech AB Method of producing cavity structures
US5585308A (en) 1993-12-23 1996-12-17 Sgs-Thomson Microelectronics, Inc. Method for improved pre-metal planarization
JP3253439B2 (en) 1993-12-24 2002-02-04 シャープ株式会社 A method of manufacturing a liquid crystal display element
US5536455A (en) 1994-01-03 1996-07-16 Omron Corporation Method of manufacturing lens array
JP3531199B2 (en) 1994-02-22 2004-05-24 三菱電機株式会社 The optical transmission device
KR0147401B1 (en) 1994-02-23 1998-08-01 구본준 Solid image sensor and the fabrication method thereof
US5380681A (en) 1994-03-21 1995-01-10 United Microelectronics Corporation Three-dimensional multichip package and methods of fabricating
US6008914A (en) * 1994-04-28 1999-12-28 Mitsubishi Denki Kabushiki Kaisha Laser transfer machining apparatus
US5627106A (en) 1994-05-06 1997-05-06 United Microelectronics Corporation Trench method for three dimensional chip connecting during IC fabrication
US5585675A (en) 1994-05-11 1996-12-17 Harris Corporation Semiconductor die packaging tub having angularly offset pad-to-pad via structure configured to allow three-dimensional stacking and electrical interconnections among multiple identical tubs
US5515167A (en) 1994-09-13 1996-05-07 Hughes Aircraft Company Transparent optical chuck incorporating optical monitoring
US5521434A (en) 1994-10-17 1996-05-28 International Business Machines Corporation Semiconductor chip and electronic module with integrated surface interconnects/components
US5904499A (en) 1994-12-22 1999-05-18 Pace; Benedict G Package for power semiconductor chips
US5624437A (en) 1995-03-28 1997-04-29 Freeman; Jerre M. High resolution, high speed, programmable laser beam modulating apparatus for microsurgery
US5677566A (en) 1995-05-08 1997-10-14 Micron Technology, Inc. Semiconductor chip package
US5646067A (en) 1995-06-05 1997-07-08 Harris Corporation Method of bonding wafers having vias including conductive material
US5673846A (en) 1995-08-24 1997-10-07 International Business Machines Corporation Solder anchor decal and method
JP3263705B2 (en) 1995-09-21 2002-03-11 三菱電機株式会社 Printed circuit board and the flat panel display driving circuit for a printed wiring board and the flat panel display device
US5851845A (en) 1995-12-18 1998-12-22 Micron Technology, Inc. Process for packaging a semiconductor die using dicing and testing
JP2905736B2 (en) 1995-12-18 1999-06-14 株式会社エイ・ティ・アール光電波通信研究所 Semiconductor device
US5776824A (en) 1995-12-22 1998-07-07 Micron Technology, Inc. Method for producing laminated film/metal structures for known good die ("KG") applications
US5773359A (en) 1995-12-26 1998-06-30 Motorola, Inc. Interconnect system and method of fabrication
US5673730A (en) 1996-01-24 1997-10-07 Micron Technology, Inc. Form tooling and method of forming semiconductor package leads
US5914488A (en) 1996-03-05 1999-06-22 Mitsubishi Denki Kabushiki Kaisha Infrared detector
US5893828A (en) 1996-05-02 1999-04-13 Uram; Martin Contact laser surgical endoscope and associated myringotomy procedure
NL1003315C2 (en) 1996-06-11 1997-12-17 Europ Semiconductor Assembly E Method for encapsulating an integrated halfgeleiderschake- rail.
US5801442A (en) 1996-07-22 1998-09-01 Northrop Grumman Corporation Microchannel cooling of high power semiconductor devices
KR100222299B1 (en) 1996-12-16 1999-10-01 윤종용 Wafer level chip scale package and method of manufacturing the same
US5821532A (en) 1997-06-16 1998-10-13 Eastman Kodak Company Imager package substrate
US5986209A (en) 1997-07-09 1999-11-16 Micron Technology, Inc. Package stack via bottom leaded plastic (BLP) packaging
US5811799A (en) 1997-07-31 1998-09-22 Wu; Liang-Chung Image sensor package having a wall with a sealed cover
US5807439A (en) 1997-09-29 1998-09-15 Siemens Aktiengesellschaft Apparatus and method for improved washing and drying of semiconductor wafers
US5891797A (en) 1997-10-20 1999-04-06 Micron Technology, Inc. Method of forming a support structure for air bridge wiring of an integrated circuit
US6222136B1 (en) * 1997-11-12 2001-04-24 International Business Machines Corporation Printed circuit board with continuous connective bumps
US5998292A (en) 1997-11-12 1999-12-07 International Business Machines Corporation Method for making three dimensional circuit integration
FI982568A (en) * 1997-12-02 1999-06-03 Samsung Electro Mech A method for manufacturing a multi-layer printed circuit board
US6195883B1 (en) * 1998-03-25 2001-03-06 International Business Machines Corporation Full additive process with filled plated through holes
US5933713A (en) 1998-04-06 1999-08-03 Micron Technology, Inc. Method of forming overmolded chip scale package and resulting product
US5990566A (en) 1998-05-20 1999-11-23 Micron Technology, Inc. High density semiconductor package
US6008070A (en) 1998-05-21 1999-12-28 Micron Technology, Inc. Wafer level fabrication and assembly of chip scale packages
FR2781707B1 (en) * 1998-07-30 2000-09-08 Snecma Method for machining by excimer laser holes or forms a variable profile
US6324253B1 (en) * 1998-08-26 2001-11-27 Yuyama Mfg. Co., Ltd. Tablet inspection apparatus
US6406636B1 (en) * 1999-06-02 2002-06-18 Megasense, Inc. Methods for wafer to wafer bonding using microstructures
JP3562389B2 (en) * 1999-06-25 2004-09-08 三菱電機株式会社 Laser heat treatment apparatus
US6457515B1 (en) * 1999-08-06 2002-10-01 The Ohio State University Two-layered micro channel heat sink, devices and systems incorporating same
JP4774146B2 (en) * 1999-12-23 2011-09-14 パナソニック株式会社 Method and apparatus for drilling a smaller pitch than the wavelength by using a laser
EP1301154A2 (en) * 2000-01-12 2003-04-16 LaserSight Technologies, Inc. Laser fluence compensation of a curved surface
JP3677429B2 (en) * 2000-03-09 2005-08-03 Necエレクトロニクス株式会社 Method of manufacturing a flip chip type semiconductor device
US6433303B1 (en) * 2000-03-31 2002-08-13 Matsushita Electric Industrial Co., Ltd. Method and apparatus using laser pulses to make an array of microcavity holes
JP4439090B2 (en) * 2000-07-26 2010-03-24 日本テキサス・インスツルメンツ株式会社 Semiconductor device and manufacturing method thereof
US6582987B2 (en) * 2000-12-30 2003-06-24 Electronics And Telecommunications Research Institute Method of fabricating microchannel array structure embedded in silicon substrate
DE10101875B4 (en) * 2001-01-16 2006-05-04 Infineon Technologies Ag Electronic component having successive stacked semiconductor chips and process for its preparation
US20020130390A1 (en) * 2001-03-13 2002-09-19 Ming-Dou Ker ESD protection circuit with very low input capacitance for high-frequency I/O ports
US6620031B2 (en) * 2001-04-04 2003-09-16 Lam Research Corporation Method for optimizing the planarizing length of a polishing pad
US6943056B2 (en) * 2002-04-16 2005-09-13 Renesas Technology Corp. Semiconductor device manufacturing method and electronic equipment using same
US6599436B1 (en) * 2001-12-06 2003-07-29 Sandia Corporation Formation of interconnections to microfluidic devices
US6724798B2 (en) * 2001-12-31 2004-04-20 Honeywell International Inc. Optoelectronic devices and method of production
US6756564B2 (en) * 2001-12-31 2004-06-29 Andrx Pharmaceuticals Llc System and method for removing particulate created from a drilled or cut surface
US7332819B2 (en) * 2002-01-09 2008-02-19 Micron Technology, Inc. Stacked die in die BGA package
US6606251B1 (en) * 2002-02-07 2003-08-12 Cooligy Inc. Power conditioning module
US6653236B2 (en) * 2002-03-29 2003-11-25 Micron Technology, Inc. Methods of forming metal-containing films over surfaces of semiconductor substrates; and semiconductor constructions
US6682955B2 (en) * 2002-05-08 2004-01-27 Micron Technology, Inc. Stacked die module and techniques for forming a stacked die module
US6621045B1 (en) * 2002-07-25 2003-09-16 Matsushita Electric Industrial Co., Ltd. Workpiece stabilization with gas flow
US20040036170A1 (en) * 2002-08-20 2004-02-26 Lee Teck Kheng Double bumping of flexible substrate for first and second level interconnects
US6936536B2 (en) * 2002-10-09 2005-08-30 Micron Technology, Inc. Methods of forming conductive through-wafer vias
US20040094389A1 (en) * 2002-11-19 2004-05-20 Boyce Keith W. Conveyor having carriers with movable jaws
JP4209178B2 (en) * 2002-11-26 2009-01-14 新光電気工業株式会社 Electronic parts packaging structure and a method of manufacturing the same
KR100621991B1 (en) * 2003-01-03 2006-09-13 삼성전자주식회사 Chip scale stack package
US20050236421A9 (en) * 2003-01-23 2005-10-27 Vasilios Vasiadis Device for handling and orienting pills or tablets in a precise manner
US7023090B2 (en) * 2003-01-29 2006-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding pad and via structure design
US7102238B2 (en) * 2003-04-24 2006-09-05 Sanyo Electric Co., Ltd. Semiconductor device and manufacturing method thereof
US6913952B2 (en) * 2003-07-03 2005-07-05 Micron Technology, Inc. Methods of forming circuit traces and contact pads for interposers utilized in semiconductor packages
US7118833B2 (en) * 2003-09-26 2006-10-10 Flipchip International, Llc Forming partial-depth features in polymer film
US6949802B2 (en) * 2003-11-20 2005-09-27 Taiwan Semiconductor Manufacturing Co., Ltd. ESD protection structure
US7316063B2 (en) * 2004-01-12 2008-01-08 Micron Technology, Inc. Methods of fabricating substrates including at least one conductive via
US7235489B2 (en) * 2004-05-21 2007-06-26 Agere Systems Inc. Device and method to eliminate shorting induced by via to metal misalignment
US7199050B2 (en) * 2004-08-24 2007-04-03 Micron Technology, Inc. Pass through via technology for use during the manufacture of a semiconductor device
US7419852B2 (en) * 2004-08-27 2008-09-02 Micron Technology, Inc. Low temperature methods of forming back side redistribution layers in association with through wafer interconnects, semiconductor devices including same, and assemblies
US8288828B2 (en) * 2004-09-09 2012-10-16 International Business Machines Corporation Via contact structure having dual silicide layers
US7387855B2 (en) * 2005-01-10 2008-06-17 Taiwan Semiconductor Manufacturing Co., Ltd Anti-ESD photomask blank
US7323784B2 (en) * 2005-03-17 2008-01-29 Taiwan Semiconductor Manufacturing Co., Ltd. Top via pattern for bond pad structure
US7371676B2 (en) * 2005-04-08 2008-05-13 Micron Technology, Inc. Method for fabricating semiconductor components with through wire interconnects
US7215032B2 (en) * 2005-06-14 2007-05-08 Cubic Wafer, Inc. Triaxial through-chip connection
US8154131B2 (en) * 2005-06-14 2012-04-10 Cufer Asset Ltd. L.L.C. Profiled contact
US20070045812A1 (en) * 2005-08-31 2007-03-01 Micron Technology, Inc. Microfeature assemblies including interconnect structures and methods for forming such interconnect structures
US7772115B2 (en) * 2005-09-01 2010-08-10 Micron Technology, Inc. Methods for forming through-wafer interconnects, intermediate structures so formed, and devices and systems having at least one solder dam structure
US7288757B2 (en) * 2005-09-01 2007-10-30 Micron Technology, Inc. Microelectronic imaging devices and associated methods for attaching transmissive elements
US7393758B2 (en) * 2005-11-03 2008-07-01 Maxim Integrated Products, Inc. Wafer level packaging process
US7417321B2 (en) * 2005-12-30 2008-08-26 Taiwan Semiconductor Manufacturing Co., Ltd Via structure and process for forming the same
US7671460B2 (en) * 2006-01-25 2010-03-02 Teledyne Licensing, Llc Buried via technology for three dimensional integrated circuits
US7453154B2 (en) * 2006-03-29 2008-11-18 Delphi Technologies, Inc. Carbon nanotube via interconnect

Patent Citations (101)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6180518B2 (en) *
US6184465B2 (en) *
US5496755A (en) * 1989-11-29 1996-03-05 Texas Instruments Incorporated Integrated circuit and method
US6020624A (en) * 1991-06-04 2000-02-01 Micron Technology, Inc. Semiconductor package with bi-substrate die
US5485039A (en) * 1991-12-27 1996-01-16 Hitachi, Ltd. Semiconductor substrate having wiring conductors at a first main surface electrically connected to plural pins at a second main surface
US5481483A (en) * 1992-11-23 1996-01-02 Ford Motor Company Non-contact method of obtaining dimensional information about an object for comparing similar objects
US5723904A (en) * 1993-03-10 1998-03-03 Sumitomo Electric Industries, Ltd. Packaged semiconductor device suitable to be mounted and connected to microstrip line structure board
US6203539B1 (en) * 1993-05-07 2001-03-20 Visx, Incorporated Method and system for laser treatment of refractive errors using offset imaging
US5593913A (en) * 1993-09-28 1997-01-14 Sharp Kabushiki Kaisha Method of manufacturing solid state imaging device having high sensitivity and exhibiting high degree of light utilization
US5593927A (en) * 1993-10-14 1997-01-14 Micron Technology, Inc. Method for packaging semiconductor dice
US5734555A (en) * 1994-03-30 1998-03-31 Intel Corporation Shared socket multi-chip module and/or piggyback pin grid array package
US5726493A (en) * 1994-06-13 1998-03-10 Fujitsu Limited Semiconductor device and semiconductor device unit having ball-grid-array type package structure
US5614743A (en) * 1994-07-26 1997-03-25 Kabushiki Kaisha Toshiba Microwave integrated circuit (MIC) having a reactance element formed on a groove
US5870289A (en) * 1994-12-15 1999-02-09 Hitachi, Ltd. Chip connection structure having diret through-hole connections through adhesive film and wiring substrate
US5605783A (en) * 1995-01-06 1997-02-25 Eastman Kodak Company Pattern transfer techniques for fabrication of lenslet arrays for solid state imagers
US5718791A (en) * 1995-06-05 1998-02-17 R + S Stanztechnik Gmbh Method of laminating a trim panel and folding a cover sheet edge around the panel rim
US5877040A (en) * 1995-08-10 1999-03-02 Lg Semicon Co., Ltd. Method of making charge-coupled device with microlens
US5861654A (en) * 1995-11-28 1999-01-19 Eastman Kodak Company Image sensor assembly
US6201304B1 (en) * 1995-12-19 2001-03-13 Micron Technology, Inc. Flip chip adaptor package for bare die
US5708293A (en) * 1996-01-05 1998-01-13 Matsushita Electronics Corporation Lead frame and method of mounting semiconductor chip
US5857963A (en) * 1996-07-17 1999-01-12 Welch Allyn, Inc. Tab imager assembly for use in an endoscope
US6184060B1 (en) * 1996-10-29 2001-02-06 Trusi Technologies Llc Integrated circuits and methods for their fabrication
US5870823A (en) * 1996-11-27 1999-02-16 International Business Machines Corporation Method of forming a multilayer electronic packaging substrate with integral cooling channels
US6188232B1 (en) * 1996-12-31 2001-02-13 Micron Technology, Inc. Temporary package, system, and method for testing semiconductor dice and chip scale packages
US6344976B1 (en) * 1997-04-07 2002-02-05 Micron Technology, Inc. Interdigitated leads-over-chip lead frame device and method for supporting an integrated circuit die
US6844978B2 (en) * 1997-10-03 2005-01-18 Digital Optics Corp. Wafer level creation of multiple optical elements
US6018249A (en) * 1997-12-11 2000-01-25 Micron Technolgoy, Inc. Test system with mechanical alignment for semiconductor chip scale packages and dice
US6191487B1 (en) * 1998-04-23 2001-02-20 Minco Technology Labs, Inc. Semiconductor and flip chip packages and method having a back-side connection
US6187615B1 (en) * 1998-08-28 2001-02-13 Samsung Electronics Co., Ltd. Chip scale packages and methods for manufacturing the chip scale packages at wafer level
US6184465B1 (en) * 1998-11-12 2001-02-06 Micron Technology, Inc. Semiconductor package
US6521530B2 (en) * 1998-11-13 2003-02-18 Fujitsu Limited Composite interposer and method for producing a composite interposer
US6359328B1 (en) * 1998-12-31 2002-03-19 Intel Corporation Methods for making interconnects and diffusion barriers in integrated circuits
US6534192B1 (en) * 1999-09-24 2003-03-18 Lucent Technologies Inc. Multi-purpose finish for printed wiring boards and method of manufacture of such boards
US6359254B1 (en) * 1999-09-30 2002-03-19 United Technologies Corporation Method for producing shaped hole in a structure
US20030014895A1 (en) * 1999-10-08 2003-01-23 Lizotte Todd E. Control system for ablating high-density array of vias or indentation in surface of object
US6180518B1 (en) * 1999-10-29 2001-01-30 Lucent Technologies Inc. Method for forming vias in a low dielectric constant material
US6852621B2 (en) * 2000-01-21 2005-02-08 Seiko Epson Corporation Semiconductor device and manufacturing method therefor, circuit board, and electronic equipment
US6341009B1 (en) * 2000-02-24 2002-01-22 Quantronix Corporation Laser delivery system and method for photolithographic mask repair
US6351027B1 (en) * 2000-02-29 2002-02-26 Agilent Technologies, Inc. Chip-mounted enclosure
US20020006687A1 (en) * 2000-05-23 2002-01-17 Lam Ken M. Integrated IC chip package for electronic image sensor die
US20020005583A1 (en) * 2000-06-07 2002-01-17 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and fabrication process therefor
US6503780B1 (en) * 2000-07-05 2003-01-07 Amkor Technology, Inc. Wafer scale image sensor package fabrication method
US20020020898A1 (en) * 2000-08-16 2002-02-21 Vu Quat T. Microelectronic substrates with integrated devices
US6708405B2 (en) * 2000-08-28 2004-03-23 Infineon Technologies Ag Method for producing an electrically conducting connection
US20030042564A1 (en) * 2000-12-04 2003-03-06 Fujitsu Limited Semiconductor device having an interconnecting post formed on an interposer within a sealing resin
US6686588B1 (en) * 2001-01-16 2004-02-03 Amkor Technology, Inc. Optical module with lens integral holder
US6534863B2 (en) * 2001-02-09 2003-03-18 International Business Machines Corporation Common ball-limiting metallurgy for I/O sites
US6838377B2 (en) * 2001-03-05 2005-01-04 Murata Manufacturing Co., Ltd. High frequency circuit chip and method of producing the same
US20040012698A1 (en) * 2001-03-05 2004-01-22 Yasuo Suda Image pickup model and image pickup device
US20040023469A1 (en) * 2001-03-21 2004-02-05 Canon Kabushiki Kaisha Semiconductor device and its manufacture method
US6703310B2 (en) * 2001-06-14 2004-03-09 Shinko Electric Industries Co., Ltd. Semiconductor device and method of production of same
US6699787B2 (en) * 2001-06-14 2004-03-02 Shinko Electric Industries Co., Ltd. Semiconductor device and method of production of same
US6680459B2 (en) * 2001-06-22 2004-01-20 Nippei Toyama Corporation Laser beam machining apparatus and laser beam machining method
US20020027293A1 (en) * 2001-06-28 2002-03-07 Fujitsu Limited Three dimensional semiconductor integrated circuit device and method for making the same
US6521516B2 (en) * 2001-06-29 2003-02-18 Intel Corporation Process for local on-chip cooling of semiconductor devices using buried microchannels
US6856023B2 (en) * 2002-01-22 2005-02-15 Canon Kabushiki Kaisha Semiconductor device and method of manufacturing semiconductor device
US20070020805A1 (en) * 2002-02-20 2007-01-25 Kim Sarah E Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack
US6858891B2 (en) * 2002-03-06 2005-02-22 Micron Technology, Inc. Nanotube semiconductor devices and methods for making the same
US6841849B2 (en) * 2002-03-19 2005-01-11 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board and electronic instrument
US7166247B2 (en) * 2002-06-24 2007-01-23 Micron Technology, Inc. Foamed mechanical planarization pads made with supercritical fluid
US20040004280A1 (en) * 2002-07-04 2004-01-08 Manabu Shibata Semiconductor device and system having semiconductor device mounted thereon
US20040018712A1 (en) * 2002-07-29 2004-01-29 Plas Hubert Vander Method of forming a through-substrate interconnect
US20040023447A1 (en) * 2002-08-02 2004-02-05 Semiconductor Energy Laboratory Co., Ltd. Organic thin film transistor and method of manufacturing the same, and semiconductor device having the organic thin film transistor
US20040046251A1 (en) * 2002-08-20 2004-03-11 Seung-Whan Lee Semiconductor contact structure and method of forming the same
US20040038442A1 (en) * 2002-08-26 2004-02-26 Kinsman Larry D. Optically interactive device packages and methods of assembly
US20040041261A1 (en) * 2002-08-29 2004-03-04 Kinsman Larry D. Flip-chip image sensor packages and methods of fabrication
US20040043607A1 (en) * 2002-08-29 2004-03-04 Farnworth Warren M. Methods for creating electrophoretically insulated vias in semiconductive substrates and resulting structures
US6847109B2 (en) * 2002-09-25 2005-01-25 Samsung Electronics Co., Ltd. Area array semiconductor package and 3-dimensional stack thereof
US7164565B2 (en) * 2002-11-29 2007-01-16 Sigmatel, Inc. ESD protection circuit
US20070042598A1 (en) * 2003-03-04 2007-02-22 Hyun-Mog Park Dielectric with sidewall passivating layer
US6982487B2 (en) * 2003-03-25 2006-01-03 Samsung Electronics Co., Ltd. Wafer level package and multi-package stack
US20050026443A1 (en) * 2003-08-01 2005-02-03 Goo Ju-Seon Method for forming a silicon oxide layer using spin-on glass
US20050037608A1 (en) * 2003-08-13 2005-02-17 Ibm Deep filled vias
US7183653B2 (en) * 2003-12-17 2007-02-27 Intel Corporation Via including multiple electrical paths
US20060003566A1 (en) * 2004-06-30 2006-01-05 Ismail Emesh Methods and apparatuses for semiconductor fabrication utilizing through-wafer interconnects
US20060014313A1 (en) * 2004-07-16 2006-01-19 Hall Frank L Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US20060011809A1 (en) * 2004-07-19 2006-01-19 Farnworth Warren M Microelectronic imagers with optical devices and methods of manufacturing such microelectronic imagers
US20060024856A1 (en) * 2004-07-28 2006-02-02 Derderian James M Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US20060023107A1 (en) * 2004-08-02 2006-02-02 Bolken Todd O Microelectronic imagers with optics supports having threadless interfaces and methods for manufacturing such microelectronic imagers
US20060035402A1 (en) * 2004-08-10 2006-02-16 Street Bret K Microelectronic imaging units and methods of manufacturing microelectronic imaging units
US20060035415A1 (en) * 2004-08-16 2006-02-16 Wood Alan G Frame structure and semiconductor attach process for use therewith for fabrication of image sensor packages and the like, and resulting packages
US20060038272A1 (en) * 2004-08-17 2006-02-23 Texas Instruments Incorporated Stacked wafer scale package
US20060040421A1 (en) * 2004-08-19 2006-02-23 Farnworth Warren M Spacers for packaged microelectronic imagers and methods of making and using spacers for wafer-level packaging of imagers
US20060040428A1 (en) * 2004-08-19 2006-02-23 Johnson Mark S Conductive structures for microfeature devices and methods for fabricating microfeature devices
US20060038183A1 (en) * 2004-08-19 2006-02-23 Oliver Steven D Microelectronic imagers with curved image sensors and methods for manufacturing microelectronic imagers
US7183176B2 (en) * 2004-08-25 2007-02-27 Agency For Science, Technology And Research Method of forming through-wafer interconnects for vertical wafer level packaging
US7491582B2 (en) * 2004-08-31 2009-02-17 Seiko Epson Corporation Method for manufacturing semiconductor device and semiconductor device
US7170183B1 (en) * 2005-05-13 2007-01-30 Amkor Technology, Inc. Wafer level stacked package
US20070035033A1 (en) * 2005-05-26 2007-02-15 Volkan Ozguz Stackable tier structure comprising high density feedthrough
US7317256B2 (en) * 2005-06-01 2008-01-08 Intel Corporation Electronic packaging including die with through silicon via
US20070004079A1 (en) * 2005-06-30 2007-01-04 Geefay Frank S Method for making contact through via contact to an offset contactor inside a cap for the wafer level packaging of FBAR chips
US20070012655A1 (en) * 2005-07-15 2007-01-18 Samsung Electronics Co., Ltd. Micro-package, multi-stack micro-package, and manufacturing method therefor
US20070020935A1 (en) * 2005-07-19 2007-01-25 Taylor Theodore M Process for enhancing solubility and reaction rates in supercritical fluids
US20070023121A1 (en) * 2005-07-29 2007-02-01 Freescale Semiconductor, Inc. Fabrication of three dimensional integrated circuit employing multiple die panels
US20070032061A1 (en) * 2005-08-05 2007-02-08 Farnworth Warren M Methods of forming through-wafer interconnects and structures resulting therefrom
US20070037379A1 (en) * 2005-08-11 2007-02-15 Ziptronix 3D IC method and device
US20080006850A1 (en) * 2006-07-10 2008-01-10 Innovative Micro Technology System and method for forming through wafer vias using reverse pulse plating
US20080050911A1 (en) * 2006-08-28 2008-02-28 Micron Technology, Inc. Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods
US20080050904A1 (en) * 2006-08-28 2008-02-28 Micron Technology, Inc. Methods for attaching microfeature dies to external devices
US20090007934A1 (en) * 2007-07-06 2009-01-08 Micron Technology, Inc. Systems and methods for exposing semiconductor workpieces to vapors for through-hole cleaning and/or other processes
US20090014859A1 (en) * 2007-07-12 2009-01-15 Micron Technology, Inc. Interconnects for packaged semiconductor devices and methods for manufacturing such devices

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US7622377B2 (en) 2009-11-24 grant
US20070045826A1 (en) 2007-03-01 application

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