US20090278179A1 - Chip scale surface mount package for semiconductor device and process of fabricating the same - Google Patents
Chip scale surface mount package for semiconductor device and process of fabricating the same Download PDFInfo
- Publication number
- US20090278179A1 US20090278179A1 US12/505,762 US50576209A US2009278179A1 US 20090278179 A1 US20090278179 A1 US 20090278179A1 US 50576209 A US50576209 A US 50576209A US 2009278179 A1 US2009278179 A1 US 2009278179A1
- Authority
- US
- United States
- Prior art keywords
- die
- metal layer
- package
- contact
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 101
- 239000002184 metal Substances 0.000 claims abstract description 101
- 229910000679 solder Inorganic materials 0.000 claims description 26
- 238000002161 passivation Methods 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 19
- 229920001940 conductive polymer Polymers 0.000 claims description 6
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 14
- 229910052759 nickel Inorganic materials 0.000 description 7
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229920002120 photoresistant polymer Polymers 0.000 description 6
- 229910052709 silver Inorganic materials 0.000 description 6
- 239000004332 silver Substances 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 238000007772 electroless plating Methods 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 3
- 239000002775 capsule Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 239000004568 cement Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000007650 screen-printing Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000001746 injection moulding Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000004634 thermosetting polymer Substances 0.000 description 1
- NWONKYPBYAMBJT-UHFFFAOYSA-L zinc sulfate Chemical compound [Zn+2].[O-]S([O-])(=O)=O NWONKYPBYAMBJT-UHFFFAOYSA-L 0.000 description 1
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Abstract
A semiconductor package has contacts on both sides of the dice on a wafer scale. The back side of the wafer is attached to a metal plate. The scribe lines separating the dice expose the metal plate without extending through the metal plate. A metal layer may be formed on the front side of the dice, covering the exposed portions of the metal plate and extending to side edges of the dice. The metal layer may cover connection pads on the front side of the dice. A second set of scribe lines are made coincident with the first set. Therefore, the metal layer remains on the side edges of the dice coupling the front and the back. As a result, the package is rugged and provides a low-resistance electrical connection between the back and front sides of the dice.
Description
- This application is a continuation of and claims benefit and priority of a co-pending application Ser. No. 11/786,328, filed on Apr. 10, 2007, which is a Continuation of application Ser. No. 11/082,080, filed on Mar. 15, 2005 and issued as U.S. Pat. No. 7,211,877, which is a Continuation of application Ser. No. 10/157,584 filed on May 28, 2002 and issued as U.S. Pat. No. 6,876,061, which is a Continuation of application Ser. No. 09/395,097 filed on Sep. 13, 1999, which are all herein incorporated by reference in their entirety. Moreover, this application is related to application Ser. No. 09/844,934, filed on Apr. 26, 2001 and issued as U.S. Pat. No. 6,562,647, which is a divisional of application Ser. No. 09/395,097 filed on Sep. 13, 1999 and which is herein incorporated by reference in its entirety. Furthermore, this application is related to application Ser. No. 09/395,095, filed Sep. 13, 1999 and issued as U.S. Pat. No. 6,271,060, and application Ser. No. 09/395,094, filed Sep. 13, 1999 and issued as U.S. Pat. No. 6,316,287, which are herein incorporated by reference in their entirety.
- After the processing of a semiconductor wafer has been completed, the resulting integrated circuit (IC) chips or dice must be separated and packaged in such a way that they can be connected to external circuitry. There are many known packaging techniques. Most involve mounting the die on a leadframe, connecting the die pads to the leadframe by wire-bonding or otherwise, and then encapsulating the die and wire bonds in a plastic capsule, with the leadframe left protruding from the capsule. The encapsulation is often done by injection-molding. The leadframe is then trimmed to remove the tie bars that hold it together, and the leads are bent in such a way that the package can be mounted on a flat surface, typically a printed circuit board (PCB).
- This is generally an expensive, time-consuming process, and the resulting semiconductor package is considerably larger than the die itself using up an undue amount of scarce “real estate” on the PCB. In addition, wire bonds are fragile and introduce a considerable resistance between the die pads and the leads of the package.
- The problems are particularly difficult when the device to be packaged is a “vertical” device, having terminals on opposite faces of the die. For example, a power MOSFET typically has its source and gate terminals on the front side of the die and its drain terminal on the back side of the die. Similarly, a vertical diode has its anode terminal on one face of the die and its cathode terminal on the opposite face of the die. Bipolar transistors, junction field effect transistors (JFETs), and various types of integrated circuits (ICs) can also be fabricated in a “vertical” configuration.
- Accordingly, there is a need for a process which is simpler and less expensive than existing processes and which produces a package that is essentially the same size as the die. There is a particular need for such a process and package that can be used with semiconductor dice having terminals on both their front and back sides.
- The process of fabricating a semiconductor device package in accordance with this invention begins with a semiconductor wafer having a front side and a back side and comprising a plurality of dice separated by scribe lines. Each die comprises a semiconductor device. A surface of the front side of each die comprises a passivation layer and at least one connection pad in electrical contact with a terminal of the semiconductor device. The back side of each die may also be in electrical contact with a terminal of the semiconductor device.
- The process comprises the following steps: attaching a conductive substrate to a back side of the wafer; cutting through the wafer along a scribe line to form a first cut, the first cut exposing the conductive substrate and a side edge of a die, a kerf of the first cut having a first width W1; forming a metal layer which extends from the portion of the conductive substrate exposed by the first cut, along the side edge of the die, and onto at least a portion of the passivation layer; cutting through the conductive substrate along a line that corresponds to the scribe line to form a second cut, a kerf of the second cut having a second width W2 that is smaller than the first width W1 such that at least a portion of the metal layer remains on the side edge of the die and forms a part of a conductive path between the conductive substrate and a location on the front side of the die.
- The process may also include forming at least one additional metal layer in electrical contact with the at least one connection pad. Forming the metal layer may include depositing several sublayers.
- Forming the metal layer may comprise, for example, depositing a metal sublayer on the front side of the die, the side edge of the dice and the exposed portion of the conductive substrate; depositing a mask layer; patterning the mask layer; removing a portion of the mask layer so as to form an opening that exposes a first portion of the metal sublayer, a remaining portion of the mask layer covering a second portion of the metal sublayer, the second portion of the metal sublayer being in contact with the conductive substrate and the side edge of the die; removing the first portion of the metal sublayer; and removing the remaining portion of the mask layer.
- This invention also includes a process for making an electrical connection between a first side of a semiconductor die and a location on a second side of the semiconductor die, the process commencing while the die is a part of a semiconductor wafer. The process comprises attaching a conductive substrate to the first side of the wafer; cutting through the semiconductor wafer from the second side of the wafer to expose a part of the conductive substrate; forming a metal layer extending laterally from the location on the second side of the die along an edge of the die to the exposed part of the conductive substrate; and cutting through the conductive substrate while leaving intact a region of contact between the metal layer and the conductive substrate.
- According to another aspect, this invention includes a package for a semiconductor device comprising: a die containing a semiconductor device, a front side of the die comprising a passivation layer and a connection pad, the connection pad being in electrical contact with the semiconductor device; a conductive plate attached to a back side of the die, the conductive plate extending beyond a side edge of the die to form a protruding portion of the conductive plate; and a metal layer extending from the protruding portion of the conductive plate, along the side edge of the die and onto the passivation layer, the metal layer being electrically insulated from the connection pad.
- According to yet another aspect, this invention also includes a semiconductor structure comprising a conductive substrate; a plurality of semiconductor dice attached to the substrate, rows of the dice being separated from each other by a plurality of parallel trenches, a passivation layer on a front side of each die; and a metal layer lining the bottoms and walls of the trenches and extending onto the passivation layer
- Semiconductor packages according to this invention do not require an epoxy capsule or bond wires; the substrate attached to the die serves to protect the die and act as a heat sink for the die; the packages are very small (e.g., 50% the size of molded packages) and thin; they provide a very low on-resistance for the semiconductor device, particularly if the wafer is ground thinner; they are economical to produce, since they require no molds or lead frames; and they can be used for a wide variety of semiconductor devices such as diodes, MOSFETs, JFETs, bipolar transistors and various types of integrated circuit chips.
- The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
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FIG. 1 shows an exemplary a top view of a semiconductor wafer in accordance with one embodiment of the present invention. -
FIGS. 2A-2B , 3, 4, 5, and 6A-6B through 12A-12B show exemplary steps of a process for fabricating a semiconductor package in accordance with one embodiment of the present invention. -
FIG. 13A shows an exemplary a bottom view of a semiconductor package in accordance with one embodiment of the present invention. -
FIG. 13B shows an exemplary a cross-sectional view of the semiconductor package in accordance with one embodiment of the present invention. -
FIG. 14 shows an exemplary cross-sectional view of a semiconductor package with electrical connections between the package and a printed circuit board in accordance with one embodiment of the present invention. - Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with these embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be evident to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the invention.
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FIG. 1 shows a top view of asemiconductor wafer 100 which containsdice scribe lines 108 running in the Y direction and scribelines 110 running in the X direction. Metal pads for connecting to external circuit elements are located on the top surface of each of thedice 100A-100N. For example, sincedice 100A-100N contain vertical power MOSFETs, each die has asource connection pad 106S and agate connection pad 106G. -
Wafer 100 typically has a thickness in the range of 15-30 mils.Wafer 100 is typically silicon but it could also be another semiconductor material such as silicon carbide or gallium arsenide. - As described above, before
dice 100A-100N can be used they must be packaged in a form that allows them to be connected to external circuitry. - The process of this invention is illustrated in
FIGS. 2A-2B , 3, 4, 5, and 6A-6B through 12A-12B, which show twodice semiconductor wafer 100. While only two dice are shown for purposes of explanation, it will be understood thatwafer 100 would typically include hundreds or thousands of dice. - In each drawing where applicable, the figure labeled “A” is a top or bottom view of the wafer; the figure labeled “B” is an enlarged cross-sectional view taken at the section labeled “B-B” in the “A” figure. As described below, in the course of the process the wafer is attached to a conductive plate, the back side of the wafer facing the conductive plate. In the finished package the wafer is normally positioned under the conductive plate, although at some points in the process the structure may be inverted, with the conductive plate under the wafer. Unless the context clearly indicates otherwise, as used herein “above”, “below”, “over”, “under” and other similar terms refer to the package in its finished form with the conductive plate above the wafer.
- This invention will be described with respect to a package for a vertical power MOSFET, which typically has source and gate terminals on its front side and a drain terminal on its back side. It should be understood, however, that the broad principles of this invention can be used to fabricate a package for any type of semiconductor die which has one or more terminals on both its front and back sides or on its front side alone. As used herein, the “front side” of a die or wafer refers to the side of the die or wafer on which the electrical devices and/or a majority of the connection pads are located; “back side” refers to the opposite side of the die or wafer. The directional arrow labeled “Z”points to the front side of the wafer and identifies the drawings in which the wafer is inverted.
- Referring to
FIGS. 2A-2B , sincedice gate metal layer 102G and asource metal layer 102S overlying the top surface of the silicon or other semiconductor material.Gate metal layer 102G andsource metal layer 102S are in electrical contact with the gate and source terminals (not shown), respectively, of the power MOSFETs withindice FIG. 2A , the separation betweenlayers - Typically,
metal layers metal layers - In one
embodiment metal layers - A
passivation layer 104 overlies a portion ofgate metal layer 102G andsource metal layer 102S.Passivation layer 104 can be formed of phosphosilicate glass (PSG) 1 μm thick, for example, or polyimide or nitride. Openings inpassivation layer 104 define agate connection pad 106G andsource connection pads 106S. -
Dice scribe line 108, which can be 6 mils wide.X-scribe lines 110 perpendicular toscribe line 108 at the top and bottom ofdice -
Wafer 100 can initially be ground from itsbackside 112 to a thickness T (about 8 mils, for example), as shown inFIG. 3 . The grinding may be performed using a grinding machine available from Strausbaugh. During the grinding the front side ofwafer 100 is typically taped. Grinding reduces the resistance to current flow from the front side to the back side of the wafer. - As an alternative to grinding,
wafer 100 can be thinned by lapping or etching the back side of the wafer. - As shown in
FIG. 4 , ametal layer 114 is then formed on thebackside 112 ofwafer 100. For example,metal layer 114 can include a 500 Å titanium sublayer overlain by a 3,000 Å nickel sublayer and a 1 μm silver sublayer. The titanium, nickel and silver sublayers can be deposited by evaporation or sputtering.Metal layer 114 is used to provide good adhesion to the silver-filled epoxy, described below. - Next, as shown in
FIG. 5 , ametal plate 116 is attached tometal layer 114 and the backside of thewafer 100, using alayer 115 of a conductive cement such as conductive silver-filled epoxy or metallic cement.Metal plate 116 can be copper or aluminum and can be 6 mils thick, for example. - As shown in
FIGS. 6A-6B ,wafer 100 is cut, using a conventional dicing saw, along the Y-scribe line 108. In this case the kerf W1 of the cut is the same as the width of the scribe line (6 mils). The cut is made just deep enough to expose asurface 118 of themetal plate 116 as well as side edges 120 of thedice X-scribe lines 110 at this point in the process. - A 500 Å titanium sublayer 122 is then sputtered on the front side of
wafer 100, covering thepassivation layer 104, theconnection pads surface 118 ofmetal plate 116, and the side edges 120 ofdice FIGS. 7A-7B . - Next a
photoresist mask layer 124 is deposited over sublayers 122 and 123.Photoresist mask layer 124 is patterned, using conventional photolithographic methods, and a portion oflayer 124 is removed, yielding the pattern shown inFIGS. 8A-8B . As shown, the portions ofphotoresist layer 124 that remain cover theconnection pads 106G and 100S, thesurface 118 ofmetal plate 116, the side edges 120 ofdice passivation layer 104 adjacent the side edges 120 ofdice Photoresist layer 124 is also left in place over a portion ofpassivation layer 104. - Sublayers 122 and 123 are then etched through the openings in
photoresist layer 124, using a wet chemical etchant. The remaining portions ofphotoresist layer 124 are stripped. In the resulting structure, shown inFIGS. 9A-9B , portions of sublayers 122 and 123 remain on theconnection pads surface 118 ofmetal plate 116, up the side edges 120 ofdice passivation layer 104.Portions - A nickel sublayer 126, for example 10 μm thick, is then deposited on the remaining portions of sputtered aluminum sublayer 123, preferably by electroless plating. A gold sublayer 127, which can be 0.1 μm thick, is then electrolessly plated onto nickel sublayer 126. The resulting structure is illustrated in
FIGS. 10A-10B . Sublayers 126, 127 are divided intoportions portions source pads 106S; portions 126G, 127G which overlie portions 122G, 123G and are in electrical contact with thegate pads 106G; andportions portions Portions - As shown in
FIGS. 10A-10B , sublayers 122, 123, 126 and 127 together form ametal layer 129. As will be apparent to those skilled in the art, in other embodiments,metal layer 129 can contain fewer or more than four sublayers. Moreover,metal layer 129 can contain fewer or more than two sputtered layers and fewer or more than two plated layers. The sublayers may also be deposited by other processes such as evaporation, electroless or electrolytic plating, stencil-printing or screen-printing. Sublayers 122, 123, 126 and 127 are sometimes referred to herein collectively asmetal layer 129. - At this stage of the process there exists semiconductor structure comprising a conductive substrate, represented by
metal plate 116; a plurality ofsemiconductor dice 100A-100N attached to the substrate. Rows of the dice are separated from each other by parallel trenches, the trenches being represented by the cuts extending through thewafer 100, a front side of each die comprising apassivation layer 104; and ametal layer 129 lining the bottoms and walls of the trenches and extending onto the passivation layers. - Optionally, a
layer 130 of solder paste is then stencil or screen printed on at least a portion of the horizontal surfaces ofmetal layer 129. The solder paste is reflowed to produce the gate solder posts 128G, the source solder posts 128S and thedrain solder posts 128D shown inFIGS. 11A-11B . Solder posts 128G, 128S and 128D are electrically insulated from each other. - As shown in
FIGS. 12A-12B ,dice metal plate 116 in the Y-direction. The saw blade is selected such that the kerf W2 of the cut is less than kerf WI of the cut that was previously made to separatedice metal layer 129 that extends up the side edges 120 ofdice metal plate 116 and thedrain solder posts 128D. -
Dice wafer 100 andmetal plate 116 along theX-scribe lines 110, using a dicing saw. Alternatively,dice - A bottom view of the resulting
semiconductor device package 140 is shown inFIG. 13A , and a cross-sectional view ofpackage 140 is shown inFIG. 13B .Package 140 comprises die 100A, which has been inverted as compared withFIG. 12B . A front side ofdie 100A comprisesconnection pad 106S in electrical contact with the semiconductor device (e.g., a MOSFET) withindie 100A andpassivation layer 104.Package 140 also includesconductive plate 116, a back side of die 10A being attached toconductive plate 116.Conductive plate 116 has a width X2 greater than a width X1 ofdie 100A such thatconductive plate 116 extends beyond aside edge 120 of the die 10A to form an protrudingportion 142 ofconductive plate 116. A flange portion ofmetal layer 144 is in contact with the protrudingportion 142 of theconductive plate 116, andmetal layer 144 extends from the protrudingportion 142, along theside edge 120 of thedie 100A and onto thepassivation layer 104. Themetal layer 144 is in electrical contact with the drain terminal of the MOSFET but is electrically insulated fromsource connection pads 102S andgate connection pads 102G. Asecond metal layer 146 is in electrical contact withsource connection pads 102S but electrically insulated fromgate connection pads 102G and the drain terminal of the MOSFET and athird metal layer 148 is in electrical contact withgate connection pads 102G but electrically insulated fromsource connection pads 102S and the drain terminal of the MOSFET. -
Package 140 can easily be mounted on, for example, a PCB usingsolder posts Solder post 128G is not shown inFIG. 13B but it too would be connected to the PCB so that the source, gate, and drain terminals of the MOSFET would be connected to the external circuitry. The drain terminal is on the back side ofdie 100A and is electrically connected viaconductive plate 116. Package 140 contains no wire bonds and, as has been shown, can be manufactured in a batch process using the entire wafer. -
FIG. 14 shows a cross-sectional view of apackage 150 which is similar topackage 140, except thatsolder balls FIG. 14 ) are used in place ofsolder posts - In the foregoing specification, embodiments of the invention have been described with reference to numerous specific details that may vary from implementation to implementation. Thus, the sole and exclusive indicator of what is, and is intended by the applicants to be, the invention is the set of claims that issue from this application, in the specific form in which such claims issue, including any subsequent correction. Hence, no limitation, element, property, feature, advantage or attribute that is not expressly recited in a claim should limit the scope of such claim in any way. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Claims (20)
1. A package for a semiconductor device comprising:
a die containing a semiconductor device, a front side of the die comprising a passivation layer and at least one connection pad, the connection pad being in electrical contact with the semiconductor device;
a conductive plate attached to a back side of the die, the conductive plate extending beyond a side edge of the die to form a protruding portion of the conductive plate; and
a metal layer extending from the protruding portion of the conductive plate, along the side edge of the die and onto the passivation layer, the metal layer being electrically insulated from the connection pad.
2. The package of claim 1 comprising a second metal layer in electrical contact with the connection pad.
3. The package of claim 1 wherein the metal layer comprises at least two metal sublayers, second metal sublayer overlying a first metal sublayer.
4. The package of claim 3 wherein the first metal sublayer is sputtered and the second metal sublayer is plated.
5. The package of claim 2 comprising at least a first solder post in contact with the metal layer and at least a second solder post in contact with the second metal layer.
6. The package of claim 2 comprising at least a first solder ball in contact with the metal layer and at least a second solder ball in contact with the second metal layer.
7. The package of claim 2 comprising at least a first conductive polymer ball in contact with the metal layer and at least a second conductive polymer ball in contact with the second metal layer.
8. The package of claim 1 wherein the conductive plate has a width X2 greater than a width X1 of the die.
9. The package of claim 1 wherein the die comprises a vertical power MOSFET.
10. The package of claim 1 wherein the die comprises a diode.
11. The package of claim 1 wherein the die comprises a bipolar transistor.
12. The package of claim 1 wherein the die comprises a JFET.
13. The package of claim 1 wherein the die comprises a IC.
14. A package for a MOSFET comprising:
a semiconductor die containing a MOSFET and having a width X2, a front side of the die comprising a source connection pad in electrical contact with a source terminal and a gate connection pad in electrical contact with a gate terminal, a back side of the die comprising a drain terminal;
a conductive substrate having a width X1 greater than X2 and being attached to the back side of the die and in electrical contact with the drain terminal;
a drain metal layer in contact with a protruding portion of the conductive substrate and extending along an edge of the die and covering a portion of a passivation layer on the front side of the die;
a source metal layer in electrical contact with the source connection pad; and
a gate metal layer in electrical contact with the gate connection pad.
15. The package of claim 14 further comprising at least one solder post in contact with the source metal layer, at least one solder post in contact with the gate metal layer, and at least one solder post in contact with the drain metal layer.
16. The package of claim 14 further comprising at least one solder ball in contact with the source metal layer, at least one solder ball in contact with the gate metal layer, and at least one solder ball in contact with the drain metal layer.
17. The package of claim 14 further comprising at least one conductive polymer ball in contact with the source metal layer, at least one conductive polymer ball in contact with the gate metal layer, and at least one conductive polymer ball in contact with the drain metal layer.
18. A package for a semiconductor device comprising:
a die containing a semiconductor device, a front side of the die comprising a passivation layer and at least one connection pad, the connection pad being in electrical contact with the semiconductor device;
a conductive plate attached to a back side of the die, the conductive plate extending beyond a side edge of the die to form a protruding portion of the conductive plate, wherein the conductive plate has a width X2 greater than a width X1 of the die; and
a metal layer extending from the protruding portion of the conductive plate, along the side edge of the die and onto the passivation layer, the metal layer being electrically insulated from the connection pad, wherein the metal layer comprises at least two metal sublayers, a second metal sublayer overlying a first metal sublayer; and
a second metal layer in electrical contact with the connection pad.
19. The package of claim 18 wherein the first metal sublayer is sputtered and the second metal sublayer is plated.
20. The package of claim 18 wherein the die comprises a vertical power MOSFET.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/505,762 US20090278179A1 (en) | 1999-09-13 | 2009-07-20 | Chip scale surface mount package for semiconductor device and process of fabricating the same |
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US39509799A | 1999-09-13 | 1999-09-13 | |
US10/157,584 US6876061B2 (en) | 1999-09-13 | 2002-05-28 | Chip scale surface mount package for semiconductor device and process of fabricating the same |
US11/082,080 US7211877B1 (en) | 1999-09-13 | 2005-03-15 | Chip scale surface mount package for semiconductor device and process of fabricating the same |
US11/786,328 US7589396B2 (en) | 1999-09-13 | 2007-04-11 | Chip scale surface mount package for semiconductor device and process of fabricating the same |
US12/505,762 US20090278179A1 (en) | 1999-09-13 | 2009-07-20 | Chip scale surface mount package for semiconductor device and process of fabricating the same |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US11/786,328 Continuation US7589396B2 (en) | 1999-09-13 | 2007-04-11 | Chip scale surface mount package for semiconductor device and process of fabricating the same |
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US20090278179A1 true US20090278179A1 (en) | 2009-11-12 |
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US11/082,080 Expired - Lifetime US7211877B1 (en) | 1999-09-13 | 2005-03-15 | Chip scale surface mount package for semiconductor device and process of fabricating the same |
US11/786,328 Expired - Lifetime US7589396B2 (en) | 1999-09-13 | 2007-04-11 | Chip scale surface mount package for semiconductor device and process of fabricating the same |
US12/505,762 Abandoned US20090278179A1 (en) | 1999-09-13 | 2009-07-20 | Chip scale surface mount package for semiconductor device and process of fabricating the same |
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US11/082,080 Expired - Lifetime US7211877B1 (en) | 1999-09-13 | 2005-03-15 | Chip scale surface mount package for semiconductor device and process of fabricating the same |
US11/786,328 Expired - Lifetime US7589396B2 (en) | 1999-09-13 | 2007-04-11 | Chip scale surface mount package for semiconductor device and process of fabricating the same |
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Also Published As
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US7211877B1 (en) | 2007-05-01 |
US7589396B2 (en) | 2009-09-15 |
US20070235774A1 (en) | 2007-10-11 |
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