US20090184632A1 - Thin film transistor, method of fabricating the same and organic light emitting diode display device having the same - Google Patents

Thin film transistor, method of fabricating the same and organic light emitting diode display device having the same Download PDF

Info

Publication number
US20090184632A1
US20090184632A1 US12/320,110 US32011009A US2009184632A1 US 20090184632 A1 US20090184632 A1 US 20090184632A1 US 32011009 A US32011009 A US 32011009A US 2009184632 A1 US2009184632 A1 US 2009184632A1
Authority
US
United States
Prior art keywords
layer
semiconductor layer
substrate
thermal oxide
disposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US12/320,110
Inventor
Moo-Jin Kim
Kyoung-Bo Kim
Ki-Yong Lee
Han-Hee Yoon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Display Co Ltd
Original Assignee
Samsung Mobile Display Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Mobile Display Co Ltd filed Critical Samsung Mobile Display Co Ltd
Assigned to SAMSUNG MOBILE DISPLAY CO., LTD., A CORPORATION CHARTERED IN AND EXISTING UNDER THE LAWS OF THE REPUBLIC OF KOREA reassignment SAMSUNG MOBILE DISPLAY CO., LTD., A CORPORATION CHARTERED IN AND EXISTING UNDER THE LAWS OF THE REPUBLIC OF KOREA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KIM, KYOUNG-BO, KIM, MOO-JIN, LEE, KI-YONG, YOON, HAN-HEE
Publication of US20090184632A1 publication Critical patent/US20090184632A1/en
Priority to US13/100,979 priority Critical patent/US8673697B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate

Definitions

  • the present invention relates to a thin film transistor, a method of fabricating the same and an organic light emitting diode (OLED) display device having the same.
  • a polycrystalline thin film transistor used in a display device is fabricated by depositing amorphous silicon on a transparent substrate formed of glass or quartz, dehydrogenating the amorphous silicon, and crystallizing the amorphous silicon to form a semiconductor layer. After that, a gate insulating layer and a gate electrode are formed on the semiconductor layer, an impurity is injected into the semiconductor layer to form source and drain regions, and an interlayer insulating layer and source and drain electrodes are formed, so that the thin film transistor is completed.
  • channel doping may be further performed.
  • ion-injection for improving electrical characteristics of a region to be a channel i.e., channel doping is performed, and then a gate insulating layer and a gate electrode are formed on the semiconductor layer.
  • a gate insulating layer insulating the semiconductor layer is generally formed of silicon oxide or silicon nitride by chemical vapor deposition (CVD).
  • CVD chemical vapor deposition
  • the layer deposited by CVD has poor quality and uniformity, so that the layer has to be deposited to a thickness of 1000 ⁇ (angstroms) or more.
  • thin film transistors are found in commonly assigned co-pending patent application Ser. No. 11/987,951 filed 6 Dec. 2007 and published on 12 Jun. 2008 having Publication No. 2008/0135893 entitled “Thin Film Transistor, Method of Fabricating the Same, and Display Device Including the Same” to Hye-Hyang Park et al., and commonly assigned co-pending patent application Ser. No. 11/951,525 filed 6 Dec. 2007 and published on 12 Jun. 2008 having Publication No. 2008/0135838 entitled “Thin Film Transistor, Method of Fabricating the Same, and Organic Light Emitting Diode Display Device Including the Same” to Hye-Hyang Park.
  • An aspect of the present invention provides a thin film transistor which is formed in a simpler process and has better electrical characteristics than a conventional art, and a method of fabricating the same.
  • Another aspect of the present invention provides an organic light emitting diode (OLED) display device having the thin film transistor.
  • OLED organic light emitting diode
  • a thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate and including a channel region, and source and drain regions, the channel region being doped with impurities; a thermal oxide layer disposed on the semiconductor layer; a silicon nitride layer disposed on the thermal oxide layer; a gate electrode disposed on the silicon nitride layer and corresponding to a predetermined region of the semiconductor layer; an interlayer insulating layer disposed on the entire surface of the substrate; and source and drain electrodes electrically connected with the semiconductor layer.
  • a method of fabricating a thin film transistor includes: preparing a substrate; forming a polycrystalline silicon layer on the substrate; injecting impurities into the polycrystalline silicon layer for channel doping; patterning the polycrystalline silicon layer and forming a semiconductor layer; annealing the semiconductor layer in an H 2 O atmosphere, and forming a thermal oxide layer on the semiconductor layer; forming a silicon nitride layer on the thermal oxide layer; forming a gate electrode at a location corresponding to a predetermined region of the semiconductor layer; forming an interlayer insulating layer on the entire surface of the substrate; and forming source and drain electrodes electrically connected with the semiconductor layer.
  • an organic light emitting diode (OLED) display device includes: a substrate; a semiconductor layer disposed on the substrate, and including a channel region and source and drain regions, the channel region being doped with impurities; a thermal oxide layer disposed on the semiconductor layer; a silicon nitride layer disposed on the thermal oxide layer; a gate electrode disposed on the silicon nitride layer and corresponding to a predetermined region of the semiconductor layer; an interlayer insulating layer disposed on the entire surface of the substrate; source and drain electrodes electrically connected with the semiconductor layer; a first electrode electrically connected with one of the source and drain electrodes; an organic layer disposed on the first electrode; and a second electrode disposed on the organic layer.
  • FIGS. 1A to 1G are cross-sectional views illustrating a process of fabricating a thin film transistor according to an exemplary embodiment of the present invention.
  • FIG. 1H is a cross-sectional view of an organic light emitting diode (OLED) display device according to an exemplary embodiment of the present invention.
  • OLED organic light emitting diode
  • FIGS. 1A to 1G are cross-sectional views illustrating a process of fabricating a thin film transistor according to an exemplary embodiment of the present invention.
  • a buffer layer 201 may be formed on a substrate 200 , for example, formed of insulating glass or plastic.
  • the buffer layer 201 prevents diffusion of moisture or impurities from the substrate or controls a heat transfer rate during crystallization, so as to facilitate the crystallization of a polycrystalline silicon layer to be formed in a following process.
  • the buffer layer 201 may be formed of silicon oxide, silicon nitride or a combination thereof.
  • an amorphous silicon layer 202 is formed on the buffer layer 201 .
  • the amorphous silicon layer may be deposited by plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD).
  • PECVD plasma enhanced chemical vapor deposition
  • LPCVD low pressure chemical vapor deposition
  • SiH 4 +Ar and/or H 2 at a temperature ranging from 330 to 430° C. and a pressure ranging from 1 to 1.5 Torr.
  • LPCVD is performed using Si 2 H 6 +Ar at a temperature ranging from 400 to 500° C. and a pressure ranging from 0.2 to 0.4 Torr.
  • the amorphous silicon layer 202 is crystallized, thereby forming a polycrystalline silicon layer 202 a.
  • the polycrystalline silicon layer 202 a may be formed by one selected from the group consisting of solid phase crystallization (SPC), sequential lateral solidification (SLS), excimer laser annealing (ELA), metal induced crystallization (MIC), metal induced lateral crystallization (MILC), and super grain silicon crystallization (SGS).
  • SPC solid phase crystallization
  • SLS sequential lateral solidification
  • ELA excimer laser annealing
  • MIC metal induced crystallization
  • MILC metal induced lateral crystallization
  • SGS super grain silicon crystallization
  • impurities e.g., boron (B) or phosphorous (P) ions
  • B boron
  • P phosphorous
  • the channel doping is to form a channel region of a thin film transistor having a predetermined resistance.
  • device's characteristics such as threshold voltage and drain current of the thin film transistor can be controlled by the doped ions.
  • the polycrystalline silicon layer 202 a formed on the substrate 200 is patterned, thereby forming a semiconductor layer 203 .
  • a thermal oxide layer 210 is formed by annealing the semiconductor layer 203 formed of the polycrystalline silicon in an H2O atmosphere.
  • the annealing process uses a common high-temperature annealing technique such as a rapid thermal annealing or furnace technique in an H 2 O atmosphere, but in the conventional art, the annealing process was performed in an N 2 or O 2 atmosphere.
  • the annealing process performed in an H 2 O atmosphere further reduces annealing time at the same temperature, or reduces annealing temperature at the same annealing time as that performed in an N 2 or O 2 atmosphere.
  • the present invention can reduce the annealing temperature as described above, and thus can prevent the bending of the substrate.
  • the annealing temperature may range from 400 to 550° C.
  • the annealing temperature is preferably 400° C. or more, because the amorphous silicon is crystallized at an appropriate temperature, and the annealing temperature is preferably 550° C. or less, because the substrate is deformed at high temperature.
  • a pressure of H 2 O may be in a range from 10000 Pa to 2 MPa.
  • the pressure of H 2 O is preferably 10000 Pa or more, in consideration that the annealing time is determined by a crystallization rate of amorphous silicon, which is proportional to a pressure.
  • the pressure of H 2 O is preferably 2 MPa or less, in consideration that a device can be exploded at high pressure.
  • a thermal oxide layer 210 is formed on the entire surface of the semiconductor layer 203 by thermal oxidation.
  • the thermal oxide layer 210 may be formed to a thickness of 50 to 300 angstroms. That is, the thickness of the thermal oxide layer 210 is preferably 50 angstroms or more, in consideration that the thermal oxide layer 210 serves as a gate insulating layer, and the thickness of the thermal oxide layer 210 is preferably 300 angstroms or less, in consideration of a processing time of the thermal oxide layer 210 . Also, the thickness of the thermal oxide layer 210 may be controlled by the annealing temperature and time.
  • the channel-doped impurity ions are simultaneously activated, and thus the process can be simpler than the conventional art in which a separate annealing process was performed.
  • a silicon nitride layer 211 is formed on the entire surface of the substrate 200 having the thermal oxide layer 210 by CVD. Both the thermal oxide layer 210 and the silicon nitride layer 211 serve as a gate insulating layer.
  • a gate insulating layer is formed of a combination of the thermal oxide layer 210 and the silicon nitride layer 211 .
  • a gate insulating layer is formed of silicon oxide by CVD like the conventional art, it is formed to a thickness of 1000 angstroms or more to prevent deterioration of quality and uniformity of the layer.
  • the thermal oxide layer 210 used as the gate insulating layer is formed to a thickness of 300 angstroms or less, and thus the characteristics of the thin film transistor can be easily controlled. Further, due to the thermal oxide layer 210 used as the gate insulating layer, the characteristics of the thin film transistor can be improved.
  • a metal layer for a gate electrode is formed of a single layer of aluminum (Al) or an aluminum alloy such as aluminum-neodymium (Al—Nd), or a multi layer in which Al or an Al alloy is disposed on chromium (Cr), molybdenum (Mo) or an alloy thereof, on the entire surface of the substrate 200 . Then, the metal layer for a gate electrode is etched, thereby forming a gate electrode 212 in a predetermined region corresponding to the semiconductor layer 203 .
  • conductive impurity ions are injected at a predetermined dose using the gate electrode 212 as a mask, so that source and drain regions 204 and 205 and a channel region 206 are formed.
  • a p-type or n-type impurity can be used.
  • the p-type impurity may be one selected from the group consisting of B, Al, gallium (Ga) and indium (In)
  • the n-type impurity may be one selected from the group consisting of P, arsenic (As) and antimony (Sb).
  • an interlayer insulating layer 213 is formed on the entire surface of the substrate 200 having the gate electrode 212 .
  • Source and drain electrodes 214 and 215 are then formed electrically connected with the source and drain regions 204 and 205 of the semiconductor layer 203 through the contact holes.
  • the thin film transistor of the present invention can be manufactured in a simpler process because the channel-doped impurity ions are simultaneously activated by the annealing process during the formation of the thermal oxide layer, and can have improved characteristics because the thermal oxide layer is used as the gate insulating layer.
  • SiO2 thermal oxide
  • a silicon nitride layer was formed to a thickness of 200 angstroms on the entire surface of the substrate by CVD, and a gate electrode was formed to a thickness of 3000 angstroms by depositing molybdenum (Mo).
  • Source and drain regions were formed by injecting BH3 ions into the entire surface of the substrate at a concentration of 1.0 ⁇ 10 15 /cm 2 and an accelerating voltage of 40 KeV, and an interlayer insulting layer was formed to a thickness of 400 angstroms by CVD.
  • source and drain electrodes were formed to a thickness of 4000 angstroms by depositing Mo to be connected with the source and drain regions of the semiconductor layer, and thus a thin film transistor was completed.
  • Threshold voltage, charge mobility and leakage current of the thin film transistor fabricated according to the above experimental example were measured, and the results are listed in Table 1.
  • FIG. 1H is a cross-sectional view of an organic light emitting diode (OLED) display device according to an exemplary embodiment of the present invention.
  • OLED organic light emitting diode
  • a planarization layer 220 is formed on the entire surface of the substrate 200 .
  • the planarization layer 220 may be formed of an organic layer, an inorganic layer or a combination thereof.
  • the inorganic planarization layer 220 may be formed of spin on glass (SOG), and the organic planarization layer 220 may be formed of acrylic resin, polyimide resin or benzocyclobutene (BCB).
  • the planarization layer 220 is etched, thereby forming a via hole 222 exposing one of the source and drain electrodes 214 and 215 , and forming a first electrode 225 connected with one of the source and drain electrodes 214 and 215 .
  • the first electrode 225 is disposed on a bottom of the via hole 222 to be in contact with the exposed one of the source and drain electrodes 214 and 215 , and extends onto the planarization layer 220 .
  • the first electrode 225 may be formed of indium tin oxide (ITO) or indium zinc oxide (IZO).
  • a pixel defining layer 230 is formed on the entire surface of the substrate 200 having the first electrode 225 , and has a sufficient thickness to completely fill the via hole 222 in which the first electrode 225 is disposed.
  • the pixel defining layer 230 may be formed of an organic or inorganic layer, and preferably an organic layer. More preferably, the pixel defining layer 230 is formed of one selected from the group consisting of BCB, acrylic resin and polyimide.
  • the pixel defining layer 230 can be uniformly formed on the entire surface of the substrate because of good flowability.
  • the pixel defining layer 230 is etched, thereby forming an opening exposing the first electrode 225 , and an organic layer 235 is formed on the first electrode 225 exposed through the opening.
  • the organic layer 235 includes at least an light emitting layer, and may further include at least one of a hole injection layer, a hole transport layer, an electron transport layer and an electron injection layer.
  • the second electrode 240 may be a transmissive electrode, which is transparent and may be formed of Mg, Ag, Al, Ca or an alloy thereof having a low work function.
  • a thin film transistor having improved electrical characteristics can be fabricated in a simpler fabrication process than a conventional art.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

A thin film transistor which has improved characteristics, a method of fabricating the same, and an organic light emitting diode (OLED) display device having the same. The thin film transistor includes a substrate, a semiconductor layer disposed on the substrate and including a channel region, and source and drain regions, the channel region being doped with impurities, a thermal oxide layer disposed on the semiconductor layer, a silicon nitride layer disposed on the thermal oxide layer, a gate electrode disposed on the silicon nitride layer and corresponding to a predetermined region of the semiconductor layer, an interlayer insulating layer disposed on the entire surface of the substrate, and source and drain electrodes electrically connected with the semiconductor layer.

Description

    CROSS-REFERENCE TO RELATED APPLICATIONS
  • This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. §119 from an application earlier filed in the Korean Intellectual Property Office on the 18 Jan. 2008 and there duly assigned Serial No. 10-2008-0005729.
    • BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention relates to a thin film transistor, a method of fabricating the same and an organic light emitting diode (OLED) display device having the same.
  • 2. Description of the Related Art
  • Generally, a polycrystalline thin film transistor used in a display device is fabricated by depositing amorphous silicon on a transparent substrate formed of glass or quartz, dehydrogenating the amorphous silicon, and crystallizing the amorphous silicon to form a semiconductor layer. After that, a gate insulating layer and a gate electrode are formed on the semiconductor layer, an impurity is injected into the semiconductor layer to form source and drain regions, and an interlayer insulating layer and source and drain electrodes are formed, so that the thin film transistor is completed.
  • Alternatively, to improve electrical characteristics of a thin film transistor, channel doping may be further performed. To be more specific, after injecting a predetermined impurity into a semiconductor layer, ion-injection for improving electrical characteristics of a region to be a channel, i.e., channel doping is performed, and then a gate insulating layer and a gate electrode are formed on the semiconductor layer.
  • However, in a common process of fabricating the thin film transistor, an annealing process for activating impurity ions injected into the semiconductor layer has to be performed after the channel doping. Therefore, the process becomes complicated and production yield is lowered.
  • A gate insulating layer insulating the semiconductor layer is generally formed of silicon oxide or silicon nitride by chemical vapor deposition (CVD). However, the layer deposited by CVD has poor quality and uniformity, so that the layer has to be deposited to a thickness of 1000 Å (angstroms) or more.
  • Examples of thin film transistors are found in commonly assigned co-pending patent application Ser. No. 11/987,951 filed 6 Dec. 2007 and published on 12 Jun. 2008 having Publication No. 2008/0135893 entitled “Thin Film Transistor, Method of Fabricating the Same, and Display Device Including the Same” to Hye-Hyang Park et al., and commonly assigned co-pending patent application Ser. No. 11/951,525 filed 6 Dec. 2007 and published on 12 Jun. 2008 having Publication No. 2008/0135838 entitled “Thin Film Transistor, Method of Fabricating the Same, and Organic Light Emitting Diode Display Device Including the Same” to Hye-Hyang Park.
  • For this reason, the electrical characteristics of the thin film transistor are difficult to be controlled, and overall characteristics of the thin film transistor become degraded.
    • SUMMARY OF THE INVENTION
  • An aspect of the present invention provides a thin film transistor which is formed in a simpler process and has better electrical characteristics than a conventional art, and a method of fabricating the same.
  • Another aspect of the present invention provides an organic light emitting diode (OLED) display device having the thin film transistor.
  • According to an embodiment of the present invention, a thin film transistor includes: a substrate; a semiconductor layer disposed on the substrate and including a channel region, and source and drain regions, the channel region being doped with impurities; a thermal oxide layer disposed on the semiconductor layer; a silicon nitride layer disposed on the thermal oxide layer; a gate electrode disposed on the silicon nitride layer and corresponding to a predetermined region of the semiconductor layer; an interlayer insulating layer disposed on the entire surface of the substrate; and source and drain electrodes electrically connected with the semiconductor layer.
  • According to another embodiment of the present invention, a method of fabricating a thin film transistor includes: preparing a substrate; forming a polycrystalline silicon layer on the substrate; injecting impurities into the polycrystalline silicon layer for channel doping; patterning the polycrystalline silicon layer and forming a semiconductor layer; annealing the semiconductor layer in an H2O atmosphere, and forming a thermal oxide layer on the semiconductor layer; forming a silicon nitride layer on the thermal oxide layer; forming a gate electrode at a location corresponding to a predetermined region of the semiconductor layer; forming an interlayer insulating layer on the entire surface of the substrate; and forming source and drain electrodes electrically connected with the semiconductor layer.
  • According to still another embodiment of the present invention, an organic light emitting diode (OLED) display device includes: a substrate; a semiconductor layer disposed on the substrate, and including a channel region and source and drain regions, the channel region being doped with impurities; a thermal oxide layer disposed on the semiconductor layer; a silicon nitride layer disposed on the thermal oxide layer; a gate electrode disposed on the silicon nitride layer and corresponding to a predetermined region of the semiconductor layer; an interlayer insulating layer disposed on the entire surface of the substrate; source and drain electrodes electrically connected with the semiconductor layer; a first electrode electrically connected with one of the source and drain electrodes; an organic layer disposed on the first electrode; and a second electrode disposed on the organic layer.
  • Additional aspects and/or advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • A more complete appreciation of the present invention, and many of the attendant advantages thereof, will be readily apparent as the present invention becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicated the same or similar components, wherein:
  • FIGS. 1A to 1G are cross-sectional views illustrating a process of fabricating a thin film transistor according to an exemplary embodiment of the present invention; and
  • FIG. 1H is a cross-sectional view of an organic light emitting diode (OLED) display device according to an exemplary embodiment of the present invention.
    •  DETAILED DESCRIPTION OF THE INVENTION
  • Reference will now be made in detail to the present embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present invention by referring to the figures.
  • FIGS. 1A to 1G are cross-sectional views illustrating a process of fabricating a thin film transistor according to an exemplary embodiment of the present invention.
  • Referring to FIG. 1A, a buffer layer 201 may be formed on a substrate 200, for example, formed of insulating glass or plastic. The buffer layer 201 prevents diffusion of moisture or impurities from the substrate or controls a heat transfer rate during crystallization, so as to facilitate the crystallization of a polycrystalline silicon layer to be formed in a following process. The buffer layer 201 may be formed of silicon oxide, silicon nitride or a combination thereof.
  • Subsequently, an amorphous silicon layer 202 is formed on the buffer layer 201. Here, the amorphous silicon layer may be deposited by plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD). Here, PECVD is performed using SiH4+Ar and/or H2 at a temperature ranging from 330 to 430° C. and a pressure ranging from 1 to 1.5 Torr. LPCVD is performed using Si2H6+Ar at a temperature ranging from 400 to 500° C. and a pressure ranging from 0.2 to 0.4 Torr.
  • After that, as illustrated in FIG. 1B, the amorphous silicon layer 202 is crystallized, thereby forming a polycrystalline silicon layer 202 a. Here, the polycrystalline silicon layer 202 a may be formed by one selected from the group consisting of solid phase crystallization (SPC), sequential lateral solidification (SLS), excimer laser annealing (ELA), metal induced crystallization (MIC), metal induced lateral crystallization (MILC), and super grain silicon crystallization (SGS).
  • Subsequently, impurities, e.g., boron (B) or phosphorous (P) ions, are injected at a dose of 0.5×1012/cm2 to 1.5×1012/cm2 into the entire surface of the substrate 200 having polycrystalline silicon layer 202 a for channel doping. Here, the channel doping is to form a channel region of a thin film transistor having a predetermined resistance. Thus, device's characteristics such as threshold voltage and drain current of the thin film transistor can be controlled by the doped ions.
  • Subsequently, referring to FIG. 1C, the polycrystalline silicon layer 202 a formed on the substrate 200 is patterned, thereby forming a semiconductor layer 203. Then, a thermal oxide layer 210 is formed by annealing the semiconductor layer 203 formed of the polycrystalline silicon in an H2O atmosphere.
  • In the present invention, the annealing process uses a common high-temperature annealing technique such as a rapid thermal annealing or furnace technique in an H2O atmosphere, but in the conventional art, the annealing process was performed in an N2 or O2 atmosphere.
  • Here, the annealing process performed in an H2O atmosphere further reduces annealing time at the same temperature, or reduces annealing temperature at the same annealing time as that performed in an N2 or O2 atmosphere.
  • Particularly, while a conventional transparent insulating substrate formed of glass is bent at high temperature, the present invention can reduce the annealing temperature as described above, and thus can prevent the bending of the substrate.
  • In the present invention, the annealing temperature may range from 400 to 550° C. Here, the annealing temperature is preferably 400° C. or more, because the amorphous silicon is crystallized at an appropriate temperature, and the annealing temperature is preferably 550° C. or less, because the substrate is deformed at high temperature.
  • In addition, a pressure of H2O may be in a range from 10000 Pa to 2 MPa. Here, the pressure of H2O is preferably 10000 Pa or more, in consideration that the annealing time is determined by a crystallization rate of amorphous silicon, which is proportional to a pressure. Further, the pressure of H2O is preferably 2 MPa or less, in consideration that a device can be exploded at high pressure.
  • Here, when the semiconductor layer 203 is annealed in the H2O atmosphere, a thermal oxide layer 210 is formed on the entire surface of the semiconductor layer 203 by thermal oxidation.
  • Here, the thermal oxide layer 210 may be formed to a thickness of 50 to 300 angstroms. That is, the thickness of the thermal oxide layer 210 is preferably 50 angstroms or more, in consideration that the thermal oxide layer 210 serves as a gate insulating layer, and the thickness of the thermal oxide layer 210 is preferably 300 angstroms or less, in consideration of a processing time of the thermal oxide layer 210. Also, the thickness of the thermal oxide layer 210 may be controlled by the annealing temperature and time.
  • By the annealing process described above, the channel-doped impurity ions are simultaneously activated, and thus the process can be simpler than the conventional art in which a separate annealing process was performed.
  • Subsequently, referring to FIG. 1D, a silicon nitride layer 211 is formed on the entire surface of the substrate 200 having the thermal oxide layer 210 by CVD. Both the thermal oxide layer 210 and the silicon nitride layer 211 serve as a gate insulating layer. In the present invention, a gate insulating layer is formed of a combination of the thermal oxide layer 210 and the silicon nitride layer 211.
  • When a gate insulating layer is formed of silicon oxide by CVD like the conventional art, it is formed to a thickness of 1000 angstroms or more to prevent deterioration of quality and uniformity of the layer. However, in the present invention, the thermal oxide layer 210 used as the gate insulating layer is formed to a thickness of 300 angstroms or less, and thus the characteristics of the thin film transistor can be easily controlled. Further, due to the thermal oxide layer 210 used as the gate insulating layer, the characteristics of the thin film transistor can be improved.
  • Subsequently, referring to FIG. 1E, a metal layer for a gate electrode is formed of a single layer of aluminum (Al) or an aluminum alloy such as aluminum-neodymium (Al—Nd), or a multi layer in which Al or an Al alloy is disposed on chromium (Cr), molybdenum (Mo) or an alloy thereof, on the entire surface of the substrate 200. Then, the metal layer for a gate electrode is etched, thereby forming a gate electrode 212 in a predetermined region corresponding to the semiconductor layer 203.
  • Referring to FIG. 1F, conductive impurity ions are injected at a predetermined dose using the gate electrode 212 as a mask, so that source and drain regions 204 and 205 and a channel region 206 are formed. To form a thin film transistor, a p-type or n-type impurity can be used. Here, the p-type impurity may be one selected from the group consisting of B, Al, gallium (Ga) and indium (In), and the n-type impurity may be one selected from the group consisting of P, arsenic (As) and antimony (Sb).
  • Referring to FIG. 1 G, an interlayer insulating layer 213 is formed on the entire surface of the substrate 200 having the gate electrode 212.
  • Subsequently, predetermined regions of the interlayer insulating layer 213, the silicon nitride layer 211 and the thermal oxide layer 210 are etched, thereby forming contact holes. Source and drain electrodes 214 and 215 are then formed electrically connected with the source and drain regions 204 and 205 of the semiconductor layer 203 through the contact holes. Thus, the thin film transistor according to the exemplary embodiment of the present invention is completed.
  • As described above, the thin film transistor of the present invention can be manufactured in a simpler process because the channel-doped impurity ions are simultaneously activated by the annealing process during the formation of the thermal oxide layer, and can have improved characteristics because the thermal oxide layer is used as the gate insulating layer.
  • Hereinafter, an experimental example will be described to help comprehension of the present invention. However, the experimental example is provided only to comprehend the present invention, which will not be limited thereto.
    • EXPERIMENTAL EXAMPLE
  • A semiconductor layer (W/L=10/10 μm) formed of polycrystalline silicon was formed on a substrate, and channel doping was performed by injecting BH3 ions into the semiconductor layer at a concentration of 1.×1012/cm2 and an accelerating voltage of 17 KeV. Then, the substrate having the semiconductor layer was annealed for 60 minutes at 2 MPa and 550° C. in an H2O atmosphere to activate the channel-doped ions and form a thermal oxide (SiO2) layer having a thickness of 160 Å. After that, a silicon nitride layer was formed to a thickness of 200 angstroms on the entire surface of the substrate by CVD, and a gate electrode was formed to a thickness of 3000 angstroms by depositing molybdenum (Mo). Source and drain regions were formed by injecting BH3 ions into the entire surface of the substrate at a concentration of 1.0×1015/cm2 and an accelerating voltage of 40 KeV, and an interlayer insulting layer was formed to a thickness of 400 angstroms by CVD. Then, source and drain electrodes were formed to a thickness of 4000 angstroms by depositing Mo to be connected with the source and drain regions of the semiconductor layer, and thus a thin film transistor was completed.
  • Threshold voltage, charge mobility and leakage current of the thin film transistor fabricated according to the above experimental example were measured, and the results are listed in Table 1.
  • TABLE 1
    Threshold Charge mobility Leakage current
    voltage (v) (cm2/Vs) (A/m)
    −3.93 27.38 2.58E−13
  • Subsequently, FIG. 1H is a cross-sectional view of an organic light emitting diode (OLED) display device according to an exemplary embodiment of the present invention.
  • Referring to FIG. 1H, a planarization layer 220 is formed on the entire surface of the substrate 200. The planarization layer 220 may be formed of an organic layer, an inorganic layer or a combination thereof. The inorganic planarization layer 220 may be formed of spin on glass (SOG), and the organic planarization layer 220 may be formed of acrylic resin, polyimide resin or benzocyclobutene (BCB).
  • Here, the planarization layer 220 is etched, thereby forming a via hole 222 exposing one of the source and drain electrodes 214 and 215, and forming a first electrode 225 connected with one of the source and drain electrodes 214 and 215. The first electrode 225 is disposed on a bottom of the via hole 222 to be in contact with the exposed one of the source and drain electrodes 214 and 215, and extends onto the planarization layer 220. The first electrode 225 may be formed of indium tin oxide (ITO) or indium zinc oxide (IZO).
  • Subsequently, a pixel defining layer 230 is formed on the entire surface of the substrate 200 having the first electrode 225, and has a sufficient thickness to completely fill the via hole 222 in which the first electrode 225 is disposed. The pixel defining layer 230 may be formed of an organic or inorganic layer, and preferably an organic layer. More preferably, the pixel defining layer 230 is formed of one selected from the group consisting of BCB, acrylic resin and polyimide. The pixel defining layer 230 can be uniformly formed on the entire surface of the substrate because of good flowability.
  • Here, the pixel defining layer 230 is etched, thereby forming an opening exposing the first electrode 225, and an organic layer 235 is formed on the first electrode 225 exposed through the opening. The organic layer 235 includes at least an light emitting layer, and may further include at least one of a hole injection layer, a hole transport layer, an electron transport layer and an electron injection layer.
  • Subsequently, a second electrode 240 is formed on the entire surface of the substrate 200. The second electrode 240 may be a transmissive electrode, which is transparent and may be formed of Mg, Ag, Al, Ca or an alloy thereof having a low work function.
  • Thus, the OLED display device according to the exemplary embodiment of the present invention is completed.
  • According to the present invention, a thin film transistor having improved electrical characteristics can be fabricated in a simpler fabrication process than a conventional art.
  • Although a few embodiments of the present invention have been shown and described, it would be appreciated by those skilled in the art that changes may be made in this embodiment without departing from the principles and spirit of the invention, the scope of which is defined in the claims and their equivalents.

Claims (13)

1. A thin film transistor, comprising:
a substrate;
a semiconductor layer disposed on the substrate and including a channel region, and source and drain regions, the channel region being doped with impurities;
a thermal oxide layer disposed on the semiconductor layer;
a silicon nitride layer disposed on the thermal oxide layer;
a gate electrode disposed on the silicon nitride layer and corresponding to a predetermined region of the semiconductor layer;
an interlayer insulating layer disposed on the entire surface of the substrate; and
source and drain electrodes electrically connected with the semiconductor layer.
2. The thin film transistor according to claim 1, wherein the thermal oxide layer is formed to a thickness of 50 Å to 300 Å.
3. The thin film transistor according to claim 1, wherein the thermal oxide layer includes a silicon oxide layer.
4. A method of fabricating a thin film transistor, comprising:
preparing a substrate;
forming a polycrystalline silicon layer on the substrate; injecting impurities into the polycrystalline silicon layer for channel doping;
patterning the polycrystalline silicon layer and forming a semiconductor layer;
annealing the semiconductor layer in an H2O atmosphere, and forming a thermal oxide layer on the semiconductor layer;
forming a silicon nitride layer on the thermal oxide layer;
forming a gate electrode at a location corresponding to a predetermined region of the semiconductor layer;
forming an interlayer insulating layer on the entire surface of the substrate; and
forming source and drain electrodes electrically connected with the semiconductor layer.
5. The method according to claim 4, wherein the annealing is performed by rapid thermal annealing (RTA).
6. The method according to claim 4, wherein the annealing is performed at a temperature ranging from 400° C. to 550° C.
7. The method according to claim 4, wherein the annealing in the H2O atmosphere is performed at a pressure ranging from 10000 Pa to 2 MPa.
8. The method according to claim 4, wherein the source and drain regions are formed by injecting impurities into the semiconductor layer after forming the gate electrode.
9. The method according to claim 4, wherein the channel doping is performed by injecting boron (B) or phosphorous (p) impurities.
10. The method according to claim 4, wherein the channel doping is performed by injecting impurities at a dose ranging from 0.5×1012/cm2 to 1.5×1012/cm2.
11. An organic light emitting diode (OLED) display device, comprising:
a substrate;
a semiconductor layer disposed on the substrate, and including a channel region and source and drain regions, the channel region being doped with impurities;
a thermal oxide layer disposed on the semiconductor layer;
a silicon nitride layer disposed on the thermal oxide layer;
a gate electrode disposed on the silicon nitride layer and corresponding to a predetermined region of the semiconductor layer;
an interlayer insulating layer disposed on the entire surface of the substrate;
source and drain electrodes electrically connected with the semiconductor layer;
a first electrode electrically connected with one of the source and drain electrodes;
an organic layer disposed on the first electrode; and
a second electrode disposed on the organic layer.
12. The OLED display device according to claim 11, wherein the thermal oxide layer is formed to a thickness of 50 Å to 300 Å.
13. The OLED display device according to claim 11, wherein the thermal oxide layer is formed of silicon oxide.
US12/320,110 2008-01-18 2009-01-16 Thin film transistor, method of fabricating the same and organic light emitting diode display device having the same Abandoned US20090184632A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US13/100,979 US8673697B2 (en) 2008-01-18 2011-05-04 Thin film transistor, method of fabricating the same and organic light emitting diode display device having the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020080005729A KR101015847B1 (en) 2008-01-18 2008-01-18 Thin film transistor and fabricating for the same and organic light emitting diode device display comprising the same
KR10-2008-0005729 2008-01-18

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13/100,979 Division US8673697B2 (en) 2008-01-18 2011-05-04 Thin film transistor, method of fabricating the same and organic light emitting diode display device having the same

Publications (1)

Publication Number Publication Date
US20090184632A1 true US20090184632A1 (en) 2009-07-23

Family

ID=40875922

Family Applications (2)

Application Number Title Priority Date Filing Date
US12/320,110 Abandoned US20090184632A1 (en) 2008-01-18 2009-01-16 Thin film transistor, method of fabricating the same and organic light emitting diode display device having the same
US13/100,979 Active 2029-05-14 US8673697B2 (en) 2008-01-18 2011-05-04 Thin film transistor, method of fabricating the same and organic light emitting diode display device having the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US13/100,979 Active 2029-05-14 US8673697B2 (en) 2008-01-18 2011-05-04 Thin film transistor, method of fabricating the same and organic light emitting diode display device having the same

Country Status (2)

Country Link
US (2) US20090184632A1 (en)
KR (1) KR101015847B1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120305921A1 (en) * 2011-06-03 2012-12-06 Byoung-Keon Park Thin film transistor, manufacturing method of thin film transistor, and organic light emitting diode display including the same
EP2613346A1 (en) * 2011-11-11 2013-07-10 Boe Technology Group Co. Ltd. Thin film transistor, manufacturing method thereof and display device
JP2015502029A (en) * 2011-11-11 2015-01-19 京東方科技集團股▲ふん▼有限公司 THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE
CN111129158A (en) * 2018-10-31 2020-05-08 三星显示有限公司 Display device and method for manufacturing the same

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101147414B1 (en) * 2009-09-22 2012-05-22 삼성모바일디스플레이주식회사 Organic light emitting diode display and method for manufacturing the same
KR102040069B1 (en) * 2013-07-09 2019-11-05 삼성디스플레이 주식회사 Manufacturing method of organic electroluminescent display

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5466641A (en) * 1992-06-15 1995-11-14 Kawasaki Steel Corporation Process for forming polycrystalline silicon film
US5548132A (en) * 1994-10-24 1996-08-20 Micron Technology, Inc. Thin film transistor with large grain size DRW offset region and small grain size source and drain and channel regions
US5565691A (en) * 1993-12-22 1996-10-15 Tdk Corporation Thin film semiconductor system
US5771110A (en) * 1995-07-03 1998-06-23 Sanyo Electric Co., Ltd. Thin film transistor device, display device and method of fabricating the same
US6150203A (en) * 1994-08-31 2000-11-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
US20010002703A1 (en) * 1999-11-30 2001-06-07 Jun Koyama Electric device
US20020113264A1 (en) * 2001-02-20 2002-08-22 Kazuhiko Horikoshi Thin-film transistor and method of manufacturing the same
US20050046342A1 (en) * 2003-08-28 2005-03-03 Park Jin-Woo Organic electroluminescence display
US20060051903A1 (en) * 2004-08-04 2006-03-09 Sony Corporation Method of manufacturing thin film semiconductor device, and thin film semiconductor device
US20070117284A1 (en) * 2004-02-16 2007-05-24 Shigeki Imai Thin film transistor, method of manufacturing same, display device, method of modifying an oxide film, method of forming an oxide film, semiconductor device, method of manufacturing semiconductor device, and apparatus for manufacturing semiconductor device
US20080135838A1 (en) * 2006-12-06 2008-06-12 Samsung Sdi Co., Ltd Thin film transistor, method of fabricating the same, and organic light emitting diode display device including the same
US20080135893A1 (en) * 2006-12-06 2008-06-12 Hye-Hyang Park Thin film transistor, method of fabricating the same, and display device including the same

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970000467B1 (en) 1993-06-25 1997-01-11 현대전자산업 주식회사 Gate insulator film of semiconductor device
JPH07321323A (en) 1994-05-24 1995-12-08 Matsushita Electric Ind Co Ltd Thin film transistor and its manufacturing method
TW447136B (en) 1996-06-06 2001-07-21 Seiko Epson Corp Method for manufacturing thin film transistor, liquid crystal display and electronic device both produced by the method
JP3442693B2 (en) 1999-08-19 2003-09-02 株式会社半導体エネルギー研究所 Method for manufacturing insulating gate type field effect semiconductor device
JP3323838B2 (en) 1999-09-03 2002-09-09 松下電器産業株式会社 Polysilicon thin film transistor, method of manufacturing the same, and liquid crystal display device using the same
TWI263336B (en) * 2000-06-12 2006-10-01 Semiconductor Energy Lab Thin film transistors and semiconductor device
TW550530B (en) * 2000-10-27 2003-09-01 Semiconductor Energy Lab Display device and method of driving the same
JP2003008023A (en) 2001-06-21 2003-01-10 Matsushita Electric Ind Co Ltd Thin-film transistor, array substrate using the same, display element, and organic electroluminescence display device
JP2003197632A (en) 2001-12-25 2003-07-11 Seiko Epson Corp Manufacturing method of thin film transistor, semiconductor device and electric optical device
KR20040050768A (en) * 2002-12-09 2004-06-17 엘지.필립스 엘시디 주식회사 Method of fabricating Thin Film Transistor for Liquid Crystal Display Device with driving circuit
JP2004193226A (en) 2002-12-09 2004-07-08 Nec Electronics Corp Nonvolatile semiconductor memory device and method of manufacturing the same
KR100977538B1 (en) 2003-01-10 2010-08-23 엘지디스플레이 주식회사 Method of manufacturing for poly-Silicone thin layer
JP4237147B2 (en) 2004-03-26 2009-03-11 シャープ株式会社 THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, DISPLAY DEVICE, AND METHOD FOR MODIFIING OXIDE FILM
KR100685391B1 (en) * 2004-05-18 2007-02-22 삼성에스디아이 주식회사 TFT, fabricating method of the same and flat panel display having the TFT
KR100599595B1 (en) * 2004-05-24 2006-07-13 삼성에스디아이 주식회사 A semiconductor device for an organic electro-luminescence light emitting cell, and a manufacturing method therof
KR100666552B1 (en) 2004-06-30 2007-01-09 삼성에스디아이 주식회사 Method of fabricating a semiconductor device and a semiconductor fabricated by the same method
KR100666563B1 (en) 2004-07-05 2007-01-09 삼성에스디아이 주식회사 Method of fabricating a semiconductor device and a semiconductor fabricated by the smae method
KR100685396B1 (en) 2004-07-22 2007-02-22 삼성에스디아이 주식회사 Method of fabricating a semiconductor device and a semiconductor fabricated bt the smae method
KR100656495B1 (en) * 2004-08-13 2006-12-11 삼성에스디아이 주식회사 Thin film transistor and method fabricating thereof
US7416928B2 (en) * 2004-09-08 2008-08-26 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of semiconductor device
WO2006031017A1 (en) 2004-09-17 2006-03-23 Jae-Sang Ro Method for annealing silicon thin films using conductive layerand polycrystalline silicon thin films prepared therefrom
US7474125B2 (en) * 2005-12-07 2009-01-06 Dsm Solutions, Inc. Method of producing and operating a low power junction field effect transistor

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5466641A (en) * 1992-06-15 1995-11-14 Kawasaki Steel Corporation Process for forming polycrystalline silicon film
US5565691A (en) * 1993-12-22 1996-10-15 Tdk Corporation Thin film semiconductor system
US6150203A (en) * 1994-08-31 2000-11-21 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a semiconductor device
US5548132A (en) * 1994-10-24 1996-08-20 Micron Technology, Inc. Thin film transistor with large grain size DRW offset region and small grain size source and drain and channel regions
US5771110A (en) * 1995-07-03 1998-06-23 Sanyo Electric Co., Ltd. Thin film transistor device, display device and method of fabricating the same
US20010002703A1 (en) * 1999-11-30 2001-06-07 Jun Koyama Electric device
US20020113264A1 (en) * 2001-02-20 2002-08-22 Kazuhiko Horikoshi Thin-film transistor and method of manufacturing the same
US20050046342A1 (en) * 2003-08-28 2005-03-03 Park Jin-Woo Organic electroluminescence display
US20070117284A1 (en) * 2004-02-16 2007-05-24 Shigeki Imai Thin film transistor, method of manufacturing same, display device, method of modifying an oxide film, method of forming an oxide film, semiconductor device, method of manufacturing semiconductor device, and apparatus for manufacturing semiconductor device
US20060051903A1 (en) * 2004-08-04 2006-03-09 Sony Corporation Method of manufacturing thin film semiconductor device, and thin film semiconductor device
US20080135838A1 (en) * 2006-12-06 2008-06-12 Samsung Sdi Co., Ltd Thin film transistor, method of fabricating the same, and organic light emitting diode display device including the same
US20080135893A1 (en) * 2006-12-06 2008-06-12 Hye-Hyang Park Thin film transistor, method of fabricating the same, and display device including the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120305921A1 (en) * 2011-06-03 2012-12-06 Byoung-Keon Park Thin film transistor, manufacturing method of thin film transistor, and organic light emitting diode display including the same
US8803148B2 (en) * 2011-06-03 2014-08-12 Samsung Display Co., Ltd. Thin film transistor, manufacturing method of thin film transistor, and organic light emitting diode display including the same
EP2613346A1 (en) * 2011-11-11 2013-07-10 Boe Technology Group Co. Ltd. Thin film transistor, manufacturing method thereof and display device
JP2015502029A (en) * 2011-11-11 2015-01-19 京東方科技集團股▲ふん▼有限公司 THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE
EP2613346A4 (en) * 2011-11-11 2015-04-08 Boe Technology Group Co Ltd Thin film transistor, manufacturing method thereof and display device
CN111129158A (en) * 2018-10-31 2020-05-08 三星显示有限公司 Display device and method for manufacturing the same

Also Published As

Publication number Publication date
US8673697B2 (en) 2014-03-18
KR101015847B1 (en) 2011-02-23
KR20090079619A (en) 2009-07-22
US20110207268A1 (en) 2011-08-25

Similar Documents

Publication Publication Date Title
US8513669B2 (en) Thin film transistor including metal or metal silicide structure in contact with semiconductor layer and organic light emitting diode display device having the thin film transistor
US7825476B2 (en) Method of fabricating polycrystalline silicon, TFT fabricated using the same, method of fabricating the TFT, and organic light emitting diode display device including the TFT
US7999261B2 (en) Thin film transistor, method of fabricating the same, and organic light emitting diode display device having the TFT
US9117798B2 (en) Thin film transistor, method of fabricating the same and organic light emitting diode display device including the same
US8283668B2 (en) Thin film transistor, method of fabricating the same, and organic light emitting diode display device including the same
US20080157116A1 (en) Thin film transistor, method of fabricating the same, and organic light emitting diode display device including the same
US8569764B2 (en) Thin film transistor, method of fabricating the same, and organic light emitting diode display device including the same
US8318523B2 (en) Thin film transistor, method of fabricating the same and organic light emitting diode display device having the same
US8673697B2 (en) Thin film transistor, method of fabricating the same and organic light emitting diode display device having the same
US8623720B2 (en) Method of fabricating a thin film transistor from amorphous silicon and organic light emitting diode display device having the thin film transistor
KR100810639B1 (en) Thin film transistor and fabricating for the same and organic light emitting diode device display comprising the same
US20110033992A1 (en) Thin Film Transistor, Method of Fabricating the Same, and Organic Light Emitting Display Device Including the Same
US8294158B2 (en) Thin film transistor, method of fabricating the same, and organic light emitting diode display device including the thin film transistor
US20100224882A1 (en) Thin film transistor, method of fabricating the same, and organic light emitting diode display device having the same
US8044576B2 (en) Organic light emitting display and method of fabricating the same
KR100810638B1 (en) Thin film transistor and fabricating for the same and organic light emitting diode device display comprising the same
US20100163856A1 (en) Method of fabricating polysilicon, thin film transistor, method of fabricating the thin film transistor, and organic light emitting diode display device including the thin film transistor

Legal Events

Date Code Title Description
AS Assignment

Owner name: SAMSUNG MOBILE DISPLAY CO., LTD., A CORPORATION CH

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KIM, MOO-JIN;KIM, KYOUNG-BO;LEE, KI-YONG;AND OTHERS;REEL/FRAME:022531/0983

Effective date: 20090113

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION