KR970000467B1 - Gate insulator film of semiconductor device - Google Patents
Gate insulator film of semiconductor device Download PDFInfo
- Publication number
- KR970000467B1 KR970000467B1 KR1019930011749A KR930011749A KR970000467B1 KR 970000467 B1 KR970000467 B1 KR 970000467B1 KR 1019930011749 A KR1019930011749 A KR 1019930011749A KR 930011749 A KR930011749 A KR 930011749A KR 970000467 B1 KR970000467 B1 KR 970000467B1
- Authority
- KR
- South Korea
- Prior art keywords
- thermal oxide
- film
- vapor deposition
- gate insulating
- chemical vapor
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 20
- 239000012212 insulator Substances 0.000 title 1
- 238000000034 method Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 10
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 6
- 238000011065 in-situ storage Methods 0.000 claims description 4
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 239000007789 gas Substances 0.000 abstract 1
- 239000010408 film Substances 0.000 description 37
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000013078 crystal Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
제1도는 종래기술에 따른 반도체 장치의 게이트 절연막 형성 공정 단면도.1 is a cross-sectional view of a gate insulating film forming process of a semiconductor device according to the prior art.
제2도는 본 발명의 일실시예에 따른 반도체 장치의 게이트 절연막 형성 공정 단면도.2 is a cross-sectional view of a gate insulating film forming process of a semiconductor device according to an embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 열산화막1 semiconductor substrate 2 thermal oxide film
3 : TEOS막 4 : 게이트 전극용 폴리실리콘막3: TEOS film 4: Polysilicon film for gate electrode
본 발명은 반도체 소자 제조공정중 게이트 절연막 형성방법에 관한 것으로, 특히 열산화막과 화학기상증착막(Chemical Vapor Deposition)의 적층구조를 갖는 반도체 장치의 게이트 절연막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate insulating film during a semiconductor device manufacturing process, and more particularly, to a method for forming a gate insulating film of a semiconductor device having a laminated structure of a thermal oxide film and a chemical vapor deposition film.
일반적으로, 온도가 높은 산화분위기(O2)속에서 실리콘 기판을 노출시키면 표면에서 균일한 열산화막(SiO2)이 형성된다. 이 열산화막은 물성적으로 매우 안정된 것이어서, 산화 방법에 관계없이 거의 같은 성질을 보여준다.In general, when the silicon substrate is exposed in a high temperature oxidation atmosphere (O 2 ), a uniform thermal oxide film (SiO 2 ) is formed on the surface. This thermal oxide film is very stable in physical properties, and shows almost the same properties regardless of the oxidation method.
또한 소자를 구성하는 실리콘을 이용하고 있기 때문에 실리콘 소자 제조 공정에 있어서 가장 유용한 절연재료로 사용되고 있다.In addition, since the silicon constituting the device is used, it is used as the most useful insulating material in the silicon device manufacturing process.
제1도는 종래기술에 따른 반도체 장치의 게이트 절연막 형성 공정 단면도로, 먼저 반도체 기판(1)을 대기압(Atomospheric) 및 약 700℃이상의 온도를 갖는 반응로에 삽입한 후, O2가스 또는 O2가스와 H2가스가 혼합된 가스분위기를 조정하여 상기 반도체 기판(1)상에 게이트 절연막으로 사용될 열산화막(20)을 성장시킨 것을 도시한 것이다. 미설명 부호 4는 게이트 전극용 폴리실리콘막을 나타낸다.1 is a cross-sectional view illustrating a process of forming a gate insulating film of a semiconductor device according to the prior art. First, a semiconductor substrate 1 is inserted into a reactor having an atmospheric pressure and a temperature of about 700 ° C. or higher, and then O 2 gas or O 2 gas. And a thermal atmosphere 20 to be used as a gate insulating film is grown on the semiconductor substrate 1 by adjusting a gas atmosphere mixed with H 2 gas. Reference numeral 4 denotes a polysilicon film for the gate electrode.
점차 소자가 고집적화되어갈수록 게이트 폭이 줄고 박막의 두께가 얇아지게 되는데, 계속해서 상기와 같은 종래기술에 의한 고온의 열산화막을 게이트 절연막으로 형성하게 될 경우 상기 열산화막 형성을 위한 고온의 열산화 공정시 기판이 스트레스를 받게 되어 항복 전압(Breakdown Voltage) 및 CCST(Constant Current Stress Time)등의 소자의 전기적 특성이 저하되는 문제점이 있었다.As the device becomes more integrated, the gate width decreases and the thickness of the thin film becomes thinner. When the high temperature thermal oxide film according to the related art is formed as a gate insulating film, the high temperature thermal oxidation process for forming the thermal oxide film is performed. When the substrate is stressed, the electrical characteristics of devices such as breakdown voltage and constant current stress time are deteriorated.
상기 문제점을 해결하기 위하여 안정된 본 발명은 고온에 의해 반도체 기판의 스트레스 및 결정결함을 제거하여 소자의 전기적 특성을 개선하기 위한 반도체 장치의 게이트 절연막 형성방법을 제공하는데 그 목적이 있다.The present invention, which is stable in order to solve the above problems, has an object to provide a method for forming a gate insulating film of a semiconductor device for improving the electrical characteristics of the device by removing the stress and crystal defects of the semiconductor substrate by high temperature.
상기 목적을 달성하기 위하여 본 발명은 반도체 장치의 게이트 절연막 형성방법에 있어서, 반도체 기판상에 열산화막과 화학 기상 증착막을 차례로 형성하는 것을 특징으로 한다.In order to achieve the above object, the present invention is characterized in that in the method for forming a gate insulating film of a semiconductor device, a thermal oxide film and a chemical vapor deposition film are sequentially formed on a semiconductor substrate.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2도는 본 발명의 일실시예에 따른 반도체 장치의 게이트 절연막 형성 공정 단면도로, 먼저 반도체 기판(1)을 저압 화학 기상 중착로(Low Pressure Chemical Vapor Depsoition Furnace)에 삽입한 후, 인-시츄(In-Situ)방식으로 약 500℃ 내지 700℃ 정도의 N2가스와 O2가스의 혼합가스 분위기속에 얇게 열산화막(2)을 성장 시킨 다음, 연속적으로 상기 열산화막(2) 상부에 화학 기상 증착법에 의해 테트라에쏘시시레인(Tetra Eth Oxy Silane; TEOS)막(3)을 차례로 증착한 것을 도시한 것이다.2 is a cross-sectional view illustrating a process of forming a gate insulating film of a semiconductor device according to an embodiment of the present invention. First, the semiconductor substrate 1 is inserted into a low pressure chemical vapor deposition furnace, and then in-situ ( In-situ) to grow a thin thermal oxide film (2) thinly in a mixed gas atmosphere of about 500 ℃ to 700 ℃ about 2 ℃ and O 2 gas, and then successively chemical vapor deposition on the thermal oxide film (2) Shows the deposition of the Tetra Eth Oxy Silane (TEOS) film 3 in sequence.
미설명 부호 4는 게이트 전극용 폴리실리콘막을 나타낸다.Reference numeral 4 denotes a polysilicon film for the gate electrode.
상기 테트라에쏘시시레인막(TEOS)(3) 증착 공정시 원하는 게이트 절연막의 두께를 조정한다.The thickness of the desired gate insulating film is adjusted during the deposition process of the tetraisocysteine film (TEOS) 3.
상기와 같이 이루어지는 본 발명은 저압 화학 기상 증착로(Low Pressure Chemical Vapor Deposirion Furnace)에 반도체 기판을 삽입한 후, 장비교환 없이 인-시츄(In-Situ)방식에 의해 약 500℃ 내지 700℃의 비교적 저온에서 열산화막을 형성한 후, 이어 화학 기상 증착 방식으로 테트라에쏘시시레인막을 연속적으로 증착하여 게이트 절연막을 형성함으로써 고온에 의한 스트레스를 감소시켜 게이트 절연막 표면의 결정결함을 줄일 수 있어 항복 전압 개선의 효과를 얻을 수 있다.According to the present invention made as described above, the semiconductor substrate is inserted into a low pressure chemical vapor deposition furnace, and is relatively in the range of about 500 ° C. to 700 ° C. by an in-situ method without equipment replacement. After the thermal oxide film is formed at low temperature, the tetra-isocysilane film is subsequently deposited by chemical vapor deposition to form a gate insulating film, thereby reducing stress due to high temperature, thereby reducing crystal defects on the surface of the gate insulating film, thereby improving breakdown voltage. The effect can be obtained.
또한, 열산화막과 화학 시상 증착막의 적층된 막을 게이트 절연막을 형성하므로써 단층의 열산화막에 비해 항복 전압 및 CCST(Constant Current Stress Time)등의 전기적 특성을 향상시킬 수 있다.In addition, by forming a gate insulating film on the laminated film of the thermal oxide film and the chemical sagittal deposition film, it is possible to improve the electrical characteristics such as the breakdown voltage and the constant current stress time (CCST) compared to the single layer thermal oxide film.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930011749A KR970000467B1 (en) | 1993-06-25 | 1993-06-25 | Gate insulator film of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930011749A KR970000467B1 (en) | 1993-06-25 | 1993-06-25 | Gate insulator film of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950002071A KR950002071A (en) | 1995-01-04 |
| KR970000467B1 true KR970000467B1 (en) | 1997-01-11 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930011749A KR970000467B1 (en) | 1993-06-25 | 1993-06-25 | Gate insulator film of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR970000467B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101015847B1 (en) | 2008-01-18 | 2011-02-23 | 삼성모바일디스플레이주식회사 | Thin film transistor and fabricating for the same and organic light emitting diode device display comprising the same |
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1993
- 1993-06-25 KR KR1019930011749A patent/KR970000467B1/en not_active IP Right Cessation
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| Publication number | Publication date |
|---|---|
| KR950002071A (en) | 1995-01-04 |
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