JPH0533306B2 - - Google Patents
Info
- Publication number
- JPH0533306B2 JPH0533306B2 JP5875884A JP5875884A JPH0533306B2 JP H0533306 B2 JPH0533306 B2 JP H0533306B2 JP 5875884 A JP5875884 A JP 5875884A JP 5875884 A JP5875884 A JP 5875884A JP H0533306 B2 JPH0533306 B2 JP H0533306B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- glow discharge
- distance
- film
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000007789 gas Substances 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 125000004433 nitrogen atom Chemical group N* 0.000 claims description 2
- 125000004430 oxygen atom Chemical group O* 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000010408 film Substances 0.000 description 49
- 230000006866 deterioration Effects 0.000 description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 239000012159 carrier gas Substances 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 239000012141 concentrate Substances 0.000 description 2
- 239000003085 diluting agent Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000002994 raw material Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001941 electron spectroscopy Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000013441 quality evaluation Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/50—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges
- C23C16/505—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges
- C23C16/509—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating using electric discharges using radio frequency discharges using internal electrodes
- C23C16/5096—Flat-bed apparatus
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Chemical Vapour Deposition (AREA)
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、MIS型トランジスタにおけるゲート
絶縁膜や各種デバイスによくもちいられるパシベ
ーシヨン用絶縁体膜あるいはコーテイング用薄膜
などに利用される絶縁膜の製造方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method for manufacturing an insulating film used as a gate insulating film in MIS transistors, a passivation insulating film often used in various devices, or a coating thin film. It is something.
従来例の構成とその問題点
比較的低温(300℃前後)で窒化ケイ素膜また
は窒化ケイ素膜を形成する方法として容量結合型
高周波グロー放電がよく用いられる。Conventional Structures and Problems Capacitively coupled high-frequency glow discharge is often used as a method for forming silicon nitride films or silicon nitride films at relatively low temperatures (around 300° C.).
第1図は、容量結合型高周波グロー放電装置の
簡略断面図である。ここではグロー放電室a内に
対向して配置された高周波電極bと基板ホルダc
との両電極間距離dを変えられるようになつてい
る。このような装置において、従来、高周波電極
と基板ホルダとの電極間距離dは、プラズマ放電
状態の均一性やそれにともなう蒸着膜厚の均一性
を得るための付属的パラメータとして高周波電源
電力などに合わせて変化させていた。従つて、こ
の電極間距離dは、一般的蒸着条件としては30〜
35mm前後で、一般的には電気的特性の劣悪な絶縁
膜ができていた。従来例において最も狭い電極距
離は電子通信学会SSD82-148周南生他には電極距
離20mmという報告がある。 FIG. 1 is a simplified cross-sectional view of a capacitively coupled high frequency glow discharge device. Here, a high frequency electrode b and a substrate holder c are placed facing each other in a glow discharge chamber a.
The distance d between the two electrodes can be changed. In such devices, the distance d between the high-frequency electrode and the substrate holder has conventionally been adjusted according to the high-frequency power supply as an additional parameter to obtain uniformity of the plasma discharge state and the resulting uniformity of the deposited film thickness. I was changing it. Therefore, this inter-electrode distance d is 30~30 as a general vapor deposition condition.
At around 35mm, an insulating film with poor electrical properties was generally formed. The narrowest electrode distance in the conventional example is reported to be 20 mm in the Institute of Electronics and Communication Engineers SSD 82-148 Shunan Sei et al.
発明の目的
本発明は、容量結合型高周波グロー放電を用い
た絶縁膜の製造条件を最適化し、特にa−Si:H
を使つたTFTの電気的特性の優れた高性能ゲー
ト絶縁膜を形成する製造方法を提供することを目
的とする。Purpose of the Invention The present invention optimizes the manufacturing conditions of an insulating film using capacitively coupled high-frequency glow discharge, and in particular, a-Si:H
The purpose of this study is to provide a manufacturing method for forming a high-performance gate insulating film with excellent electrical properties for TFT using .
発明の構成
本発明は、容量結合型高周波グロー放電装置に
おける電極間距離を20mm未満とするものである。Structure of the Invention The present invention provides a capacitively coupled high frequency glow discharge device in which the distance between electrodes is less than 20 mm.
実施例の説明
本発明者らは、第1図に示している容量結合型
高周波グロー放電装置における電極間距離dは、
窒化ケイ素膜や窒化酸化ケイ素膜の膜質に大きな
影響を与えるパラメータであることを見い出し
た。特に高性能絶縁膜として利用する場合などに
は、まず電極間距離dに着目し、これを20mm未満
に保ちつつ他のパラメータを変化させて均一性な
ど諸特性が得られるように、絶縁膜の製造条件を
最適化することが重要である。Description of Examples The present inventors have determined that the inter-electrode distance d in the capacitively coupled high-frequency glow discharge device shown in FIG.
It was discovered that this parameter has a great influence on the film quality of silicon nitride films and silicon nitride oxide films. Particularly when using it as a high-performance insulating film, we first focus on the distance d between the electrodes, and while keeping this at less than 20 mm, we change other parameters to obtain various properties such as uniformity of the insulating film. It is important to optimize manufacturing conditions.
ここでは絶縁膜3として窒化ケイ素膜を例にと
り説明する。尚、窒化酸化ケイ素膜の場合、窒化
ケイ素膜を製造する各種混合ガスに、N2Oなど
を少量加えるだけで製造できるので、以下と同様
のことが言える。 Here, a silicon nitride film will be described as an example of the insulating film 3. Note that in the case of a silicon nitride oxide film, it can be manufactured by simply adding a small amount of N 2 O or the like to various mixed gases for manufacturing the silicon nitride film, so the same can be said as described below.
まず窒化ケイ素膜の膜質評価方法を記す。この
膜質評価に使用したMIS型トランジスタの断面図
を第2図に示している。ガラス基板1上にM0よ
りなるゲート電極2を選択被着し、評価するゲー
ト絶縁膜3、水素化非晶質シリコン4それにPを
ドープしたn+の水素化非晶質シリコン5の3層
を被着し、その後、Alよりなるソース6、ドレ
イン電極7を選択被着形成し、チヤンネル部に露
出しているPをドープしたn+の水素化非晶質シ
リコン5の一部を、HF:HNO3=1:30の混合
液でエツチングしたものである。 First, a method for evaluating the film quality of silicon nitride films will be described. Figure 2 shows a cross-sectional view of the MIS transistor used for this film quality evaluation. A gate electrode 2 made of M0 is selectively deposited on a glass substrate 1, and three layers of a gate insulating film 3 to be evaluated, hydrogenated amorphous silicon 4, and P-doped n + hydrogenated amorphous silicon 5 are deposited. After that, a source 6 and a drain electrode 7 made of Al are selectively deposited, and a part of the P-doped n + hydrogenated amorphous silicon 5 exposed in the channel part is covered with HF. :HNO 3 =1:30 mixture.
このMIS型トランジスタのゲート絶縁膜3を評
価すると絶縁膜とし、ゲート・ドレイン両電極に
電圧(10、20、30、40、50、60ボルト)を30分間
順に印加し、その都度トランジスタ特性を測定す
ることにより、しきい値電圧のシフトつまりゲー
ト絶縁膜(評価の対象となる絶縁膜)中に、強制
的に注入された電子の数の大小がわかる。この電
子注入によるトランジスタ特性の劣化を現わす飽
和ドレイン電流IDの低下(ここではゲート電圧
12V、ドレイン電圧12V、ソース接地でのドレイ
ン電流値IDの低下)を測定し、絶縁膜膜質の評価
をした。また絶縁膜単層で、絶縁破壊電界強度を
測定し、耐圧をも評価した。 To evaluate the gate insulating film 3 of this MIS type transistor, voltage (10, 20, 30, 40, 50, 60 volts) was sequentially applied to both the gate and drain electrodes for 30 minutes, and the transistor characteristics were measured each time. By doing so, it is possible to determine the shift in threshold voltage, that is, the magnitude of the number of electrons forcibly injected into the gate insulating film (the insulating film to be evaluated). A decrease in the saturation drain current I D (in this case, the gate voltage
12V, drain voltage 12V, drain current value ID (decrease in source common) was measured, and the quality of the insulating film was evaluated. In addition, the dielectric breakdown field strength was measured using a single layer of insulating film, and the withstand voltage was also evaluated.
このMIS型トランジスタの半導体層4(トラン
ジスタの活性領域)には、すべて同一条件で製造
した水素化晶質シリコンをもちいた。またこの電
圧印加によるトランジスタの劣化原因が、ゲート
絶縁膜に起因するものであり、活性領域となる水
素化非晶質シリコンの劣化と比べはるかに大きい
ことを確認している。 For the semiconductor layer 4 (active region of the transistor) of this MIS type transistor, hydrogenated crystalline silicon manufactured under the same conditions was used. It has also been confirmed that the cause of deterioration of the transistor due to this voltage application is due to the gate insulating film, and is far greater than the deterioration of the hydrogenated amorphous silicon that forms the active region.
製造装置は、第1図に示すように、グロー放電
室aとその室内に対向して配置された高周波電極
bと基板ホルダcとを有し、その両電極間距離d
を変化させうるようになつており、その室内にガ
スが供給されるように構成eされた容量結合型高
周波グロー放電装置である。 As shown in FIG. 1, the manufacturing apparatus has a glow discharge chamber a, a high frequency electrode b and a substrate holder c disposed facing each other in the chamber, and a distance d between the two electrodes.
This is a capacitively coupled high-frequency glow discharge device configured so that gas can be changed and gas is supplied into the chamber.
実施例 1
SiH4などケイ素原子を含むガスおよびNH3な
ど窒素原子を含むガス(但しN2を除く)を原料
ガスとし、キヤリアガスとしてH2を使用する場
合について述べる。Example 1 A case will be described in which a gas containing silicon atoms such as SiH 4 and a gas containing nitrogen atoms such as NH 3 (excluding N 2 ) are used as source gases and H 2 is used as a carrier gas.
本発明者らの窒化ケイ素よりなる絶縁膜3は、
製造条件の最適化の結果得られた次の条件で形成
される。混合ガス成分比は、SiH4:NH3:H2=
1:6:12で、基板温度300℃、高周波電極単位
面積当り、13.56MHzの高周波電源電力0.2W/cm2
絶縁膜膜厚約4000Åのゲート絶縁膜3を形成す
る。 The insulating film 3 made of silicon nitride by the present inventors is
It is formed under the following conditions obtained as a result of optimization of manufacturing conditions. The mixed gas component ratio is SiH 4 :NH 3 :H 2 =
1:6:12, substrate temperature 300℃, 13.56MHz high frequency power supply power per unit area of high frequency electrode 0.2W/cm 2
A gate insulating film 3 having a thickness of about 4000 Å is formed.
ここで第1図に示しているように電極間距離d
だけを変化させたときの絶縁膜の光学的特性を、
第3図、第4図に、それらの絶縁物を使用した
MIS型トランジスタ(第2図参照)の電圧印加に
よる電流値劣化を第5図に示す。第3図における
エネルギギヤツプEopt/gの定義は、吸収関係α=
5×104となる光の波長のエネルギをEopt/gとして
いる。 Here, as shown in Fig. 1, the distance between the electrodes d
The optical properties of the insulating film when only the
Figures 3 and 4 show the use of these insulators.
FIG. 5 shows the current value deterioration due to voltage application of the MIS type transistor (see FIG. 2). The definition of the energy gap E opt/g in Figure 3 is the absorption relationship α=
The energy of the wavelength of light that is 5×10 4 is E opt/g .
またオージエ電子分光測定より得られたデータ
から、どの膜もほぼ元素比Si/N=3/4になつ
ている。従つて、光学干渉から求められた屈折率
(第4図)が大きくなるほど、充てん密度が高く
なつていると考えられ、優れた絶縁膜である高温
熱CVDによる窒化ケイ素膜に近づいている。 Furthermore, data obtained from Augier electron spectroscopy shows that the elemental ratio Si/N is approximately 3/4 in all films. Therefore, as the refractive index determined from optical interference (Figure 4) increases, it is thought that the packing density increases, approaching the silicon nitride film produced by high-temperature thermal CVD, which is an excellent insulating film.
第5図(第9図も同様であるが)は、第2図の
構造をしたMIS型トランジスタにおいて、ゲート
電圧(VG)、ドレイン電圧(VD)ともに12ボルト
を印加し、ソース接地(VS=0)の状態でのド
レイン電流(ID)の初期値
(I
D初期値)
を測定し、それを基準にとつている。電圧印加の
方法は、まずソース電極を接地し、ゲート・ドレ
イン両電極に10ボルト印加したまま30分間印加放
置した後、前記
I
D初期値
と同条件でドレイン電流(ID10)を測定し、
I
D初期値
との比をとる。次にVG=VD=20ボルト、ソース
接地で30分間印加放置後、前記ID初期値と同条件
でID20を測定し、
I
D初期値
との比をとる。このように順にゲート電圧、ドレ
イン電圧に、30、40、50、60ボルトと30分間ずつ
印加し、それぞれI
D初期値と同条件でIDを測定
し、
I
D初期値
との比をとり、プロツトしたグラフである。 FIG. 5 (FIG. 9 is similar) shows an MIS type transistor having the structure shown in FIG. 2, with 12 volts applied to both the gate voltage (V G ) and the drain voltage (V D ), The initial value (I D initial value) of the drain current (I D ) under the condition (V S =0) is measured and used as a reference. The voltage application method is to first ground the source electrode, apply 10 volts to both the gate and drain electrodes, leave it for 30 minutes, and then measure the drain current ( ID10 ) under the same conditions as the initial ID value. Take the ratio with the initial ID value. Next, after applying V G =V D =20 volts for 30 minutes with the source grounded, I D20 is measured under the same conditions as the initial ID value, and the ratio with the initial ID value is calculated. In this way, apply 30, 40, 50, and 60 volts to the gate voltage and drain voltage in sequence for 30 minutes each, measure ID under the same conditions as the initial ID value, and calculate the ratio with the initial ID value. , is a plotted graph.
ゲート絶縁膜4000Å内電界強度が約1×
106V/mとなる40ボルト電圧印加時のID劣化特性
を見ると電極間距離が短かい程劣化が小さくなつ
ている。また、絶縁破壊電界強度を見ても電極間
距離dが短かい程大きい値を示している。 Electric field strength within 4000Å of gate insulating film is approximately 1×
Looking at the ID deterioration characteristics when a voltage of 40 volts (10 6 V/m) is applied, the shorter the distance between the electrodes, the smaller the deterioration. Also, when looking at the dielectric breakdown field strength, the shorter the distance d between the electrodes, the greater the value.
一方、被着膜厚の均一性の面から電極間距離を
見た場合、近づき過ぎるとプラズマ放電が電極中
央部または電極外周附近に集中し、不均一な状態
になるので、必要とされる均一性及びその面積に
よつて最小電極距離は異なるが普通15mm前後が望
ましい。なお、原料ガスのほかに希釈ガスを用い
るが、この希釈ガスの種類及び混合比を最適化す
ればさらに最小電極距離は小さくなる。 On the other hand, when looking at the distance between the electrodes from the viewpoint of uniformity of the deposited film thickness, if the distance between the electrodes is too close, the plasma discharge will concentrate at the center of the electrode or near the outer periphery of the electrode, resulting in an uneven state. The minimum electrode distance varies depending on the nature and area of the electrode, but it is generally desirable to be around 15 mm. Note that a diluent gas is used in addition to the raw material gas, and the minimum electrode distance can be further reduced by optimizing the type and mixing ratio of this diluent gas.
実施例 2
原料ガスの他にキヤリアガスとして主にN2を
使用する場合について述べる。混合ガス成分比
は、SiH4:NH3:N2=2:9:25であり、基板
温度320℃高周波電極単位面積当り13.56MHzの高
周波電源実効電力0.2W/cm2、絶縁膜厚約4500Å
のゲート絶縁膜を形成する。実施例1と同様な測
定方法による結果を第7図〜第10図に示す。第
7図、第8図に示すとおり、Eopt/g、屈折率とも
に実施例1と同じ傾向にあり、電極間距離dが短
かいほど膜質が優れているこを説明している。ま
た実施例1と同様にゲート・ドレイン両電極に電
圧印加し、ゲート絶縁膜内に電子を強制注入させ
飽和電流値劣化を測定した結果を第9図に示す。
実施例1の場合と同様の理由で、ゲート絶縁膜
4500Å内電界強度が約1×106V/mとなる45ボ
ルトあたりの電圧印加時のID劣化特性を見ると、
電極間距離が20mmぐらいから電気的特性の劣化が
始まり、28mmでは大きく劣化している。Example 2 A case where N 2 is mainly used as a carrier gas in addition to the raw material gas will be described. The mixed gas component ratio is SiH 4 :NH 3 :N 2 = 2:9:25, substrate temperature is 320°C, 13.56 MHz high frequency power source per unit area of high frequency electrode, effective power 0.2 W/cm 2 , insulation film thickness approximately 4500 Å.
Form a gate insulating film. Results obtained by the same measuring method as in Example 1 are shown in FIGS. 7 to 10. As shown in FIGS. 7 and 8, both E opt/g and the refractive index have the same tendency as in Example 1, which explains that the shorter the inter-electrode distance d, the better the film quality. Further, as in Example 1, a voltage was applied to both the gate and drain electrodes, electrons were forcibly injected into the gate insulating film, and saturation current value deterioration was measured. The results are shown in FIG.
For the same reason as in Example 1, the gate insulating film
Looking at the ID deterioration characteristics when a voltage of around 45 volts is applied, where the electric field strength within 4500 Å is approximately 1 × 10 6 V/m,
The electrical characteristics begin to deteriorate when the distance between the electrodes is around 20 mm, and the deterioration is significant at 28 mm.
また第10図に示すように実施例1と同様の理
由で絶縁破壊電界強度においても電極間距離が短
かい程耐圧がよい。 Further, as shown in FIG. 10, for the same reason as in Example 1, the shorter the distance between the electrodes, the better the breakdown voltage in terms of dielectric breakdown field strength.
一方、披着膜厚の均一性の面から電極間距離を
見た場合、12mm未満の関係では、プラズマ放電が
電極中央部または電極外周附近に集中し、不均一
な状態になり、12mm以上が望ましい。 On the other hand, when looking at the interelectrode distance from the perspective of uniformity of the deposited film thickness, if the distance is less than 12 mm, the plasma discharge will concentrate at the center of the electrode or near the outer periphery of the electrode, resulting in an uneven state; desirable.
以上より、絶縁膜膜質に大きな影響を与える電
極間距離の制限は20mm以下ということになる。尚
キヤリアガスとしてN2とH2を主に使用した場
合、膜質及び、プラズマ放電状態は、H2を使用
した実施例1の測定結果とN2を使用した実施例
2の測定結果の中間の特性を示す測定結果が得ら
れた。 From the above, the limit on the distance between the electrodes, which has a large effect on the quality of the insulating film, is 20 mm or less. When N 2 and H 2 are mainly used as the carrier gas, the film quality and plasma discharge state are intermediate between the measurement results of Example 1 using H 2 and the measurement results of Example 2 using N 2 . The measurement results showed that
また、He、Arなどのガスをさらに少量加えた
場合も、ほぼ同じ結果が得られた。 Furthermore, almost the same results were obtained when a smaller amount of gas such as He or Ar was added.
発明の効果
以上説明してきたように容量結合型高周波グロ
ー放電を用いた製造装置の電極間距離を20mm以下
とすることにより、電気的特性の優れた耐圧の高
い高性能絶縁膜を形成できる。Effects of the Invention As explained above, by setting the distance between the electrodes of the manufacturing apparatus using capacitively coupled high-frequency glow discharge to 20 mm or less, a high-performance insulating film with excellent electrical characteristics and high breakdown voltage can be formed.
第1図は容量結合型高周波グロー放電装置の簡
略断面図、第2図は、電圧印加実験に使用した
MIS型トランジスタの断面図、第3図、第7図
は、第1図における電極間距離を、16、20、24、
28mmと変化させたときの絶縁膜のエネルギギヤツ
プを示す図、第4図、第8図は、第1図における
電極間距離dを、16、20、24、28mmと変化させた
ときの絶縁膜の屈折率を示す図、第5図、第9図
は、第2図の構造をしたMIS型トランジスタにお
いて、ゲート・ドレイン両電極に電圧印加した後
のドレイン電流の減少量をグラフにプロツトした
図、第6図、第10図は、評価したい絶縁膜単層
の絶縁破壊電界強度を示す図である。
a……グロー放電室、b……高周波電極、c…
…基板ホルダ、1……ガラス基板、2……ゲート
電極、3……ゲート絶縁膜、4……水素化非晶質
シリコン。
Figure 1 is a simplified cross-sectional view of the capacitively coupled high-frequency glow discharge device, and Figure 2 is the one used in the voltage application experiment.
The cross-sectional views of MIS type transistors, FIGS. 3 and 7, show that the distance between the electrodes in FIG.
Figures 4 and 8 show the energy gap of the insulating film when the distance is changed to 28 mm, and the energy gap of the insulating film is shown when the inter-electrode distance d in Fig. 1 is changed to 16, 20, 24, and 28 mm. The graphs showing the refractive index, Figures 5 and 9, are graphs plotting the amount of decrease in drain current after voltage is applied to both the gate and drain electrodes in the MIS type transistor having the structure shown in Figure 2. FIG. 6 and FIG. 10 are diagrams showing the dielectric breakdown electric field strength of a single layer of an insulating film to be evaluated. a... Glow discharge chamber, b... High frequency electrode, c...
...Substrate holder, 1...Glass substrate, 2...Gate electrode, 3...Gate insulating film, 4...Hydrogenated amorphous silicon.
Claims (1)
して配置された高周波電極および基板ホルダを有
し、前記グロー放電室内にガスが供給されるよう
に構成された容量結合型高周波グロー放電装置を
用いて窒化ケイ素膜または酸化窒化ケイ素膜を形
成するに際し、前記高周波電極と基板ホルダとの
電極間距離を20mm未満とすることを特徴とする絶
縁膜の製造方法。 2 ケイ素原子を含むガスおよび窒素原子を含む
ガス(N2を除く)を使用する窒化ケイ素膜又は
前記二種のガスとN2Oなど酸素原子を含むガス
を使用する窒化酸化ケイ素膜の形成に際し、前記
二種のガス以外にH2を主に使用することを特徴
とする特許請求の範囲第1項に記載の絶縁膜の製
造方法。[Scope of Claims] 1. A capacitively coupled type comprising a glow discharge chamber, a high frequency electrode and a substrate holder disposed facing each other in the glow discharge chamber, and configured such that gas is supplied into the glow discharge chamber. A method for producing an insulating film, characterized in that when forming a silicon nitride film or a silicon oxynitride film using a high-frequency glow discharge device, the distance between the high-frequency electrode and a substrate holder is less than 20 mm. 2. When forming a silicon nitride film using a gas containing silicon atoms and a gas containing nitrogen atoms (excluding N 2 ), or a silicon nitride oxide film using the above two gases and a gas containing oxygen atoms such as N 2 O. 2. The method of manufacturing an insulating film according to claim 1, wherein H 2 is mainly used in addition to the two types of gases.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5875884A JPS60204880A (en) | 1984-03-27 | 1984-03-27 | Production of insulating film |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5875884A JPS60204880A (en) | 1984-03-27 | 1984-03-27 | Production of insulating film |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60204880A JPS60204880A (en) | 1985-10-16 |
JPH0533306B2 true JPH0533306B2 (en) | 1993-05-19 |
Family
ID=13093433
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5875884A Granted JPS60204880A (en) | 1984-03-27 | 1984-03-27 | Production of insulating film |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60204880A (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01309975A (en) * | 1988-06-08 | 1989-12-14 | Matsushita Electric Ind Co Ltd | Plasma cvd device |
JP2700208B2 (en) * | 1988-09-08 | 1998-01-19 | 住友電気工業株式会社 | Thin film formation method |
JP2719183B2 (en) * | 1989-04-06 | 1998-02-25 | 住友電気工業株式会社 | Thin film forming equipment |
JP2719184B2 (en) * | 1989-04-06 | 1998-02-25 | 住友電気工業株式会社 | Thin film formation method |
EP0608633B1 (en) * | 1993-01-28 | 1999-03-03 | Applied Materials, Inc. | Method for multilayer CVD processing in a single chamber |
JP2752582B2 (en) * | 1994-05-20 | 1998-05-18 | 株式会社フロンテック | Electronic element and manufacturing method thereof |
US5665640A (en) * | 1994-06-03 | 1997-09-09 | Sony Corporation | Method for producing titanium-containing thin films by low temperature plasma-enhanced chemical vapor deposition using a rotating susceptor reactor |
-
1984
- 1984-03-27 JP JP5875884A patent/JPS60204880A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS60204880A (en) | 1985-10-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7884035B2 (en) | Method of controlling film uniformity and composition of a PECVD-deposited A-SiNx : H gate dielectric film deposited over a large substrate surface | |
US7754294B2 (en) | Method of improving the uniformity of PECVD-deposited thin films | |
KR100335135B1 (en) | Method of forming silicon oxide layer and method of manufacturing thin film transistor thereby | |
US6355943B1 (en) | Thin film transistor, method of producing the same, liquid crystal display, and thin film forming apparatus | |
US20110095402A1 (en) | Gate dielectric film with controlled structural and physical properties over a large surface area substrate | |
US20170162678A1 (en) | Multilayer passivation or etch stop tft | |
JPH0533306B2 (en) | ||
Batey et al. | Plasma-enhanced CVD of high quality insulating films | |
US6639279B1 (en) | Semiconductor transistor having interface layer between semiconductor and insulating layers | |
KR19980038871A (en) | Thin film transistor using pseudo diamond and manufacturing method thereof | |
JPH08242005A (en) | Amorphous silicon thin film transistor and its manufacture | |
JPH0351094B2 (en) | ||
US6441466B1 (en) | Method and apparatus for reducing fixed charge in semiconductor device layers | |
JP3119988B2 (en) | Method for manufacturing semiconductor device | |
Jung et al. | Electrical properties of ultra-thin oxynitrided layer using N2O plasma in inductively coupled plasma chemical vapor deposition for non-volatile memory on glass | |
JP3340407B2 (en) | Insulating coating and semiconductor device | |
KR970000467B1 (en) | Gate insulator film of semiconductor device | |
JP3340429B2 (en) | Semiconductor device | |
JP3340406B2 (en) | Method for manufacturing semiconductor device | |
JP3120079B2 (en) | Insulating coating and semiconductor device | |
JP3340425B2 (en) | Method for manufacturing semiconductor device | |
Kang et al. | Characteristics of room temperature silicon nitride deposited by internal inductively coupled plasma chemical vapor deposition | |
He et al. | Channel Layer Surface Modifications in a-Si: II thin Film Transistors With Oxide/Nitride Dielectric Layers | |
JP3564505B2 (en) | Method for manufacturing semiconductor device | |
JP3367946B2 (en) | Method for manufacturing semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
EXPY | Cancellation because of completion of term |