US20090089540A1 - Processor architecture for executing transfers between wide operand memories - Google Patents
Processor architecture for executing transfers between wide operand memoriesInfo
- Publication number
- US20090089540A1 US20090089540A1 US11/982,202 US98220207A US2009089540A1 US 20090089540 A1 US20090089540 A1 US 20090089540A1 US 98220207 A US98220207 A US 98220207A US 2009089540 A1 US2009089540 A1 US 2009089540A1
- Authority
- US
- United States
- Prior art keywords
- memory
- data
- instruction
- operand
- instructions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/982,202 US20090089540A1 (en) | 1998-08-24 | 2007-10-31 | Processor architecture for executing transfers between wide operand memories |
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US9763598P | 1998-08-24 | 1998-08-24 | |
| US09/382,402 US6295599B1 (en) | 1995-08-16 | 1999-08-24 | System and method for providing a wide operand architecture |
| US09/922,319 US6725356B2 (en) | 1995-08-16 | 2001-08-02 | System with wide operand architecture, and method |
| US10/616,303 US7301541B2 (en) | 1995-08-16 | 2003-12-19 | Programmable processor and method with wide operations |
| US11/346,213 US8289335B2 (en) | 1995-08-16 | 2006-02-03 | Method for performing computations using wide operands |
| US11/982,202 US20090089540A1 (en) | 1998-08-24 | 2007-10-31 | Processor architecture for executing transfers between wide operand memories |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US11/346,213 Continuation US8289335B2 (en) | 1995-08-16 | 2006-02-03 | Method for performing computations using wide operands |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US20090089540A1 true US20090089540A1 (en) | 2009-04-02 |
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| US11/982,202 Abandoned US20090089540A1 (en) | 1998-08-24 | 2007-10-31 | Processor architecture for executing transfers between wide operand memories |
| US11/982,106 Expired - Fee Related US7889204B2 (en) | 1995-08-16 | 2007-10-31 | Processor architecture for executing wide transform slice instructions |
| US11/982,124 Expired - Fee Related US7940277B2 (en) | 1998-08-24 | 2007-10-31 | Processor for executing extract controlled by a register instruction |
| US12/986,412 Abandoned US20110107069A1 (en) | 1995-08-16 | 2011-01-07 | Processor Architecture for Executing Wide Transform Slice Instructions |
| US13/354,214 Expired - Fee Related US8269784B2 (en) | 1998-08-24 | 2012-01-19 | Processor architecture for executing wide transform slice instructions |
| US13/584,235 Expired - Fee Related US8812821B2 (en) | 1998-08-24 | 2012-08-13 | Processor for performing operations with two wide operands |
Family Applications After (5)
| Application Number | Title | Priority Date | Filing Date |
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| US11/982,106 Expired - Fee Related US7889204B2 (en) | 1995-08-16 | 2007-10-31 | Processor architecture for executing wide transform slice instructions |
| US11/982,124 Expired - Fee Related US7940277B2 (en) | 1998-08-24 | 2007-10-31 | Processor for executing extract controlled by a register instruction |
| US12/986,412 Abandoned US20110107069A1 (en) | 1995-08-16 | 2011-01-07 | Processor Architecture for Executing Wide Transform Slice Instructions |
| US13/354,214 Expired - Fee Related US8269784B2 (en) | 1998-08-24 | 2012-01-19 | Processor architecture for executing wide transform slice instructions |
| US13/584,235 Expired - Fee Related US8812821B2 (en) | 1998-08-24 | 2012-08-13 | Processor for performing operations with two wide operands |
Country Status (4)
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120191925A1 (en) * | 2011-01-12 | 2012-07-26 | Sony Corporation | Memory access control circuit, prefetch circuit, memory device and information processing system |
| WO2013090389A1 (en) * | 2011-12-16 | 2013-06-20 | Mips Technologies, Inc. | Vector size agnostic single instruction multiple data (simd) processor architecture |
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Also Published As
| Publication number | Publication date |
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| EP2241968B1 (en) | 2012-06-27 |
| US20090113187A1 (en) | 2009-04-30 |
| EP2241968A2 (en) | 2010-10-20 |
| ATE467171T1 (de) | 2010-05-15 |
| US20090106536A1 (en) | 2009-04-23 |
| US20110107069A1 (en) | 2011-05-05 |
| US7889204B2 (en) | 2011-02-15 |
| EP2241968A3 (en) | 2010-11-03 |
| US8269784B2 (en) | 2012-09-18 |
| US20120311303A1 (en) | 2012-12-06 |
| DE69942339D1 (de) | 2010-06-17 |
| US8812821B2 (en) | 2014-08-19 |
| US20120117441A1 (en) | 2012-05-10 |
| US7940277B2 (en) | 2011-05-10 |
| ATE557342T1 (de) | 2012-05-15 |
| ATE557343T1 (de) | 2012-05-15 |
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