US20080288687A1 - Information processing device and processor - Google Patents
Information processing device and processor Download PDFInfo
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- US20080288687A1 US20080288687A1 US12/176,714 US17671408A US2008288687A1 US 20080288687 A1 US20080288687 A1 US 20080288687A1 US 17671408 A US17671408 A US 17671408A US 2008288687 A1 US2008288687 A1 US 2008288687A1
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- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 230000000903 blocking effect Effects 0.000 claims description 37
- 238000010586 diagram Methods 0.000 description 16
- 230000002093 peripheral effect Effects 0.000 description 14
- 238000012545 processing Methods 0.000 description 10
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- 238000013461 design Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 230000004044 response Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
- G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
- G06F12/1441—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a range
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
- G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
Definitions
- the memory writing 850 from the image input section 810 , and the memory writing 852 from the image processor section 820 must be performed in parallel. Therefore, switching must be performed to prevent conflicts arising from both accesses ( 850 and 852 ) to the memory area (at the same time).
- FIG. 11 is a memory map of the system shown in FIG. 10 .
- the section shown in area 910 is the area for the memory 830 .
- the image input section 810 In order to operate the image input section 810 and the image processor section 820 in parallel and avoid conflicts in the memory area, the image input section 810 must write in area 921 of area 910 and the image processor section 820 must write in area 920 thereof within a time period T. In the same way, the respective areas 922 and 921 must be written in T+1, and the areas 920 and 922 must be written in T+2.
- the present invention therefore, has the object of providing a device to detect and block illegal address accessing with a small circuit overhead.
- the unique features of the present invention to achieve this and other objects will become apparent from the description provided in the present specification and the accompanying drawings.
- the first illegal address blocking circuit contains a range setting register that is set with an address prohibit range.
- FIG. 1 is a simplified view of the overall system structure of the present embodiment. Though there are no particular restrictions, the components are all formed on one semiconductor substrate.
- the reference numeral 100 denotes the system bus within the processor, and it is composed of control lines, data lines and address lines shared by multiple devices.
- the reference numerals 110 and 120 denote bus master devices for accessing other devices via the system bus 100 .
- the reference numeral 130 denotes a slave device for accepting requests via the system bus 100 of the master devices 110 , 120 and sending back responses to the system bus 100 .
- the example for this system configuration comprises two bus master devices made up of an audio processing IP and an image processing IP.
- the respective processing results from these bus master devices are written into the slave device constituting the serial interface.
- FIG. 2 is a diagram showing the connections of the system bus 100 itself, as well as the interconnections between the system bus 100 and the connecting lines 114 , 124 , and 131 .
- the connecting line 114 connecting the bus master device 110 and the system bus 100 is composed of a request control line 210 , a read/write enable signal line 211 , an address line 212 , a write data line 213 , and a read data line 214 .
- an “H” here indicates a request and an “L” indicates no request.
- the read/write enable signal line 211 identifiers a read request with a “H” and a write request with an “L”, and the address line 212 provides the address for reading/writing.
- the write data is output from the write data line 213 .
- the data is input from the read data line 214 .
- the connecting line 124 that connects the bus master device 120 to the system bus 100 has the same structure as the connecting line 114 .
- the request control lines 210 through 214 respectively correspond in function to the lines 220 through 224 .
- the connecting line 131 which connects the slave device 130 with the system bus 100 , is composed of a request control line 230 , a read/write enable signal line 231 , an address line 232 , a write data line 233 , and a read data line 234 .
- an output from the request control line 210 is conveyed to the request control line 230 .
- Data from the write data line 233 is input to the slave device via the connecting line 131 , or data is output to the read data line 234 .
- FIG. 3 is a schematic diagram showing the illegal address access blocking circuit 113 contained in the bus master device 110 of the present invention.
- the illegal address access blocking circuit 123 contained in the bus master device 120 is identical in structure.
- the signal lines 310 through 314 comprise the connecting line 112 , and they respectively correspond to the signal lines 210 through 214 that comprise the connecting line 114 to the bus.
- the reference numeral 320 denotes an illegal address access detector.
- the bus master device 110 along with the registers 321 and 322 constitute the range setting register that sets the address range for accessing the slave device 130 .
- the upper limit value of the address range within which access to the bus master device 110 is allowed is stored in the register 321 and the lower limit value is stored in the register 322 .
- these registers can be set by way of the control line 112 . These registers may also be set by software processing when the power is turned on, or they may be set automatically when it is detected that the power has been turned on.
- the registers 321 , 322 as well as the comparators 323 , 326 are one set. Needless to say, however, when there are many slave devices, the number of registers and comparators can be increased according to the number of slave devices. Also, the address locations within the registers 321 , 322 may be configured to store all bits representing the address, or they may be configured to store only a portion. In other words, these can be set within a range where access control is needed.
- FIG. 4 is a timing chart showing the operation which is carried out when normal address accessing and illegal address accessing have occurred in a processor having an illegal address access blocking function.
- the reference numerals 700 and 710 in the figure indicate one clock period. During this period, the request control signals 310 , 210 , the address line 312 , as well as the internal signals 325 , 326 , 327 of the illegal address access blocking device 320 transition to different states.
- the value 701 of address line 312 is within the range set in the registers 321 , 322 .
- the signals 325 , 326 are set to “H” at this time, and the signal 327 also is set to “H”. Therefore, a signal level of request control signal 310 equivalent to “H” is also output to the request control line 210 .
- An illegal address access blocking device of this type can be implemented with a small number of circuits comprising a minimum structure made up of two registers, two comparators, and two AND gates per a bus master device, such as one peripheral IP. This illegal address access blocking device also will prevent product defects due to software bugs and provides early detection.
- FIG. 5 through FIG. 7 show another embodiment of the present invention.
- This embodiment utilizes a switching type (On-chip Star Topological Network) as the system bus structure.
- This switching type bus structure (On-chip Star Topological Network), for example, has a structure where the connections between the bus master device and slave device are controlled by a selector. Utilizing this type of structure allows the system bus to operate at higher speeds.
- a switching type bus structure On-chip Star Topological Network
- This type of structure has a structure where the connections between the bus master device and slave device are controlled by a selector. Utilizing this type of structure allows the system bus to operate at higher speeds.
- the sections of the embodiment differing from the first embodiment will be described. Needless to say, the items described for the first embodiment are also applicable to the second embodiment.
- FIG. 5 is a diagram showing a simplified form of the system structure as applied to the present invention.
- the reference numeral 400 denotes a switching type system bus (On-chip Start Topological Network) within the processor.
- the reference numerals 410 and 420 denote the bus master devices, and 430 denotes the slave device.
- the bus master devices 410 , 420 and the slave device 430 are respectively connected to the system bus 400 by the connecting lines 411 , 421 , and 431 . This method, as with the first embodiment, applies no restrictions on the type or number of connected devices.
- FIG. 6 is a diagram showing connections of the system bus 400 itself and the connections between the system bus 400 and the connecting lines 411 , 421 and 431 .
- the connecting line 411 connecting the system bus 400 and the bus master device 410 is composed of a request control line 510 , a read/write enable signal line 511 , an address line 512 , a write data line 513 , a read data line 514 , and a (request) acceptance notification line 515 .
- the description of the lines 510 through 514 matches the lines 210 through 214 in the first embodiment.
- the signal line 515 indicates whether or not a request from the request control line 510 was accepted.
- the connecting line 421 connecting the system bus 400 and the bus master device 420 has a structure identical to the connecting line 411 .
- the connecting line 431 connecting the slave device 430 with the system bus 400 is composed of a request control line 530 , a read/write enable signal line 531 , an address line 532 , a write data line 533 , and a read data line 534 .
- the description of each signal line is the same as the lines 230 through 234 of the first embodiment.
- Reference numeral 540 denotes the request signal selector (switch).
- the request control lines 510 , 520 , and the address lines 512 , 522 are input to the request signal selector (switch) 540 , and the selector control signal lines 541 , 542 , and 543 , as well as the request control line 530 signals, are output from this selector (switch) 540 .
- the selector control signal line 543 is “L”
- the read/write enable signal line 511 signal is then output to the read/write enable signal line 531 .
- the signal from the selector control signal line 543 is “H”
- the signal from control line 521 is output to the control line 531 .
- the signals on line 512 or 522 are output along address line 532 according to the state of the selector control signal line 542 , or the signals on address 513 and 523 are respectively output along the data line 533 according to the state of the selector control signal 541 in the same way.
- the connections between the bus master device 410 , 420 and the slave device 430 are switched in this way. This type of configuration allows the system bus 400 to operate at high speed.
- the reference numeral 610 identifies the illegal address access detector.
- the reference numerals 611 and 612 respectively identify the registers for that detector circuit and reference numerals 613 , 614 identify the comparators.
- the circuit of this illegal address access detector is the same as that of the illegal address access detector 320 of the first embodiment.
- the signal line 617 is set to an “H” value.
- the register 611 and the register 612 can also read/write values by way of the signal line 411 .
- the processor PC carries out external access by using an external bus interface circuit EXIF that is connected to the bus state controller 5 by way of the processor internal main network (or internal bus IBUS).
- the external bus interface circuit EXIF is connected to the external memory MEM.
- the bus state controller BSC outputs strobe signals RAS, CAS and a write enable signal WE to the memory MEM installed externally.
- the processor internal main network (or internal bus IBUS) is the bus type (network typology).
- the illegal address access blocking circuit (IABU) of the present invention is therefore installed in the CPU, direct memory access controller DMAC, dedicated image processor IP (device) MPEG4, or dedicated audio processor IP (device) MP3 that make up the bus master device. Illegal address accessing can therefore be blocked with a small number of circuits, product defects due to software bugs can be prevented, and early stage detection can be achieved.
- processor internal main network or internal bus IBUS
- illegal accessing can be prevented by installing an illegal address access blocking circuit in the processor internal main network (IBUS), and there is no need to install illegal address access blocking circuits in the direct memory access controller DMAC (and other circuit in the bus master device) so that the required circuits surface area can be reduced.
- the circuits for all types of devices are pre-designed and stored as an IP in design tools. Then, during the actual circuit design stage, these devices that are stored in the design tools and which are needed to make the required product can be combined to create an LSI circuit.
- the illegal address access blocking circuit of the present invention can be stored as one IP in the design tool. In this way, the stored illegal address access blocking circuit can be connected easily between each device and the system bus.
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Abstract
A semiconductor device including: a first slave device; a first master device outputting a first request control signal and a first access address signal; a second master device outputting a second request control signal and a second access address signal; a system bus connected to the first slave device, the first master device and the second master device, and selecting and outputting either the first request control signal or the second request control signal when the first request control signal is outputted from the first master device and the second request control signal is outputted from the second master device; and a range setting register holding an address range of which an access of the first master device is permitted, wherein the system bus blocks the first request control signal if the first access address signal is out of the address range.
Description
- This is a continuation of U.S. application Ser. No. 10/838,240, filed May 5, 2004. This application relates to and claims priority from Japanese Patent Application No. 2003-127638, filed on May 6, 2003. The entirety of the contents and subject matter of all of the above is incorporated herein by reference.
- The present invention relates to information processing devices and, in particular, to processors utilized in central processing devices in computers.
- Modern processors, especially in microcomputers built into equipment, utilize a system with a one chip processor made up of a CPU for general processing tasks and a multiple peripheral IP for special processing tasks all mounted on a single chip. This type of system typically has a structure where multiple devices, such as the CPU and the peripheral IP, are connected to a bus within a processor. These types of systems, in particular, contain multiple bus master devices for issuing access requests to the bus.
- The bus master device in a processor containing a CPU sometimes accesses the bus unintentionally due to: (1) software bugs, (2) hardware bugs, and (3) temporary hardware problems (such as software errors on the α line). This type of access is called illegal address accessing. Product defects due to software bugs caused by illegal address accessing are especially numerous in built-in equipment applications.
- To illustrate those cases in an application of the present invention where illegal address accessing has occurred, an example will be considered here which involves a system with multiple bus masters for image input and processing. The system structure is shown in
FIG. 10 . Here, thereference numeral 810 denotes the image input section and numeral 830 denotes the memory. Theimage input section 810 and thememory 830 are both connected to thesystem bus 800. Theimage input section 810, for example, loads images from a camera and stores that data in thememory 830 by operating a bus master. The numeral 850 indicates the flow of data during that operation. - The
reference numeral 820 denotes the image processor section for performing color correction and noise elimination. Theimage processor section 820 loads image data from thememory 830 and writes back the processing results. Thenumerals - The memory writing 850 from the
image input section 810, and the memory writing 852 from theimage processor section 820 must be performed in parallel. Therefore, switching must be performed to prevent conflicts arising from both accesses (850 and 852) to the memory area (at the same time). -
FIG. 11 is a memory map of the system shown inFIG. 10 . The section shown inarea 910 is the area for thememory 830. In order to operate theimage input section 810 and theimage processor section 820 in parallel and avoid conflicts in the memory area, theimage input section 810 must write inarea 921 ofarea 910 and theimage processor section 820 must write inarea 920 thereof within a time period T. In the same way, therespective areas areas - The above-mentioned memory area switching which is employed to avoid conflicts in the memory area is especially important in systems having multiple bus masters. When conflicts in the memory area occur, for example, due to control software bugs, the problem occurs that image data cannot be processed correctly.
- The CPU core typifying the bus master device contains a device called the MMU (Memory Management Unit). The MMU both detects and blocks illegal address accessing. However, the peripheral IP generally does not contain an MMU. A typical MMU used here with a peripheral IP also converts virtual addresses within the CPU core into actual addresses so that using the MMU for blocking illegal address accessing requires a large overhead in terms of the number of circuits and the software overhead to handle these circuits. The MMU therefore cannot be used for detecting and blocking illegal address accessing from a peripheral IP.
- The present invention, therefore, has the object of providing a device to detect and block illegal address accessing with a small circuit overhead. The unique features of the present invention to achieve this and other objects will become apparent from the description provided in the present specification and the accompanying drawings.
- A brief description of a typical embodiment of the invention is as follows. An information processing device has a first bus master device and a first slave device, and a bus is connected to that first bus master device and first slave device, wherein when the first bus master device accesses the first slave device, a first illegal address blocking circuit detects and blocks illegal access from the first bus master device.
- More preferably, the first illegal address blocking circuit contains a range setting register that is set with an address prohibit range.
- Still more preferably, range setting register is constituted by a first register holding an upper address limit for addresses assigned to the first slave device and a second register holding a lower address limit, and the first illegal address blocking circuit contains a comparator circuit to determine if the address output from the first bus master device is included in the address range defined by the values contained in the first register and the second register.
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FIG. 1 is a block diagram showing the system structure of a first embodiment of the present invention; -
FIG. 2 is schematic diagram showing device connections and the bus configuration of the first embodiment; -
FIG. 3 is a schematic diagram of the illegal address access blocking circuit of the first embodiment; -
FIG. 4 is a timing diagram showing the operation of the illegal address access blocking circuit; -
FIG. 5 is a block showing the system structure of a second embodiment of the present invention; -
FIG. 6 is a schematic diagram showing device connections and the bus structure of the second embodiment; -
FIG. 7 is a schematic diagram of the illegal address access blocking circuit of the second embodiment; -
FIG. 8 is a block diagram of the processor for the illegal address access blocking circuit; -
FIG. 9 is a block diagram of the processor for the illegal address access blocking circuit of the second embodiment; -
FIG. 10 is a block diagram of a system with multiple bus masters; and -
FIG. 11 is a diagram of the memory map for the system shown inFIG. 10 . - Preferred embodiments of the information processing device of the present invention will be described with reference to the accompanying drawings. Though there are no special restrictions, the circuit elements comprising each block of an embodiment are known semiconductor integrated circuits, such as bipolar transistors and CMOS (complementary metal-oxide semiconductor) devices, formed on a single semiconductor substrate of monocrystalline silicon.
- A first embodiment of the present invention is shown in
FIG. 1 throughFIG. 3 . This embodiment utilizes a bus configuration with multiple devices jointly using control lines, data lines and address lines as the system bus structure. -
FIG. 1 is a simplified view of the overall system structure of the present embodiment. Though there are no particular restrictions, the components are all formed on one semiconductor substrate. Thereference numeral 100 denotes the system bus within the processor, and it is composed of control lines, data lines and address lines shared by multiple devices. Thereference numerals system bus 100. Thereference numeral 130 denotes a slave device for accepting requests via thesystem bus 100 of themaster devices system bus 100. - The example for this system configuration comprises two bus master devices made up of an audio processing IP and an image processing IP. In this system, the respective processing results from these bus master devices are written into the slave device constituting the serial interface.
- The present embodiment is also assumed to be a system with two bus master devices and one slave device. However, the method of the present invention is not limited by the type or number of devices. The
reference numerals reference numerals access blocking circuits main circuits lines access blocking circuits system bus 100 via the connectinglines slave device 130 is connected to thesystem bus 100 via the connectingline 131. Though described later, when the bus master device is accessing the slave device, the illegal addressaccess blocking circuits -
FIG. 2 is a diagram showing the connections of thesystem bus 100 itself, as well as the interconnections between thesystem bus 100 and the connectinglines - The connecting
line 114 connecting thebus master device 110 and thesystem bus 100 is composed of arequest control line 210, a read/write enablesignal line 211, anaddress line 212, awrite data line 213, and aread data line 214. - Though there are no particular restrictions on the
request control line 210, an “H” here indicates a request and an “L” indicates no request. When therequest control line 210 is “H”, then the read/write enablesignal line 211 identifiers a read request with a “H” and a write request with an “L”, and theaddress line 212 provides the address for reading/writing. During a write request, the write data is output from thewrite data line 213. During a read request, the data is input from the readdata line 214. - The connecting
line 124 that connects thebus master device 120 to thesystem bus 100 has the same structure as the connectingline 114. Therequest control lines 210 through 214 respectively correspond in function to thelines 220 through 224. - The connecting
line 131, which connects theslave device 130 with thesystem bus 100, is composed of arequest control line 230, a read/write enablesignal line 231, anaddress line 232, awrite data line 233, and aread data line 234. Here for example, an output from therequest control line 210 is conveyed to therequest control line 230. Data from thewrite data line 233 is input to the slave device via the connectingline 131, or data is output to the readdata line 234. -
FIG. 3 is a schematic diagram showing the illegal addressaccess blocking circuit 113 contained in thebus master device 110 of the present invention. The illegal addressaccess blocking circuit 123 contained in thebus master device 120 is identical in structure. The signal lines 310 through 314 comprise the connectingline 112, and they respectively correspond to thesignal lines 210 through 214 that comprise the connectingline 114 to the bus. - The
reference numeral 320 denotes an illegal address access detector. Thebus master device 110 along with theregisters slave device 130. The upper limit value of the address range within which access to thebus master device 110 is allowed is stored in theregister 321 and the lower limit value is stored in theregister 322. Though not specified in the drawing, these registers can be set by way of thecontrol line 112. These registers may also be set by software processing when the power is turned on, or they may be set automatically when it is detected that the power has been turned on. - The
reference numerals 323 and 324, respectively, denote comparators. Thecomparator 323 compares the values of theaddress line 312 and the content of theregister 321. When the value of theaddress line 312 is the larger value, thecomparator 323 outputs an “H” to thesignal line 325. The comparator 324 compares the values of theaddress line 312 and the content of theregister 322. When the value of theaddress line 312 is the smaller value, the comparator 324 outputs an “H” to thesignal line 326. Therefore, thesignal line 327 holding the logic sum of thesignal line 325 and thesignal line 326, outputs an “H” when the value of theaddress line 312 is within the range specified by theregister 321 and theregister 322. - The
reference numeral 330 denotes an illegal address blocking section (circuit). When the output of thecontrol line 327 is “H”, or, in other words, when the value of theaddress line 312 is within the range specified by theregister 321 and theregister 322, then the output from therequest control line 310 is output unchanged to therequest control line 210. Conversely, when the output of thesignal line 327 is “L”, or, in other words, when the value of theaddress line 312 is outside the allowable access range, the output from therequest control line 210 is “L” and illegal address accessing is blocked, even if the output from therequest control line 310 is “H”. The logic seen onsignal line 327 is sent unchanged to thesignal line 315, and the bus master devicemain circuit 111 is notified of the blocking of an illegal address access. Illegal address accessing can be prevented in this way. In the present embodiment, theregisters comparators registers registers comparators registers -
FIG. 4 is a timing chart showing the operation which is carried out when normal address accessing and illegal address accessing have occurred in a processor having an illegal address access blocking function. Thereference numerals address line 312, as well as theinternal signals access blocking device 320 transition to different states. - During the
period 700, thevalue 701 ofaddress line 312 is within the range set in theregisters signals signal 327 also is set to “H”. Therefore, a signal level ofrequest control signal 310 equivalent to “H” is also output to therequest control line 210. - In the
period 701, the value 702 is set to a value higher than the lower limit value set in theregister 322. At this time, thesignal 327 is set to “L” when thesignal 326 is set to “L”. The requestcontrol signal line 210 therefore is set to “L” at therequest control signal 310 setting to “H”, so that illegal address accessing is blocked. There are no particular restrictions on action taken when it is determined that illegal address accessing has occurred. For example, a signal line can notify themaster device 110 of an interrupt, and action then taken by the master device, or the interrupt, can be detected by software and action can be taken. - An illegal address access blocking device of this type can be implemented with a small number of circuits comprising a minimum structure made up of two registers, two comparators, and two AND gates per a bus master device, such as one peripheral IP. This illegal address access blocking device also will prevent product defects due to software bugs and provides early detection.
-
FIG. 5 throughFIG. 7 show another embodiment of the present invention. This embodiment utilizes a switching type (On-chip Star Topological Network) as the system bus structure. This switching type bus structure (On-chip Star Topological Network), for example, has a structure where the connections between the bus master device and slave device are controlled by a selector. Utilizing this type of structure allows the system bus to operate at higher speeds. Hereafter, mainly the sections of the embodiment differing from the first embodiment will be described. Needless to say, the items described for the first embodiment are also applicable to the second embodiment. -
FIG. 5 is a diagram showing a simplified form of the system structure as applied to the present invention. Thereference numeral 400 denotes a switching type system bus (On-chip Start Topological Network) within the processor. Thereference numerals bus master devices slave device 430 are respectively connected to thesystem bus 400 by the connectinglines -
FIG. 6 is a diagram showing connections of thesystem bus 400 itself and the connections between thesystem bus 400 and the connectinglines line 411 connecting thesystem bus 400 and thebus master device 410 is composed of arequest control line 510, a read/write enablesignal line 511, anaddress line 512, awrite data line 513, aread data line 514, and a (request)acceptance notification line 515. The description of thelines 510 through 514 matches thelines 210 through 214 in the first embodiment. Thesignal line 515 indicates whether or not a request from therequest control line 510 was accepted. The connectingline 421 connecting thesystem bus 400 and thebus master device 420 has a structure identical to the connectingline 411. - The connecting
line 431 connecting theslave device 430 with thesystem bus 400 is composed of arequest control line 530, a read/write enablesignal line 531, anaddress line 532, awrite data line 533, and aread data line 534. The description of each signal line is the same as thelines 230 through 234 of the first embodiment. -
Reference numeral 540 denotes the request signal selector (switch). Therequest control lines address lines control signal lines request control line 530 signals, are output from this selector (switch) 540. When the signal from the selectorcontrol signal line 543 is “L”, the read/write enablesignal line 511 signal is then output to the read/write enablesignal line 531. Conversely, when the signal from the selectorcontrol signal line 543 is “H”, the signal fromcontrol line 521 is output to thecontrol line 531. - The signals on
line address line 532 according to the state of the selectorcontrol signal line 542, or the signals onaddress data line 533 according to the state of theselector control signal 541 in the same way. The connections between thebus master device slave device 430 are switched in this way. This type of configuration allows thesystem bus 400 to operate at high speed. -
FIG. 7 is a diagram showing the internal structure of thecontrol circuit 540. Thereference numeral 600 is a decoder which outputs an “H” signal to thesignal line 601 when the value on theaddress line 522 indicates theslave device 430. Therefore, when a request is output to theslave device 430 from thebus master device 420 on thecontrol signal lines - When the address destination indicated by the value on
line 522 does not indicate theslave device 430, then an “L” signal is output to thesignal line 525 and an “H” is output to thesignal line 602. In the opposite case, an “L” is output to thesignal line 602, and an “H” is output on thesignal line 525. - The
reference numeral 610 identifies the illegal address access detector. Thereference numerals reference numerals 613, 614 identify the comparators. The circuit of this illegal address access detector is the same as that of the illegaladdress access detector 320 of the first embodiment. When the value on theaddress line 512 is within the range specified by theregister 611 and theregister 612, thesignal line 617 is set to an “H” value. Theregister 611 and theregister 612 can also read/write values by way of thesignal line 411. - The
reference numeral 620 identifies the illegal address blocking section (or circuit) and is identical to theblocking section 330 of the first embodiment. Theblocking section 620 blocks (masks) therequest control line 510 when the output from thecontrol line 617 is “L”. Illegal address accessing from thebus master device 410 can be blocked in this way. This blocking of thesignal line 602 signal by the output from thesignal line 617 to prevent illegal address accessing is reported to thebus master device 410. Thebus master device 410 receives this notification and performs the necessary processing. - The
bus master devices system bus 400 so that installing the illegal address blocking circuit in the selector control circuit allows it to be implemented in a small surface area.FIG. 8 is an embodiment in which the invention is applied to a specific processor PC. The processor PC contains a CPU (central processing unit) for controlling the entire processor PC. The MMU (Memory Management Unit) converts the virtual address inside the CPU core to a physical address and also contains a function to block illegal address accessing. In the processor PC in the present embodiment, the bus master device is composed of a CPU, a direct memory access controller DMAC, a dedicated image processor IP (device) MPEG4, and a dedicated audio processor IP (device) MP3. The processor PC carries out external access by using an external bus interface circuit EXIF that is connected to the bus state controller 5 by way of the processor internal main network (or internal bus IBUS). The external bus interface circuit EXIF is connected to the external memory MEM. The bus state controller BSC outputs strobe signals RAS, CAS and a write enable signal WE to the memory MEM installed externally. - The processor PC contains a clock pulse generator CPG, an interrupt control circuit INTC, a serial communication interface controller SCI, a real-time clock circuit RTC and a timer TMU, which serve as internal peripheral circuits connected to the processor internal main network (or internal bus IBUS). These peripheral circuits are accessed by the CPU or the direct memory access controller DMAC, or the dedicated image processor IP (device) MPEG4, or the dedicated audio processor IP (device) MP3 by way of the processor internal main network (or internal bus IBUS). A clock signal synchronized with the system clock is output from the clock pulse generator CPG. This processor PC performs operations, such as loading external data, while synchronized with this system clock signal.
- The bus state controller BSC determines the access data size, access time, and wait state according to the circuit for access (address area to be accessed) by the CPU or direct memory access controller DMAC, and it also controls the bus access to the external memory MEM. The bus state controller BSC also arbitrates competing requests for bus use from external sections and from the direct memory access controller DMAC.
- Here, the processor internal main network (or internal bus IBUS) is the bus type (network typology). The illegal address access blocking circuit (IABU) of the present invention is therefore installed in the CPU, direct memory access controller DMAC, dedicated image processor IP (device) MPEG4, or dedicated audio processor IP (device) MP3 that make up the bus master device. Illegal address accessing can therefore be blocked with a small number of circuits, product defects due to software bugs can be prevented, and early stage detection can be achieved. When the processor internal main network (or internal bus IBUS) is of the switch type, illegal accessing can be prevented by installing an illegal address access blocking circuit in the processor internal main network (IBUS), and there is no need to install illegal address access blocking circuits in the direct memory access controller DMAC (and other circuit in the bus master device) so that the required circuits surface area can be reduced.
- In circuit design in recent years, the circuits for all types of devices (such as CPU and DMAC) are pre-designed and stored as an IP in design tools. Then, during the actual circuit design stage, these devices that are stored in the design tools and which are needed to make the required product can be combined to create an LSI circuit. In this case, the illegal address access blocking circuit of the present invention can be stored as one IP in the design tool. In this way, the stored illegal address access blocking circuit can be connected easily between each device and the system bus.
-
FIG. 9 is a block diagram of a processor representative of the second embodiment of the present invention. This drawing differs fromFIG. 8 in that a processor internal peripheral network (or PBUS) is connected to the peripheral circuit (slave device) separate from the processor internal main network (IBUS). The processor internal peripheral network (PBUS) and processor internal main network (IBUS) are connected by way of a bus state controller BSC. Using this type of structure allows the peripheral circuits that constitute the slave device to connect to the bus master device by way of a bus state controller containing a direct memory access controller DMAC. The processor PC inFIG. 8 has a structure where the peripheral circuits are directly accessed by way of the processor internal main network (IBUS) so, that the illegal address access blocking circuit must be installed in each slave device within each bus master device. However, in the present embodiment, the peripheral circuit is connected to the bus master device by way of the bus state controller so that the illegal address access blocking circuits can be concentrated in the bus state controller and, therefore, take up a smaller area than the processor PC inFIG. 8 . - The present invention was described will reference to specific embodiments, however a range of diverse adaptations are possible without departing from the objects of the invention. For example, the values indicating the address range can be hardwired in without installing a register.
Claims (7)
1. A semiconductor device comprising:
a first slave device;
a first master device outputting a first request control signal from the first master device to the first slave device and a first access address signal assigned to the first slave device when the first master device accesses to the first slave device;
a second master device outputting a second request control signal from the second master device to the first slave device and a second access address signal assigned to the first slave device when the second master device accesses to the first slave device;
a system bus connected to the first slave device, the first master device and the second master device, and selecting and outputting either the first request control signal or the second request control signal when the first request control signal is outputted from the first master device and the second request control signal is outputted from the second master device; and
a range setting register holding an address range of which an access of the first master device is permitted,
wherein the system bus blocks the first request control signal if the first access address signal is out of the address range.
2. The semiconductor device according to claim 1 ,
wherein the range setting register comprises a first register to hold an upper limit address, and a second register holding a lower limit address assigned to the first slave device, and
wherein the system bus includes a comparator to compare whether the address outputted by the first master device is within the range shown in the first register and the second register.
3. The semiconductor device according to claim 1 ,
wherein the system bus comprises a selector for switching the connection states of the first slave device, the first master device and the second master device, and a selector control circuit for controlling the selector.
4. The semiconductor device according to claim 1 ,
wherein the system bus comprises a first illegal address access blocking circuit to detect and block illegal access by the first master device during accessing of the first slave device.
5. The semiconductor device according to claim 4 ,
wherein the first illegal address access blocking circuit further detects and blocks illegal access by the second master device during accessing of the first slave device by the second master device.
6. The semiconductor device according to claim 1 , comprising:
a second slave device connected to the system bus,
wherein the system bus comprises a second illegal address access blocking circuit to detect and block illegal access by the first master device during accessing of the second slave device.
7. The semiconductor device according to claim 1 ,
wherein an information held in the range setting register is rewritable by the first master device.
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US15/791,687 US10289569B2 (en) | 2003-05-06 | 2017-10-24 | Information processing device and processor |
US16/397,358 US10983924B2 (en) | 2003-05-06 | 2019-04-29 | Information processing device and processor |
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US20180046587A1 (en) | 2018-02-15 |
US10289569B2 (en) | 2019-05-14 |
JP2004334410A (en) | 2004-11-25 |
US10983924B2 (en) | 2021-04-20 |
US20110016244A1 (en) | 2011-01-20 |
US7404054B2 (en) | 2008-07-22 |
US20190251041A1 (en) | 2019-08-15 |
US9798679B2 (en) | 2017-10-24 |
US20040225768A1 (en) | 2004-11-11 |
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