JP2002334068A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the exclusiveness guarantee and availability of I/O access by a multiprocessor or multi-computer system. SOLUTION: Processors A and B and a common I/O 3 are connected by a common bus and the common I/O is provided with a semaphore variable 16 for access to data of the common I/O by the processor 5 or 6; when the semaphore variable is 0 (initial state), it is considered that neither of the processors 5 and 6 accesses the common I/O, so the data buffer access in this state is inhibited. Further, access violating access restrictions is monitored through access monitoring 20 and error information is written in an error register 19.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a computer system, and more particularly to an exclusive processing method for I / O resources. Further, the present invention relates to an electron beam lithography apparatus using the I / O.

[0002]

2. Description of the Related Art In a computer system, a so-called multiprocessor system or multicomputer system in which a plurality of processors and a plurality of computers perform parallel processing, that is, a parallel processing by a plurality of processors and a plurality of computers, is effective in realizing arithmetic processing and high speed processing of a large amount of data. In addition, if a redundant component can be easily replaced with a normal component by making the system component redundant, system availability (Avai
lability) is improved.

One of the problems in a multiprocessor system arises when multiple processors access hardware resources commonly used (read, input, or write data). Here, the problematic common hardware resource is an I / O for exchanging input / output data. Generally, the input / output data of each processor cannot be exchanged with the outside unless the order and the amount of data are separated according to a certain rule. To solve this problem, semaphores (Se
A technique for preparing variables called maphore is known as computer software technique. The semaphore variables guarantee the exclusiveness of the I / O access of each processor.

FIG. 12 shows a conventional data processing apparatus.
The data processing device (computer system) includes two processors 202 and 203, a memory 204, and a shared I / O.
205, each of which is connected to a common bus 207 to exchange data. When the processor 202 and the processor 203 access the common I / O 205, the semaphore variable 206 prepared on the memory is used to guarantee the exclusiveness.

[0005] Here, for example, 0 is set as the initial value of the semaphore variable, the processor that reads 0 is regarded as being permitted the I / O access, and the processor that reads a value other than 0 is not permitted the I / O access. Is considered.

FIG. 2 shows a general procedure (semaphore procedure) for assuring exclusivity using semaphore variables. When the processor 202 attempts to access the common I / O 205, the semaphore variable is read before the access (S1).
01), it is determined whether the value can be accessed. If 0 has been read (S102), the value of the semaphore is immediately rewritten to 1 (S103). Then, necessary data buffer access to the common I / O is performed (S104). After the access is completed, the processor 202 writes the value of the semaphore back to 0 (S105).

On the other hand, the processor 202 reads the semaphore variable, and if the value is 1 (S102), the data buffer access is not performed until the value becomes 0.

[0008] By performing the above semaphore procedure also by the other processor 203, appropriate exclusiveness of data input / output can be maintained.

However, this method has some problems. First, between the operation of rewriting the semaphore value to 1 (S103) and the operation of semaphore read ahead (S101), the other processor must not perform semaphore read (inseparable semaphore access). For this guarantee, the computer system must provide special operation.

Second, each processor accesses a shared semaphore variable. Usually, however, the memory is exclusively protected on a region-by-region basis, that is, the memory is not shared and the reliability of the system is generally improved. Often cause management problems.

Another example of the prior art is disclosed in Japanese Patent Laid-Open No. 11-161625.
There is an official gazette. Here, as one of the methods for solving these problems, a configuration having a semaphore rewrite logic in an I / O device is shown.

[0012]

However, the prior art is not enough to solve the above problems. If the semaphore procedure is ignored due to a program error or a thermal runaway of the processor, the exclusivity is easily destroyed. Unless such abnormal operation is detected, the availability cannot be improved by redundancy.

An object of the present invention is to provide a data processing apparatus capable of overcoming the above-mentioned problems which cannot be solved by the prior art, realizing exclusive protection of data input / output and detecting abnormal operation, and a shared I / O device.
/ O. Another object of the present invention is to provide an electron beam drawing apparatus to which the present invention is applied.

[0014]

In order to achieve the above object, the present invention provides a data processing apparatus having a plurality of processors and a shared I / O, wherein the shared I / O has a variable, and the plurality of processors are A variable is accessed as a semaphore variable, and the shared I / O suppresses improper access to input / output data by at least the value of the semaphore variable. The shared I / O monitors whether a shared I / O access violating at least an access restriction determined by a value of the semaphore variable is performed,
Violating access is detected as abnormal.

Alternatively, the shared I / O has a variable in which an initial value is assigned a predetermined value and a change value is assigned to each processor, and the plurality of processors access the variable as a semaphore variable, and O monitors whether a shared I / O access violating the access restriction determined by at least the value of the semaphore variable is performed, and if there is a violating access, detects the corresponding processor as abnormal from the change value. It is characterized by.

The shared I / O determines whether the access from the processor is a semaphore variable access if the access is a semaphore variable access. If the access is a variable read, the shared I / O executes the semaphore variable access as it is. When it can be considered that the semaphore access is not performed in the procedure, the semaphore access is not executed, and the error information is written in an error register.

Further, the data processing device may be configured so that the shared I
A plurality of I / Os are connected, the plurality of processing devices are connected to the respective shared I / Os by respective common buses, and input / output of data to / from the shared I / Os can be executed in parallel.

The present invention also relates to an I / O device,
A variable, which is accessible as a semaphore variable from a plurality of external processors, and monitors whether an I / O data access that violates at least an access restriction determined by a value of the semaphore variable is performed. Then, the violating I / O data access is detected as abnormal.

Further, in an electron beam drawing apparatus used for manufacturing a semiconductor integrated circuit, comprising a host computer, a data processing device, a drawing control section, and an electron beam drawing control section main body, the data processing apparatus includes: One of the described data processing devices is used.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of the data processing device according to the first embodiment. The processing device (A) 1, the processing device (B) 2, and the shared I / O 3 are communicably connected by a common bus 4. Each of the processing devices 1 and 2 is composed of functional components of the same semiconductor integrated circuit, and includes processors 5 and 6, memories 7 and 8, and bridges 9 and 10.

The processors 5 and 6 are generally called microprocessors, and the memories 7 and 8 are memory modules having a capacity of, for example, 128 megabytes or 256 megabytes. The bridges 9 and 10 bridge the communication between the two connected buses 11 and 4, and 12 and 4, and are also called bus bridges. Thus, each processor has access to its own memory and shared I / O.

Also, while one of the processing units is performing the shared I / O access, the other processing unit can access the memory and perform efficient parallel processing. Further, the bridges 9 and 10 have functions 13 and 14 for performing an inseparable semaphore access operation on the shared I / O 3.

The shared I / O 3 has a data buffer 18 for exchanging data with the outside of the system. The data buffer 18 buffers (temporarily stores) input / output data through the common bus 4 and the access control unit 21.

The shared I / O 3 further includes a semaphore variable 16
have. The semaphore variable 16 is connected to the access control unit 21 inside the I / O, and is read from the processing devices 1 and 2 via the common bus 4 or rewritten by a write-back operation. The function of the access restriction 17 restricts access to the data buffer 18 that violates the value of the semaphore variable, thereby inhibiting execution.

The operation of this embodiment will be described in more detail. The semaphore procedure performed by the processing devices A and B on the shared I / O 3 is the same as the conventional one, as shown in FIG. Then, the shared I / O side of this embodiment is operated by the access control unit 21 as follows.

When the shared I / O receives an access request from the processing device, if the value of the semaphore variable is 0, the processor should not access the shared I / O. Access to the data buffer 18 is prohibited. More specifically, even if there is an access request, the contents of the data buffer 18 are not changed. Or data transfer function (DM
A: Direct Memory Access), and when data transfer is activated by a command from the processor, the activation may be suppressed.

The shared I / O 3 is provided in the error register 19
Having. The function of the access monitor 20 of the access control unit 21 is that the data buffer 18 violates the value of the semaphore variable.
Is detected, and the error information is written into the error register 19. The method of judging a violation is the same as that included in the function of the access restriction 17 and can be used in common.

The error register 19 is read out to the processing units 1 and 2 via the access control unit 21 in the I / O and the common bus 4 so that it is possible to know the occurrence of an abnormality.
Note that an interrupt notification unit may be provided for any of the processors to notify an abnormality.

The detailed processing procedure performed by the access control unit 21 in the shared I / O will be described below with reference to the flowcharts of FIGS. When an access request to the shared I / O 3 is detected (S201), if the access is to a semaphore variable (S202), a semaphore variable access (read or write) is executed (S207). If it is a data buffer access (S203), a data buffer access response operation is performed (S206). In the case of error register access (S204), error register access (read,
Or writing) (S205).

FIG. 4 shows details of the data buffer access response operation. In the data buffer access, if the semaphore variable is not 0 (S302), the data buffer access is executed (S303). On the other hand, if the semaphore variable is 0 (S302), the data buffer access is not executed, and it is determined that an error in the semaphore procedure has been detected.
The error information is written in No. 9 (S304).

According to this embodiment, the data buffer access is not executed without any processor performing the semaphore procedure to be performed at the time of data buffer access.

Next, a second embodiment of the present invention will be described with reference to FIGS. In the second embodiment, a more detailed procedure error is detected by using 0 and a value (device information) unique to each processor, instead of using 0 and 1 as the values of the semaphore variables.

FIG. 5 shows the configuration of the data processing device. FIG.
The difference is that the device information 901 is used as a semaphore variable. The device information is 0 as an initial value and a value unique to each processor, for example, the processor 5 of the processing device A.
Is assigned a value “1” in advance, and a value “2” is assigned in advance to the processor 6 of the processing device B.

FIG. 6 shows a semaphore procedure performed by each processor. The difference from FIG. 2 is that each processor uses device information assigned in advance as a value for rewriting a semaphore variable (S103-1). The processing procedure inside the shared I / O is the same as that of FIG. 3, but the data buffer access response operation (S301) shows the detailed procedure in FIG.

FIG. 7 differs from FIG. 4 in that it checks whether the access is from a processor that matches the device information or not (S302-1). If the access is from a processor that matches the device information, the processor is in a permitted state.
The data buffer access is executed (S303). Otherwise, execution is not performed, and error information is written to the error register (S304).

That is, for example, when the value of the semaphore variable is 1, the data buffer access from the processor 5 of the processing device A is executed, but the data buffer access from the processor 6 of the processing device B is not executed. Further, for example, when the value of the semaphore variable is 0, no data buffer access from any of the processors 5 and 6 is executed.

As described above, the semaphore procedure to be performed at the time of accessing the data buffer is not executed by any processor without performing any semaphore procedure, as in the first embodiment. further,
In the second embodiment, it is possible to identify, limit, and detect a procedure error for each processor.

Next, a third embodiment will be described. A method of limiting and detecting an error in a semaphore variable rewriting procedure (inseparable semaphore access processing), which is a modification of the second embodiment, will be described. Here, a semaphore access response operation based on the procedure is executed instead of a simple read / write single operation as in the semaphore variable access execution (S207).

FIG. 8 shows the procedure of the semaphore access response operation. First, it is determined whether a semaphore variable is written (rewritten) (S402). If it is a read operation, semaphore variable access (read) may be executed as it is (S407). On the other hand, in the case of writing, the judgment is divided into a case where it can be regarded as being performed in a regular procedure and a judgment when it is not.

When the semaphore variable is set to 0 (S403),
A semaphore variable access (write) is executed (S407) when a non-zero value is to be written (S404: No), and when a semaphore variable is not 0 and a zero value is to be written (S406: Yes).

When the semaphore variable is 0, the value of 0 is to be written (S404: Yes), and when the semaphore variable is not 0, the value is not 0. When trying to write (S40
6: No), the semaphore variable access is not restricted and executed, and error information is written to the error register as a monitoring result (S405).

According to the third embodiment, it is possible to limit the rewriting in the semaphore variable rewriting procedure and to monitor and detect errors.

Next, a fourth embodiment is shown in FIG. This is a system including three processing devices 301, 302, 303 and two shared I / Os 304, 305.

A common bus 350 connects each of the processing units 301, 302, and 303 to the shared I / O-A 304, and the shared bus from each of the processing units.
/ O-A 304 is enabled. The common bus 351 connects each of the processing devices 301, 302, and 303 to the shared I / O-B 305, and enables each processing device to access the shared I / O-B 305. For example, if the processing device a (301) has shared I / O
-While accessing the A 304, the processing device b (302) can access the shared I / O-B 305. That is, in such a configuration, data input / output can be performed in parallel, and high-speed processing throughput can be realized.

The shared I / O-A 304 and the shared I / O-B 305 perform different purposes and input / output different data, and are, for example, I / O with high-speed communication equipment and industrial control equipment. However, it has the same characteristics as the shared I / O3 shown in FIG.
It has data buffers 339 and 340 for input / output data, semaphore variables 335 and 336, functions of access restrictions 337 and 338, functions of access monitors 343 and 344, and error registers 341 and 342, and stores data according to the present invention. Exclusive input / output protection and abnormal operation detection are realized.

Each processor 301, 302, 303 has two processors 307 and 308, 309 and 310, 311 and 312, and a memory.
313, 314, 315, two bridges 316 and 323, 317 and 32
4, 318 and 325, and local I / Os 319, 320 and 321. Internal buses 326, 327, 328 connect the two processors and bridges 316, 317, 318, and another internal bus 329,
330 and 331 are two bridges 316 and 323, 317 and 324, 318 and 3
25 and local I / Os 319, 320, 321 are connected. Memory 3
13, 314, 315 and bridges 316, 317, 318 are connected in a one-to-one manner, so that the electrical load is suppressed. Local I / O31
Reference numerals 9, 320 and 321 denote serial communication interfaces with a terminal device for performing maintenance for each processing device and interfaces with a storage device having a system program.

As described above, the internal configuration of the processing device is different, the number of the processing devices is three or more, the shared I / O
This indicates that the present invention is applicable even when there are two or more. It is possible to individually protect the exclusiveness of data input / output and detect an abnormal operation for each shared I / O.

Next, an application example of the present invention will be described. FIG.
1 shows a system configuration in which the data processing apparatus of the present invention is applied to an electron beam drawing apparatus. Electron beam lithography systems are used in the manufacture of semiconductor integrated circuits. With the miniaturization of design rules and the increase in the size of silicon chips, future drawing data will not only be enormous, but will also reduce the drawing time. Therefore, high-speed data processing has been desired.
The data processing in the electron beam drawing apparatus is to restore the compressed drawing data or to convert the data into individual data that can be used for control unique to the drawing apparatus and output the converted data.

The electron beam drawing system according to the present embodiment includes a host computer 401, a data processing device 402, a drawing control unit 403,
It comprises an electron beam lithography apparatus main body 404. The data processing device 402 is the same as the device shown in FIG. 9, receives drawing data from the host computer 401, converts the drawing data into unique control data, and outputs it to the drawing control unit 403. The drawing control unit 403 is based on the received control data, and
Is performed.

By applying the present invention, for example, shared I / O
When an abnormality is detected in the access to the B 305, one of the processing devices 301, 302, and 303 notifies the host computer 401. Further, since the two processing devices can process the shared I / OA and B in parallel, the processing throughput can be improved.

FIG. 11 shows a display example on the host computer when an abnormality is detected. An attempt to make a violating access is made by the processing device b (302). If the processing device a (301) and the processing device b (302) are executing data processing in parallel and the processing device c (303) is a redundant standby system, the subsequent data processing is performed by the processing device a (301). And the processing device c (303) can execute them in parallel.

[0052]

According to the present invention, improper access to input / output data is suppressed, and if an access that violates the access restriction is attempted, it is detected as abnormal.
The I / O access is exclusively protected, suppressing abnormal data input / output, and has the effect of improving availability through redundancy.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a data processing device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a semaphore procedure.

FIG. 3 is a flowchart showing a procedure of shared I / O access according to the first embodiment.

FIG. 4 is a flowchart showing a data buffer access response operation according to the first embodiment;

FIG. 5 is a block diagram showing a configuration of a data processing device according to a second embodiment.

FIG. 6 is a flowchart showing a semaphore procedure according to the second embodiment.

FIG. 7 is a flowchart showing a data buffer access response operation according to the second embodiment.

FIG. 8 is a flowchart showing a semaphore variable access response operation according to the third embodiment.

FIG. 9 is a block diagram showing a configuration of a data processing device according to a fourth embodiment.

FIG. 10 is a schematic diagram showing a system configuration of an electron beam drawing apparatus showing an application example of the data processing apparatus of the present invention.

FIG. 11 is an exemplary view showing an error display on a monitor screen when an abnormality is detected.

FIG. 12 is a block diagram of a data processing device showing a conventional technique.

[Explanation of symbols]

1, 2 ... processing device, 3 ... shared I / O, 4 ... common bus,
5, 6 processor, 7, 8 memory, 9, 10 bridge, 16 semaphore variable, 17 access restriction, 18
... data buffer, 19 ... error register, 20 ... access monitoring, 21 ... access control unit.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kimiaki Ando 882, Ichimo, Hitachinaka-shi, Ibaraki F-term in the measuring instrument group of Hitachi, Ltd. (Reference) 5B045 BB12 BB30 EE08 EE19 JJ02 JJ07 JJ09

Claims (7)

[Claims] 1. A data processing apparatus comprising a plurality of processors and a shared I / O, wherein the shared I / O has a variable, the plurality of processors access the variable as a semaphore variable, and
/ O suppresses inappropriate access to input / output data by at least the value of the semaphore variable. 2. A data processing apparatus comprising a plurality of processors and a shared I / O, wherein the shared I / O has a variable, the plurality of processors access the variable as a semaphore variable, and
/ O monitors whether or not shared I / O access that violates the access restriction determined by at least the value of the semaphore variable is performed, and detects the violating access as abnormal. 3. A data processing device comprising a plurality of processors and a shared I / O, wherein the shared I / O has a variable whose initial value is assigned to a predetermined value and whose change value is assigned to each of the processors, The processor accesses the variable as a semaphore variable, and the shared I / O monitors whether at least a shared I / O access that violates an access restriction determined by a value of the semaphore variable is performed. A data processing device characterized by detecting a corresponding processor as an abnormality from the change value, if any. 4. The shared I / O according to claim 3, wherein the shared I / O determines whether the access from the processor is a variable write if the access is a semaphore variable access, and if the access is a variable read, executes the semaphore variable access as it is, In the case of (1), if it is determined that the semaphore access has not been performed, the semaphore access is not performed, and error information is written in an error register. 5. The shared I / O according to claim 1, wherein the shared I / O includes a plurality of the shared I / Os, and the plurality of processing devices and the respective shared I / Os are respectively connected by a common bus.
A data processing device capable of executing data input / output to / from a computer in parallel. 6. A semaphore variable having a variable, wherein the variable is accessible from a plurality of processors, and at least I / O data access violating an access restriction determined by a value of the semaphore variable is not performed. An I / O device that monitors whether the I / O data access is in violation and detects the violation as an error. 7. An electron beam drawing apparatus used for manufacturing a semiconductor integrated circuit, comprising a host computer, a data processing device, a drawing control unit, and an electron beam drawing control unit main body. An electron beam drawing apparatus using the data processing apparatus according to any one of claims 1 to 5.