US20080157391A1 - RF semiconductor devices and methods for fabricating the same - Google Patents

RF semiconductor devices and methods for fabricating the same Download PDF

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US20080157391A1
US20080157391A1 US12/075,338 US7533808A US2008157391A1 US 20080157391 A1 US20080157391 A1 US 20080157391A1 US 7533808 A US7533808 A US 7533808A US 2008157391 A1 US2008157391 A1 US 2008157391A1
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semiconductor device
gate lines
insulating layer
active region
trenches
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US12/075,338
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Yong Guen Lee
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present disclosure relates generally to semiconductor devices; and, more particularly, to radio frequency (RF) semiconductor devices having decreased parasitic capacitance and gate resistance and methods for fabricating the same.
  • RF radio frequency
  • Transistors, inductors, capacitors and varactors are widely used radio frequency (RF) semiconductor devices.
  • RF radio frequency
  • silicon has become widely used in fabricating RF semiconductor devices for the purpose of reducing manufacturing costs.
  • an RF semiconductor device is made of silicon, certain characteristics thereof may be deteriorated.
  • a transistor e.g., a MOSFET
  • Ft, Fmax an operating frequency of the transistor.
  • Factors effecting the operating frequency of MOSFETs include the parasitic capacitance between the gate and the substrate of the MOSFET, the resistance of the gate line, and the like. If the RF MOSFET is produced in a semiconductor manufacturing process, since a greater current, that is, a large transconductance gm of the RF MOSFET is required, the gate width thereof must be enlarged.
  • FIG. 1 shows a top plan view of a conventional RF semiconductor device.
  • FIGS. 2A and 2B are cross-sectional views of the conventional RF semiconductor device taken along lines X-X′ and Y-Y′ shown in FIG. 1 , respectively.
  • a gate line 15 is formed on an active region 10 in a longitudinally elongated zigzag shape.
  • a plurality of contact holes 19 are formed between the zigzags of the gate line 15 .
  • the contact holes are formed at a constant distance from one another.
  • a portion of the gate line 15 is formed over an inactive region, i.e., an element isolation region. Some of the contact holes 19 are also formed on the gate line 15 within the element isolation region.
  • a trench 13 is formed in a semiconductor substrate 11 and then the gate line 15 is formed on the semiconductor substrate 11 .
  • an insulating layer 17 is formed on the semiconductor substrate 11 having the gate line 15 thereon.
  • the insulating layer 17 is then selectively patterned to thereby form the contact holes 19 which expose the semiconductor substrate 11 and the gate line 15 .
  • a first conductive material is deposited on the insulating layer 17 and in the contact holes 19 .
  • the first conductive material is then planarized to thereby form contact plugs 21 .
  • a second conductive material is deposited on the insulating layer 17 and the contact plugs 21 .
  • the second conductive material is then selectively patterned to thereby form a conductive pattern 23 in contact with the contact plugs 21 .
  • the gate line 15 is also formed over the trench 13 beyond the active region 10 .
  • the parasitic capacitance Cgb between the gate line 15 and the trench 13 is increased as indicated at C in FIGS. 2A and 2B .
  • the operating frequency Ft which is one of the important parameters of the RF MOSFET, has a functional relationship with the parasitic capacitance Cgb
  • an increase in the parasitic capacitance Cgb can adversely affect the operating frequency Ft. Specifically, if several (e.g., dozens) of gate fingers are used in order to enlarge the width of the gate line 15 , the parasitic capacitance Cgb will be further increased.
  • FIG. 1 is a top plan view of a conventional RF semiconductor device.
  • FIGS. 2A and 2B are cross-sectional views of the conventional RF semiconductor device of FIG. 1 taken along lines X-X′ and Y-Y′, respectively.
  • FIG. 3 is a top plan view of an example RF semiconductor device.
  • FIGS. 4A and 4B are cross-sectional views of the RF semiconductor device of FIG. 3 taken along lines X-X′ and Y-Y′, respectively
  • FIG. 3 is a top plan view of an example RF semiconductor device.
  • FIGS. 4A and 4B are cross-sectional views of the example RF semiconductor device of FIG. 3 taken along lines X-X′ and Y-Y′, respectively.
  • a plurality of gate lines 35 which are elongated along a longitudinal direction are arranged on an active region 30 of a semiconductor substrate 31 .
  • a substantially constant distance is maintained between the gate lines 35 .
  • a plurality of contact holes 39 are formed between and on the gate lines 35 as shown in FIG. 3 .
  • a substantially constant distance is maintained between the contact holes 39 .
  • the plurality of contact holes 39 are only formed within the active region 30 .
  • a trench 33 is formed in the semiconductor substrate 31 and then the gate lines 35 are formed on the semiconductor substrate 31 .
  • the gate lines 35 are not formed to run along a longitudinal axis of the trench 33 as indicated at B of FIG. 4A .
  • an insulating layer 37 is formed on the semiconductor substrate 31 having the gate lines 35 thereon.
  • the insulating layer 37 is then selectively patterned to thereby form the contact holes 39 which expose the semiconductor substrate 31 and the gate line 35 .
  • the contact holes 39 are only formed within the active region 30 .
  • a first conductive material is then deposited on the insulating layer 37 and in the contact holes 39 .
  • the first conductive material is then planarized to thereby form contact plugs 41 .
  • a second conductive material is deposited on the insulating layer 37 and the contact plugs 41 .
  • the second conductive material is then selectively patterned to thereby form a conductive pattern 43 contacting the contact plugs 41 .
  • some of the contact holes 39 are formed on the gate lines 35 .
  • the gate lines 35 are only formed within the active region 30 .
  • the contact holes 39 are filled with the first conductive material and are electrically connected with the conductive pattern 43 .
  • the thickness of the insulating layer is formed from about 1000 to about 20000 angstroms.
  • the thickness of the conductive pattern layer 43 is formed to be over 10000 angstroms to maximize efficiency.
  • the insulating layer 37 is oxide formed at low temperature, or a polyimide film.
  • the conventional fringe portion of the gate lines 15 which are extended from the active region 10 to the isolation region are removed. Since a gate line finger has one removed fringe portion, if N gate fingers are used, the parasitic capacitance Cgb is decreased by as much as N times relative to the conventional RF MOSFET.
  • the gate lines 35 are not substantially overlapped with the trench(es) 33 , the parasitic capacitance between the gate lines 35 and the semiconductor substrate 31 is decreased and the resistance of the gate lines 35 is decreased as well to thereby improve the operating frequency Ft of the semiconductor device.
  • a trench for defining an active region and an element isolation region is formed in a semiconductor substrate.
  • One or more gate lines are formed within the active region in the semiconductor substrate. The gate line(s) do not substantially overlap with the trench.
  • An insulating layer is formed on the semiconductor substrate.
  • a contact hole is formed in the insulating layer.
  • a contact plug is formed in the contact hole.
  • a conductive pattern is then formed that is electrically connected with the contact plug.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

RF semiconductor devices and methods of making the same are disclosed. In a disclosed method, a trench for defining an active region and an element isolation region is formed in a semiconductor substrate. One or more gate lines is then formed within the active region. Next, an insulating layer is formed on the semiconductor substrate and the gate lines. Contact holes are then formed in the insulating layer. Contact plugs are then formed in the contact holes. Thereafter, a conductive pattern is electrically connected with the contact plugs.

Description

    RELATED APPLICATIONS
  • This application is a divisional of U.S. patent application Ser. No. 10/627,057, filed Jul. 25, 2003 (Attorney Docket No. PIA30746/DBE/US), pending, which is incorporated herein by reference in its entirety. This application also claims the benefit of Korean Application No. 10-2002-0044084, filed on Jul. 26, 2002, which is hereby incorporated by reference in its entirety.
    • FIELD OF THE DISCLOSURE
  • The present disclosure relates generally to semiconductor devices; and, more particularly, to radio frequency (RF) semiconductor devices having decreased parasitic capacitance and gate resistance and methods for fabricating the same.
    • BACKGROUND
  • Transistors, inductors, capacitors and varactors are widely used radio frequency (RF) semiconductor devices. Recently, silicon has become widely used in fabricating RF semiconductor devices for the purpose of reducing manufacturing costs. However, when an RF semiconductor device is made of silicon, certain characteristics thereof may be deteriorated.
  • For example, if a transistor, e.g., a MOSFET, is used in an RF circuit operating at high frequency, it is necessary to increase an operating frequency (Ft, Fmax) of the transistor. Factors effecting the operating frequency of MOSFETs include the parasitic capacitance between the gate and the substrate of the MOSFET, the resistance of the gate line, and the like. If the RF MOSFET is produced in a semiconductor manufacturing process, since a greater current, that is, a large transconductance gm of the RF MOSFET is required, the gate width thereof must be enlarged.
  • A prior art method for manufacturing a conventional RF semiconductor device will now be described with reference to the accompanying drawings. FIG. 1 shows a top plan view of a conventional RF semiconductor device. FIGS. 2A and 2B are cross-sectional views of the conventional RF semiconductor device taken along lines X-X′ and Y-Y′ shown in FIG. 1, respectively.
  • Referring to FIG. 1, a gate line 15 is formed on an active region 10 in a longitudinally elongated zigzag shape. A plurality of contact holes 19 are formed between the zigzags of the gate line 15. The contact holes are formed at a constant distance from one another. A portion of the gate line 15, as shown in FIG. 1, is formed over an inactive region, i.e., an element isolation region. Some of the contact holes 19 are also formed on the gate line 15 within the element isolation region.
  • As shown in FIG. 2A, a trench 13 is formed in a semiconductor substrate 11 and then the gate line 15 is formed on the semiconductor substrate 11. Next, an insulating layer 17 is formed on the semiconductor substrate 11 having the gate line 15 thereon. The insulating layer 17 is then selectively patterned to thereby form the contact holes 19 which expose the semiconductor substrate 11 and the gate line 15. Next, a first conductive material is deposited on the insulating layer 17 and in the contact holes 19. The first conductive material is then planarized to thereby form contact plugs 21.
  • Next, a second conductive material is deposited on the insulating layer 17 and the contact plugs 21. The second conductive material is then selectively patterned to thereby form a conductive pattern 23 in contact with the contact plugs 21.
  • Meanwhile, as shown in FIG. 2B, the gate line 15 is also formed over the trench 13 beyond the active region 10.
  • Most conventional RF MOSFETs employ a gate having a large width. In such a case, a fringe of the gate line 15 is extended for contact to the element isolation region as shown in FIGS. 1 and 2A.
  • Also, in the above construction, since the trench 13 and the gate line 15 are overlapped with each other in a plurality of places, the parasitic capacitance Cgb between the gate line 15 and the trench 13 is increased as indicated at C in FIGS. 2A and 2B.
  • Because the operating frequency Ft, which is one of the important parameters of the RF MOSFET, has a functional relationship with the parasitic capacitance Cgb, an increase in the parasitic capacitance Cgb can adversely affect the operating frequency Ft. Specifically, if several (e.g., dozens) of gate fingers are used in order to enlarge the width of the gate line 15, the parasitic capacitance Cgb will be further increased.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a top plan view of a conventional RF semiconductor device.
  • FIGS. 2A and 2B are cross-sectional views of the conventional RF semiconductor device of FIG. 1 taken along lines X-X′ and Y-Y′, respectively.
  • FIG. 3 is a top plan view of an example RF semiconductor device.
  • FIGS. 4A and 4B are cross-sectional views of the RF semiconductor device of FIG. 3 taken along lines X-X′ and Y-Y′, respectively
    •  DETAILED DESCRIPTION
  • Hereinafter, an example method for fabricating an RF semiconductor device will be described with reference to the accompanying drawings. FIG. 3 is a top plan view of an example RF semiconductor device. FIGS. 4A and 4B are cross-sectional views of the example RF semiconductor device of FIG. 3 taken along lines X-X′ and Y-Y′, respectively.
  • Referring to FIG. 3, a plurality of gate lines 35 which are elongated along a longitudinal direction are arranged on an active region 30 of a semiconductor substrate 31. A substantially constant distance is maintained between the gate lines 35. A plurality of contact holes 39 are formed between and on the gate lines 35 as shown in FIG. 3. A substantially constant distance is maintained between the contact holes 39. Specifically, the plurality of contact holes 39 are only formed within the active region 30.
  • As shown in FIG. 4A, a trench 33 is formed in the semiconductor substrate 31 and then the gate lines 35 are formed on the semiconductor substrate 31. However unlike the conventional gate lines 15 discussed above, the gate lines 35 are not formed to run along a longitudinal axis of the trench 33 as indicated at B of FIG. 4A.
  • Next, an insulating layer 37 is formed on the semiconductor substrate 31 having the gate lines 35 thereon. The insulating layer 37 is then selectively patterned to thereby form the contact holes 39 which expose the semiconductor substrate 31 and the gate line 35. At this time, the contact holes 39 are only formed within the active region 30.
  • A first conductive material is then deposited on the insulating layer 37 and in the contact holes 39. The first conductive material is then planarized to thereby form contact plugs 41.
  • Next, a second conductive material is deposited on the insulating layer 37 and the contact plugs 41. The second conductive material is then selectively patterned to thereby form a conductive pattern 43 contacting the contact plugs 41. As a result, some of the contact holes 39 are formed on the gate lines 35. As mentioned, the gate lines 35 are only formed within the active region 30. The contact holes 39 are filled with the first conductive material and are electrically connected with the conductive pattern 43. The thickness of the insulating layer is formed from about 1000 to about 20000 angstroms. The thickness of the conductive pattern layer 43 is formed to be over 10000 angstroms to maximize efficiency. The insulating layer 37 is oxide formed at low temperature, or a polyimide film.
  • As described above, the conventional fringe portion of the gate lines 15 which are extended from the active region 10 to the isolation region are removed. Since a gate line finger has one removed fringe portion, if N gate fingers are used, the parasitic capacitance Cgb is decreased by as much as N times relative to the conventional RF MOSFET.
  • Since the gate lines 35 are not substantially overlapped with the trench(es) 33, the parasitic capacitance between the gate lines 35 and the semiconductor substrate 31 is decreased and the resistance of the gate lines 35 is decreased as well to thereby improve the operating frequency Ft of the semiconductor device.
  • From the foregoing, persons of ordinary skill in the art will appreciate that methods for fabricating RF semiconductor devices having decreased parasitic capacitance and gate resistance have been disclosed. In a disclosed method, a trench for defining an active region and an element isolation region is formed in a semiconductor substrate. One or more gate lines are formed within the active region in the semiconductor substrate. The gate line(s) do not substantially overlap with the trench. An insulating layer is formed on the semiconductor substrate. A contact hole is formed in the insulating layer. A contact plug is formed in the contact hole. A conductive pattern is then formed that is electrically connected with the contact plug.
  • Although certain example methods and apparatus have been described herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all methods, apparatus and articles of manufacture fairly falling within the scope of the appended claims either literally or under the doctrine of equivalents.

Claims (20)

1. A RF semiconductor device comprising:
a substrate;
first and second trenches defining an active region and at least one isolation region in the substrate, the first and second trenches being located on opposite sides of the active region, each of the first and second trenches having a longitudinal axis; and
a plurality of gate lines formed in the active region and oriented substantially perpendicularly to the longitudinal axes of the first and second trenches, wherein the gate lines do not extend along the longitudinal axes of the first and second trenches.
2. The RF semiconductor device of claim 1, further comprising an insulating layer disposed on the plurality of gate lines and the substrate.
3. The RF semiconductor device of claim 1, wherein the plurality of gate lines are not connected with each other in the isolation region.
4. The RF semiconductor device of claim 1, wherein at least two of the plurality of gate lines are connected in the active region.
5. The RF semiconductor device of claim 1, wherein adjacent gate lines are formed at a substantially constant distance along their lengths.
6. The RF semiconductor device of claim 2, wherein a thickness of the insulating layer is about 1000 to about 20000 angstroms.
7. The RF semiconductor device of claim 2, wherein the insulating layer comprises an oxide or a polyimide.
8. The RF semiconductor device of claim 2, further comprising contact plugs disposed in the insulating layer over the active region.
9. The RF semiconductor device of claim 8, further comprising a conductive pattern layer disposed on the insulating layer and the contact plug, wherein the conductive pattern is electrically connected with the contact plugs.
10. The RF semiconductor device of claim 9, wherein a thickness of the conductive pattern layer is above 1000 angstroms.
11. A RF semiconductor device comprising:
a substrate;
first and second trenches defining an active region and at least one isolating region in the substrate, the first and second trenches being located on opposite sides of the active region; and
at least two gate lines extending across the active region from the first trench to the second trench without passing above a center of either of the first and second trenches.
12. The RF semiconductor device of claim 11, further comprising an insulating layer disposed on said at least two gate lines and the substrate.
13. The RF semiconductor device of claim 11, wherein said at least two gate lines do not extend longitudinally along a longitudinal axis of the trench.
14. The RF semiconductor device of claim 11, wherein said at least two gate lines are not connected with each other in the isolation region.
15. The RF semiconductor device of claim 11, wherein said at least two gate lines are connected in the active region.
16. The RF semiconductor device of claim 12, wherein a thickness of the insulating layer is about 1000 to about 20000 angstroms.
17. The RF semiconductor device of claim 12, wherein the insulating layer comprises an oxide or a polyimide
18. The RF semiconductor device of claim 12, further comprising contact plugs in each of contact holes,
wherein the contact holes are disposed in the insulating layer over the active region, and
wherein a first group of the contact holes exposes portions of said at least two gate lines and a second group of the contract holes exposes portion of the substrate in the active region.
19. The RF semiconductor device of claim 13, wherein said at least two gate lines do not extend horizontally along the longitudinal axis of the trench.
20. The RF semiconductor device of claim 18, further comprising a conductive pattern layer disposed on the insulating layer and the contact plug, wherein the conductive pattern is electrically connected with the contact plugs.
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KR1020020044084A KR20040011016A (en) 2002-07-26 2002-07-26 Method for fabricating RF semicoductor device
US10/627,057 US7361583B2 (en) 2002-07-26 2003-07-25 RF semiconductor devices and methods for fabricating the same
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2476236A (en) * 2009-12-15 2011-06-22 Cambridge Silicon Radio Ltd On-Gate contacts

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100840663B1 (en) * 2006-10-11 2008-06-24 동부일렉트로닉스 주식회사 RF Semiconductor Device and Method for Fabricating the Same
KR20090036831A (en) * 2007-10-10 2009-04-15 삼성전자주식회사 Wiring structure in semiconductor device and method of forming the same

Citations (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5858866A (en) * 1996-11-22 1999-01-12 International Business Machines Corportation Geometrical control of device corner threshold
US5939753A (en) * 1997-04-02 1999-08-17 Motorola, Inc. Monolithic RF mixed signal IC with power amplification
US6048772A (en) * 1998-05-04 2000-04-11 Xemod, Inc. Method for fabricating a lateral RF MOS device with an non-diffusion source-backside connection
US6171909B1 (en) * 1999-03-01 2001-01-09 United Semiconductor Corp. Method for forming a stacked gate
US6177320B1 (en) * 1998-01-08 2001-01-23 Samsung Electronics Co., Ltd. Method for forming a self aligned contact in a semiconductor device
US6204161B1 (en) * 1998-10-17 2001-03-20 Samsung Electronics, Co., Ltd. Self aligned contact pad in a semiconductor device and method for forming the same
US6277707B1 (en) * 1998-12-16 2001-08-21 Lsi Logic Corporation Method of manufacturing semiconductor device having a recessed gate structure
US6294834B1 (en) * 2000-01-21 2001-09-25 United Microelectronics Corp. Structure of combined passive elements and logic circuit on a silicon on insulator wafer
US20010025954A1 (en) * 1995-11-13 2001-10-04 Siemens Aktiengesellschaft Opto-electronic component made from II-VI semiconductor material
US6363658B1 (en) * 2000-10-10 2002-04-02 Yuan-Song Lai Flower pot
US6376351B1 (en) * 2001-06-28 2002-04-23 Taiwan Semiconductor Manufacturing Company High Fmax RF MOSFET with embedded stack gate
US6410390B1 (en) * 2000-02-03 2002-06-25 Hyundai Electronics Industries Co., Ltd. Nonvolatile memory device and method for fabricating the same
US6445026B1 (en) * 1999-07-29 2002-09-03 Sony Corporation Semiconductor device having a memory cell with a plurality of active elements and at least one passive element
US6444517B1 (en) * 2002-01-23 2002-09-03 Taiwan Semiconductor Manufacturing Company High Q inductor with Cu damascene via/trench etching simultaneous module
US6452249B1 (en) * 2000-04-19 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Inductor with patterned ground shield
US20020155655A1 (en) * 2001-04-18 2002-10-24 Pon Harry Q. EMI and noise shielding for multi-metal layer high frequency integrated circuit processes
US6489217B1 (en) * 2001-07-03 2002-12-03 Maxim Integrated Products, Inc. Method of forming an integrated circuit on a low loss substrate
US20030003700A1 (en) * 2001-06-28 2003-01-02 Cho Chang-Hyun Methods providing oxide layers having reduced thicknesses at central portions thereof and related devices
US6511919B1 (en) * 1999-08-26 2003-01-28 Samsung Electronics Co., Ltd. Contacts for a bit line and a storage node in a semiconductor device
US6528848B1 (en) * 1999-09-21 2003-03-04 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same
US6537849B1 (en) * 2001-08-22 2003-03-25 Taiwan Semiconductor Manufacturing Company Seal ring structure for radio frequency integrated circuits
US6627950B1 (en) * 1988-12-27 2003-09-30 Siliconix, Incorporated Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry
US6642555B1 (en) * 1998-05-01 2003-11-04 Sony Corporation Semiconductor memory device
US20040100814A1 (en) * 2002-11-26 2004-05-27 Sheng Teng Hsu Common bit/common source line high density 1T1R R-RAM array
US20050042833A1 (en) * 2003-08-20 2005-02-24 Jong-Chul Park Method of manufacturing integrated circuit device including recessed channel transistor
US6903406B2 (en) * 2002-02-08 2005-06-07 Samsung Electronics Co., Ltd. Cells of nonvolatile memory device with high inter-layer dielectric constant
US20050136616A1 (en) * 2003-12-19 2005-06-23 Young-Sun Cho Method of fabricating a recess channel array transistor using a mask layer with a high etch selectivity with respect to a silicon substrate
US20050280068A1 (en) * 2004-06-21 2005-12-22 Leo Wang Flash memory cell and manufacturing method thereof
US20060001107A1 (en) * 2004-07-05 2006-01-05 Ji-Young Kim Transistor including an active region and methods for fabricating the same
US20060018161A1 (en) * 2004-07-20 2006-01-26 Hsin-Ming Chen Single poly non-volatile memory
US20060120138A1 (en) * 2004-10-29 2006-06-08 Infineon Technologies Ag Semiconductor memory with volatile and non-volatile memory cells
US7061069B2 (en) * 2000-10-30 2006-06-13 Kabushiki Kaisha Toshiba Semiconductor device having two-layered charge storage electrode
US7068878B2 (en) * 2003-01-24 2006-06-27 University Of Washington Optical beam scanning system for compact image display or image acquisition
US7091087B2 (en) * 2001-07-13 2006-08-15 Micron Technology, Inc. Optimized flash memory cell
US20060231903A1 (en) * 2003-03-17 2006-10-19 Samsung Electronics Co., Ltd. Semiconductor devices having dual capping layer patterns and methods of manufacturing the same
US20070013024A1 (en) * 2004-08-19 2007-01-18 Hiroyuki Kutsukake High-voltage transistor having shielding gate
US20080061363A1 (en) * 2006-09-08 2008-03-13 Rolf Weis Integrated transistor device and corresponding manufacturing method
US7432157B2 (en) * 2003-09-24 2008-10-07 Dongbu Electronics Co., Ltd. Method of fabricating flash memory
US7732317B2 (en) * 2003-12-30 2010-06-08 Samsung Electronics Co., Ltd. Methods of forming contact structures for memory cells using both anisotropic and isotropic etching
US7745878B2 (en) * 2005-02-11 2010-06-29 Alpha & Omega Semiconductor, Ltd Shielded gate trench (SGT) MOSFET cells implemented with a schottky source contact

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08279610A (en) * 1995-04-06 1996-10-22 Toshiba Corp Semiconductor device
US5789791A (en) * 1996-08-27 1998-08-04 National Semiconductor Corporation Multi-finger MOS transistor with reduced gate resistance
KR19990057106A (en) * 1997-12-29 1999-07-15 구자홍 MOSFET and manufacturing method
KR20010093013A (en) * 2000-03-28 2001-10-27 박종섭 Method of forming a gate electrode and a gate line in a semiconductor device

Patent Citations (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6627950B1 (en) * 1988-12-27 2003-09-30 Siliconix, Incorporated Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry
US20010025954A1 (en) * 1995-11-13 2001-10-04 Siemens Aktiengesellschaft Opto-electronic component made from II-VI semiconductor material
US5858866A (en) * 1996-11-22 1999-01-12 International Business Machines Corportation Geometrical control of device corner threshold
US5939753A (en) * 1997-04-02 1999-08-17 Motorola, Inc. Monolithic RF mixed signal IC with power amplification
US6177320B1 (en) * 1998-01-08 2001-01-23 Samsung Electronics Co., Ltd. Method for forming a self aligned contact in a semiconductor device
US6642555B1 (en) * 1998-05-01 2003-11-04 Sony Corporation Semiconductor memory device
US6048772A (en) * 1998-05-04 2000-04-11 Xemod, Inc. Method for fabricating a lateral RF MOS device with an non-diffusion source-backside connection
US6204161B1 (en) * 1998-10-17 2001-03-20 Samsung Electronics, Co., Ltd. Self aligned contact pad in a semiconductor device and method for forming the same
US6277707B1 (en) * 1998-12-16 2001-08-21 Lsi Logic Corporation Method of manufacturing semiconductor device having a recessed gate structure
US6171909B1 (en) * 1999-03-01 2001-01-09 United Semiconductor Corp. Method for forming a stacked gate
US6445026B1 (en) * 1999-07-29 2002-09-03 Sony Corporation Semiconductor device having a memory cell with a plurality of active elements and at least one passive element
US6511919B1 (en) * 1999-08-26 2003-01-28 Samsung Electronics Co., Ltd. Contacts for a bit line and a storage node in a semiconductor device
US6777343B2 (en) * 1999-08-26 2004-08-17 Samsung Electronics Co., Ltd. Method of forming contacts for a bit line and a storage node in a semiconductor device
US20030022514A1 (en) * 1999-08-26 2003-01-30 Samsung Electronics Co., Ltd. Method of forming contacts for a bit line and a storage node in a semiconductor device
US6528848B1 (en) * 1999-09-21 2003-03-04 Hitachi, Ltd. Semiconductor device and a method of manufacturing the same
US6294834B1 (en) * 2000-01-21 2001-09-25 United Microelectronics Corp. Structure of combined passive elements and logic circuit on a silicon on insulator wafer
US6410390B1 (en) * 2000-02-03 2002-06-25 Hyundai Electronics Industries Co., Ltd. Nonvolatile memory device and method for fabricating the same
US6452249B1 (en) * 2000-04-19 2002-09-17 Mitsubishi Denki Kabushiki Kaisha Inductor with patterned ground shield
US6363658B1 (en) * 2000-10-10 2002-04-02 Yuan-Song Lai Flower pot
US7061069B2 (en) * 2000-10-30 2006-06-13 Kabushiki Kaisha Toshiba Semiconductor device having two-layered charge storage electrode
US7420259B2 (en) * 2000-10-30 2008-09-02 Kabushiki Kaisha Toshiba Semiconductor device having two-layered charge storage electrode
US20020155655A1 (en) * 2001-04-18 2002-10-24 Pon Harry Q. EMI and noise shielding for multi-metal layer high frequency integrated circuit processes
US20030199155A9 (en) * 2001-06-28 2003-10-23 Cho Chang-Hyun Methods providing oxide layers having reduced thicknesses at central portions thereof
US6376351B1 (en) * 2001-06-28 2002-04-23 Taiwan Semiconductor Manufacturing Company High Fmax RF MOSFET with embedded stack gate
US20030003700A1 (en) * 2001-06-28 2003-01-02 Cho Chang-Hyun Methods providing oxide layers having reduced thicknesses at central portions thereof and related devices
US6489217B1 (en) * 2001-07-03 2002-12-03 Maxim Integrated Products, Inc. Method of forming an integrated circuit on a low loss substrate
US7091087B2 (en) * 2001-07-13 2006-08-15 Micron Technology, Inc. Optimized flash memory cell
US6537849B1 (en) * 2001-08-22 2003-03-25 Taiwan Semiconductor Manufacturing Company Seal ring structure for radio frequency integrated circuits
US6444517B1 (en) * 2002-01-23 2002-09-03 Taiwan Semiconductor Manufacturing Company High Q inductor with Cu damascene via/trench etching simultaneous module
US6903406B2 (en) * 2002-02-08 2005-06-07 Samsung Electronics Co., Ltd. Cells of nonvolatile memory device with high inter-layer dielectric constant
US7449763B2 (en) * 2002-02-08 2008-11-11 Samsung Electronics Co., Ltd. Method of fabricating cell of nonvolatile memory device with floating gate
US20040100814A1 (en) * 2002-11-26 2004-05-27 Sheng Teng Hsu Common bit/common source line high density 1T1R R-RAM array
US7068878B2 (en) * 2003-01-24 2006-06-27 University Of Washington Optical beam scanning system for compact image display or image acquisition
US20060231903A1 (en) * 2003-03-17 2006-10-19 Samsung Electronics Co., Ltd. Semiconductor devices having dual capping layer patterns and methods of manufacturing the same
US20050042833A1 (en) * 2003-08-20 2005-02-24 Jong-Chul Park Method of manufacturing integrated circuit device including recessed channel transistor
US7432157B2 (en) * 2003-09-24 2008-10-07 Dongbu Electronics Co., Ltd. Method of fabricating flash memory
US20050136616A1 (en) * 2003-12-19 2005-06-23 Young-Sun Cho Method of fabricating a recess channel array transistor using a mask layer with a high etch selectivity with respect to a silicon substrate
US7732317B2 (en) * 2003-12-30 2010-06-08 Samsung Electronics Co., Ltd. Methods of forming contact structures for memory cells using both anisotropic and isotropic etching
US20050280068A1 (en) * 2004-06-21 2005-12-22 Leo Wang Flash memory cell and manufacturing method thereof
US20060001107A1 (en) * 2004-07-05 2006-01-05 Ji-Young Kim Transistor including an active region and methods for fabricating the same
US7462544B2 (en) * 2004-07-05 2008-12-09 Samsung Electronics Co., Ltd. Methods for fabricating transistors having trench gates
US20090127635A1 (en) * 2004-07-05 2009-05-21 Ji-Young Kim Transistor including an active region and methods for fabricating the same
US20060018161A1 (en) * 2004-07-20 2006-01-26 Hsin-Ming Chen Single poly non-volatile memory
US20070013024A1 (en) * 2004-08-19 2007-01-18 Hiroyuki Kutsukake High-voltage transistor having shielding gate
US20060120138A1 (en) * 2004-10-29 2006-06-08 Infineon Technologies Ag Semiconductor memory with volatile and non-volatile memory cells
US7745878B2 (en) * 2005-02-11 2010-06-29 Alpha & Omega Semiconductor, Ltd Shielded gate trench (SGT) MOSFET cells implemented with a schottky source contact
US20080061363A1 (en) * 2006-09-08 2008-03-13 Rolf Weis Integrated transistor device and corresponding manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2476236A (en) * 2009-12-15 2011-06-22 Cambridge Silicon Radio Ltd On-Gate contacts

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