US20080010429A1 - Pipelined semiconductor memories and systems - Google Patents

Pipelined semiconductor memories and systems Download PDF

Info

Publication number
US20080010429A1
US20080010429A1 US11771689 US77168907A US2008010429A1 US 20080010429 A1 US20080010429 A1 US 20080010429A1 US 11771689 US11771689 US 11771689 US 77168907 A US77168907 A US 77168907A US 2008010429 A1 US2008010429 A1 US 2008010429A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
memory
address
bank
data
addresses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US11771689
Inventor
G. R. Mohan Rao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
S Aqua Semiconductor LLC
Original Assignee
S Aqua Semiconductor LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers

Abstract

The invention describes and provides pipelining of addresses to memory products. Addresses are pipelined to multibank memories on both rising and falling edges of a clock. Global Address Supervisor pipelines these addresses optimally without causing bank or block or subarray operational conflicts. Enhanced data through put and bandwidth, as well as substantially improved bus utilization (simultaneously), can be realized. In peer-to-peer connected systems, significant random data access throughput can be obtained.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • [0001]
    The Patent Application claims priority to provisional patent Application Ser. No. 60/475,224 entitled “Pipelined Semiconductor Memories” filed Jun. 2, 2003 by inventor G. R. Mohan Rao [Attorney Docket No. 17200-P037V1].
  • FIELD OF INVENTION
  • [0002]
    The present invention relates in general to electronic systems comprising semiconductor integrated circuits. It relates in particular to pipelined memories in standalone (discrete) as well as embedded (system-on-chip, system-in-package) implementations.
  • BACKGROUND OF THE INVENTION
  • [0003]
    Peak data bandwidth, average data bandwidth, fast bus turnaround, maximum bus utilization and efficiency, low power, nonvolatility—all at an affordable cost—are key requirements for semiconductor components. Specifically, for semiconductor memories, there are additional requirements as well. For example, balanced read/write operational efficiency in communication systems, is necessary. In some systems dominated by ‘page’ architectures (DRAM, Flash are some examples), multiple open pages improves system efficiency. Since memory integrated circuits are used in large numbers in electronic systems, their ability to function efficiently in bus architectures, as well as peak-to-peak architectures is desirable.
  • [0004]
    Most memories, at the core, are two-dimensional arrays of rows and columns. DRAMS, Flash, SRAMs, EEPROMS, Ferroelectric memories, Magnetic RAMS, nanotube RAM's (carbon nanotube is one example), molecular memories, phase change memories and organic memories etc. Each of these memories serve a particular application satisfying the requirements of that particular application. Although, all these memories are Read and Write memories, each application requires focus on a particular parameter. ‘Open page’ applications (Personal Computers, Servers for example) require fast data with a given page (or predetermined set/sets of columns)—Rambus™, DDR (double data rate), QDR (quad data rate), FCRAM™, RLDRAM™ (reduced latency) are serving those requirements. ZBTSRAM™ serves some specific needs in wired communication systems. Pseudo static RAM'S, nonvolatile SRAM'S, MIM (metal-insulator-metal) RAM'S are finding acceptance in portable electronic systems like cellular phones.
  • SUMMARY OF THE INVENTION
  • [0005]
    All of the above memories without an exception, desire fast data throughput at low cost and low power. Although data pipelining and prefetching from the memory core have been described in prior art, address pipelining in general, bank/block/sector/row/subarray and address pipelining in particular, have not been attempted. It is one embodiment of the invention to pipeline all addresses at the same rate as data, independent of the address function (row, column, bank, block, sector). It is another embodiment of the invention to pipeline those addresses on both the rising and falling edges of SCLK (System clock) or a primary clock for that particular system or IC. It is yet another purpose and embodiment of the invention to provide a global command and control supervisory circuitry for each monolithic integrated circuit that optimizes the efficiency of a multi bank/block/sector IC. The word “bank” is used here, synonymously with block, sector, subarray etc. It is also another embodiment to pipeline addresses at a rate faster than data, or, even slower than data in an asynchronous manner.
  • [0006]
    Although preferred embodiments are described in this invention, the implementation and extension of the principles of the invention are not limited. For those skilled in the art, the principles described in this invention will be obvious. The principles of the present invention are embodied in memory system architectures and operating methods utilizing multiple banks (blocks, sectors, subarrays) and independent row/column address decoding pipeline. A memory is disclosed where a plurality of independently addressable banks for storing data can function with a decoding pipeline of n-stages where n is greater than 1, and at least 2. The “unit” is one system or primary clock (SCLK, CLK) period. Row and column addresses can be continuously pipelined from the address input parts. Global address supervisory circuitry allows a sequence of addresses to be continuously received, and, properly implemented, without conflict at any stage.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • [0007]
    FIG. 1 is a functional block diagram of a 32 Meg×16 double data rate synchronous RAM (memory) incorporating some of the inventions like global supervisory control described in this patent.
  • [0008]
    FIG. 2 is a functional block diagram of a 32 Meg×16 memory with additional embodiments of the invention where the global supervisory control specifically focuses on the bank and row address path.
  • [0009]
    FIG. 3 is a functional block diagram of a memory system/IC where an SRAM buffer/register between the memory core (can be any memory, DRAM core is shown as an example only) and peripheral circuitry (address, command, control and clocks).
  • [0010]
    FIG. 4 is a functional block diagram of a memory system/IC where the READ and WRITE data paths are separately gated to the core memory.
  • DETAILED DESCRIPTION OF THE INVENTION
  • [0011]
    The principles of the present invention and their advantages are best understood by referring to the illustrated embodiments depicted in FIGS. 1-4 of the drawings, in which like numbers designate like parts. The inventions described below apply to any memory, namely, DRAM, SRAM, EPROM, EEPROM, Flash, Mag RAM, FeRAM, PCRAM, plastic RAM, CNTRAM, Molecular RAM etc. The inventions apply to both non-multiplexed address as well as multiplexed-address integrated circuits. The inventions described below apply to what is known in the industry as “row” chain—namely, selecting block/bank/sector/subarray/row in any IC (integrated circuit) or system (consisting of several IC's) or SOC (System On Chip). The inventions apply to single-ended or rail-to-rail address/data/clock signals. The inventions apply to the “column” chain as well. The inventions apply to “data bursts”, “prefetch schemes”, “page schemes” and similar architectures known in the industry. The effective bandwidth of a device can be enhanced 2 to 4× or even more, by using these inventions, with minimal cost.
  • [0012]
    The time line sequence of events in a monolithic commercial multi-bank synchronous DRAM (generally speaking)—a 512 Mb DRAM, organized as 32 Mb×16, for example is described below (a clock, a command, a control are given, in addition to the addresses, to access one or more sets of memory locations). For simplicity's sake, we shall describe these in ‘clock units’ (1 unit is one master clock period). Assume all banks have been precharged before the memory access cycle begins (it is assumed and understood that MODE registers, defining specific device operational choices are set appropriately):
      • a) Addresses are received, appropriately level shifted/converted after detection (on chip)
      • b) Bank selection is made
      • c) Row address is streered to the selected bank
      • d) Row address is decoded (to select 1 of n rows) in the specific bank (assumes proper subarray is selected, if necessary)
      • e) Word line is activated
      • f) Signal from all storage cells (memory cells) in the related row, are detected and amplified by the sense amplifier (for a read operation in a dynamic cell, appropriate digital level is written instead of RESTORE)
      • g) Column start address is selected, data prefetched in the ‘burst order’ defined (activation of column address select can be posted earlier; ‘posted CAS’ as is well known in the industry)
      • h) If the command is READ, appropriate data is sent to output buffers (depending on data fetch schemes, DDR or QDR is employed
      • i) If the command is WRITE, appropriate data is received from the input buffers (level shifted and amplified as needed) is coupled to appropriate lines of columns at the sense amplifiers
      • j) RESTORE is performed if a memory core requires that function, automatically, as a part of the READ
      • k) Page is left open for further READ/WRITE operations into the same PAGE (usually one Page is equal to one row of data). As is well known in the industry, nonvolatile memory IC's also used PAGE driven architecture, by employing an SRAM buffer.
  • [0024]
    In the case of RLDRAM (reduced latency DRAM), the banks are cycled in sequence and the PAGE in the previously accessed bank is closed in each bank as the cycling starts to a new bank access.
  • [0025]
    Precharge is not required for 6TSRAM's, Flash nonvolatile memories and similar memory cores. Precharge is required PSRAM's (pseudo static RAM's) as is know in the industry. The above ‘time sequence’ varies for memory type, namely, DRAM, SPAM, flash etc.
  • [0026]
    The critical paths of ‘row access’ and ‘column access’ dictate the ‘access time’ of each memory. In today's popular memory products (DRAM's, SRAM's, flash), although the memory may be in multiple banks in the same monolithic chip, the peripheral circuitry (internal clocks, data paths to the external media) is common. This limitation, significantly, impedes access speed. For example, while one ‘row’ (wordline) is ON, the next row address for access can be waiting in line without turning ON the wordline. As illustrated in FIG. 1, the invention highlights what has not been shown in prior art. Firstly, addresses are toggled on both raising and falling edges of the CLK. Effectively, this doubles the rate (speed) at which addresses can be funneled into the IC, compared to prior art. Secondly, all incoming addresses (after level shifting and amplification, as necessary) directly go to the Global Address Supervisor (global address/command/control register and scheduler). Such an architectural item is not know in the industry, nor implemented in any of the IC's (DRAM, SRAM, flash, NVSRAM). The Global Address supervisor, in this invention, performs some of the following tasks:
      • 1) it steers the address to the designated bank (if a DRAM or SRAM) or block/sector (if Flash memory) or similar memory array unit as used by memory IC's.
      • 2) it has the ability to map, if required, addresses, or sequence the addresses appropriately, to avoid bank/flock/sector/subarray/row conflicts
      • 3) if a BANK is busy, it has the ability to hold the addresses in a STAGING area temporarily, and release that address to that bank at the appropriate time without causing device malfunction. This increases bus utilization time.
  • [0030]
    The Global Address Supervisor is shown in FIGS. 1 and 2. Whereas FIG. 1 highlights the invention for a multiplexed address DRAM, FIG. 2 shows the implementation of this invention to any memory (not limited to DRAM). The staging area for the addresses—row, column or whatever—can be implemented either with SRAM like latches (set/release latches) or similar digital logic circuitry well known in the industry. Such isolation latches can also be used in various stages of clocked circuitry, where needed in the row path as well as column path.
  • [0031]
    It should be obvious that the peak as well as average bandwidth of the memory IC or system can be doubled, with minimal cost. By employing separate READ and WRITE access port, the bandwidth can be increased even further. By employing FIFO'S (FIRST IN, FIRST OUT) in the WRITE path, one can further enhance performance in specific application like packet buffering (where the INCOMING PACKET QUEUE is well defined, where as the OUTGOING PACKET QUEUE is mostly random).
  • [0032]
    Yet another embodiment of the invention is illustrated in FIG. 3. Using an SRAM as the interface between memory core/sense amplifiers and data path circuitry further enhances random access latency and bus turn around time. FIG. 3 illustrates such a preferred embodiment bank architecture. These SRAM registers can be staging areas for the INGRESS and EGRESS of data (packets or other forms). The Global Address Supervisor interacts with the SRAM registers when the BANK is available to enhance performance further. All addresses/commands/controls are from SRAM registers, as shown in FIG. 3. When the memory core is flash, such SRAM registers are already available (see references) so that this invention enhances performance without additional cost to the user.
  • [0033]
    Yet another embodiment is shown in FIG. 4 where the READ and WRITE data paths are separated (individualized). Such separate data path architecture enhances random access performance, as well as double the data throughput (especially for balanced Read/Write schemes in communication applications). The number of SRAM registers (buffers) can be increased, to maintain multiple open pages as well.
  • [0034]
    While particular embodiments of the inventions have been shown and described, changes and modifications may be made there in without departing from the inventions in their broader aspects. Therefore, the aim in the appended claims to cover all such changes and modifications as fall within the true spirit and scope of the basic invention.

Claims (34)

  1. 1. (canceled)
  2. 2. (canceled)
  3. 3. (canceled)
  4. 4. (canceled)
  5. 5. (canceled)
  6. 6. (canceled)
  7. 7. (canceled)
  8. 8. (canceled)
  9. 9. (canceled)
  10. 10. (canceled)
  11. 11. (canceled)
  12. 12. (canceled)
  13. 13. (canceled)
  14. 14. (canceled)
  15. 15. (canceled)
  16. 16. (canceled)
  17. 17. (canceled)
  18. 18. A semiconductor memory device, comprising:
    a plurality of independently addressable banks to store data; and
    a Global Address Supervisor coupled to said plurality of independently addressable banks, wherein said Global Address Supervisor is configured to continuously receive a sequence of row and column addresses addressing selected ones of said banks, and to steer said continuously received row and column addresses to the addressed banks of said plurality of independently addressable banks in a manner that avoids bank conflicts.
  19. 19. The semiconductor memory device as recited in claim 18, wherein if a bank of said plurality of independently addressable banks is unavailable, then said Global Address Supervisor is configured to hold a received address addressing the unavailable bank in a staging area.
  20. 20. The semiconductor memory device as recited in claim 19, wherein said Global Address Supervisor is further configured to release an address held in the staging area to the addressed bank of said plurality of independently addressable banks after the addressed bank becomes available.
  21. 21. The semiconductor memory device as recited in claim 18, wherein the semiconductor memory device is configured to be coupled to separate read and write buses to receive said row and column addresses through said separate read and write busses.
  22. 22. A method for operating a memory device comprising:
    receiving a sequence of row and column addresses addressing selected ones of a plurality of memory banks of the memory device; and
    steering said received sequence of row and column addresses to the addressed bank of said plurality of independently addressable banks in a manner that avoids bank conflicts.
  23. 23. The method as recited in claim 22 further comprising:
    holding a received address addressing an unavailable bank in a staging area.
  24. 24. The method as recited in claim 23 further comprising:
    releasing an address held in the staging area to the addressed bank after the addressed bank becomes available.
  25. 25. The method as recited in claim 22, wherein said receiving comprises receiving said row and column addresses through separate read and write busses.
  26. 26. The apparatus of claim 18 wherein said continuously received row and column addresses are toggled on both rising and falling edges of a clock signal.
  27. 27. The apparatus of claim 18 further comprising an SRAM register and wherein the Global Address Supervisor is coupled to said independently addressable banks via the SRAM register.
  28. 28. The apparatus of claim 18 further comprising independent read and write paths coupled to said independently addressable banks for independently reading or writing data to the independently addressable banks.
  29. 29. The apparatus of claim 28 further comprising a plurality of buffers coupling the independent read and write paths to the independently addressable banks, the plurality of buffers including at least one buffer coupled to the read path and at least one buffer coupled to the write path.
  30. 30. The apparatus of claim 29 wherein the plurality of buffers are SRAM devices.
  31. 31. The apparatus of claim 29 wherein the plurality of buffers comprise either a plurality of read buffers coupled to the read path or a plurality of write buffers coupled to the write path for maintaining simultaneous multiple open pages of the independently addressable banks.
  32. 32. The method of claim 22 further comprising toggling the continuous sequence of row and column addresses on both rising and falling edges of a clock signal.
  33. 33. The semiconductor memory device of claim 18, wherein the Global Address Supervisor is configured to map said continuously received row and column addresses to the addressed banks of said plurality of independently addressable banks in a manner that avoids bank conflicts.
  34. 34. The method of claim 22 further comprising mapping said received sequence of row and column addresses to the addressed bank of said plurality of independently addressable banks in a manner that avoids bank conflicts.
US11771689 2003-06-02 2007-06-29 Pipelined semiconductor memories and systems Abandoned US20080010429A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US47522403 true 2003-06-02 2003-06-02
US10850719 US7254690B2 (en) 2003-06-02 2004-05-20 Pipelined semiconductor memories and systems
US11771689 US20080010429A1 (en) 2003-06-02 2007-06-29 Pipelined semiconductor memories and systems

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11771689 US20080010429A1 (en) 2003-06-02 2007-06-29 Pipelined semiconductor memories and systems

Publications (1)

Publication Number Publication Date
US20080010429A1 true true US20080010429A1 (en) 2008-01-10

Family

ID=33457676

Family Applications (2)

Application Number Title Priority Date Filing Date
US10850719 Active 2025-05-13 US7254690B2 (en) 2003-06-02 2004-05-20 Pipelined semiconductor memories and systems
US11771689 Abandoned US20080010429A1 (en) 2003-06-02 2007-06-29 Pipelined semiconductor memories and systems

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US10850719 Active 2025-05-13 US7254690B2 (en) 2003-06-02 2004-05-20 Pipelined semiconductor memories and systems

Country Status (1)

Country Link
US (2) US7254690B2 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080106961A1 (en) * 2006-11-07 2008-05-08 Seiko Epson Corporation Data transmission control device, and data transmission control method
CN101916590A (en) * 2010-08-19 2010-12-15 中国科学院上海微系统与信息技术研究所 Data reading method and circuit of phase change memory
US8374051B2 (en) 2011-03-03 2013-02-12 Sandisk 3D Llc Three dimensional memory system with column pipeline
WO2013025656A1 (en) * 2011-08-12 2013-02-21 Gsi Technology, Inc. Systems and methods involving multi-bank, dual- or multi-pipe srams
US8553476B2 (en) 2011-03-03 2013-10-08 Sandisk 3D Llc Three dimensional memory system with page of data across word lines
US20140025892A1 (en) * 2012-07-17 2014-01-23 Gerard R. Williams III Converting memory accesses near barriers into prefetches
US20140173170A1 (en) * 2012-12-14 2014-06-19 Hewlett-Packard Development Company, L.P. Multiple subarray memory access
US9053766B2 (en) 2011-03-03 2015-06-09 Sandisk 3D, Llc Three dimensional memory system with intelligent select circuit
US9146867B2 (en) 2011-10-31 2015-09-29 Hewlett-Packard Development Company, L.P. Methods and apparatus to access memory using runtime characteristics
US9361955B2 (en) 2010-01-28 2016-06-07 Hewlett Packard Enterprise Development Lp Memory access methods and apparatus

Families Citing this family (73)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060020634A1 (en) * 2004-07-20 2006-01-26 International Business Machines Corporation Method, system and program for recording changes made to a database
CA2597551A1 (en) * 2005-02-11 2006-08-17 M-Systems Flash Disk Pioneers Ltd. Nand flash memory system architecture
WO2007132456A3 (en) 2006-05-12 2009-04-16 Anobit Technologies Ltd Memory device with adaptive capacity
WO2007132457A3 (en) 2006-05-12 2009-04-16 Anobit Technologies Ltd Combined distortion estimation and error correction coding for memory devices
WO2007132452A3 (en) 2006-05-12 2009-04-09 Anobit Technologies Reducing programming error in memory devices
US8151166B2 (en) 2007-01-24 2012-04-03 Anobit Technologies Ltd. Reduction of back pattern dependency effects in memory devices
WO2007132453A3 (en) 2006-05-12 2009-04-16 Anobit Technologies Ltd Distortion estimation and cancellation in memory devices
US7755961B2 (en) * 2006-07-07 2010-07-13 Rao G R Mohan Memories with selective precharge
US7724593B2 (en) * 2006-07-07 2010-05-25 Rao G R Mohan Memories with front end precharge
WO2008026203A3 (en) 2006-08-27 2009-05-07 Anobit Technologies Estimation of non-linear distortion in memory devices
WO2008053472A3 (en) 2006-10-30 2009-05-14 Anobit Technologies Ltd Reading memory cells using multiple thresholds
CN101601094B (en) 2006-10-30 2013-03-27 苹果公司 Reading memory cells using multiple thresholds
US7924648B2 (en) 2006-11-28 2011-04-12 Anobit Technologies Ltd. Memory power and performance management
US8151163B2 (en) 2006-12-03 2012-04-03 Anobit Technologies Ltd. Automatic defect management in memory devices
US7900102B2 (en) 2006-12-17 2011-03-01 Anobit Technologies Ltd. High-speed programming of memory devices
US7751240B2 (en) 2007-01-24 2010-07-06 Anobit Technologies Ltd. Memory device with negative thresholds
CN101715595A (en) 2007-03-12 2010-05-26 爱诺彼得技术有限责任公司 Adaptive estimation of memory cell read thresholds
US8001320B2 (en) 2007-04-22 2011-08-16 Anobit Technologies Ltd. Command interface for memory devices
WO2008139441A3 (en) 2007-05-12 2010-02-25 Anobit Technologies Ltd. Memory device with internal signal processing unit
US8234545B2 (en) 2007-05-12 2012-07-31 Apple Inc. Data storage with incremental redundancy
WO2008154360A1 (en) * 2007-06-06 2008-12-18 Hunt Technologies, Llc Arbitration of memory transfers in a dsp system
US7925936B1 (en) 2007-07-13 2011-04-12 Anobit Technologies Ltd. Memory device with non-uniform programming levels
US8259497B2 (en) 2007-08-06 2012-09-04 Apple Inc. Programming schemes for multi-level analog memory cells
US8174905B2 (en) 2007-09-19 2012-05-08 Anobit Technologies Ltd. Programming orders for reducing distortion in arrays of multi-level analog memory cells
US7773413B2 (en) 2007-10-08 2010-08-10 Anobit Technologies Ltd. Reliable data storage in analog memory cells in the presence of temperature variations
US7995409B2 (en) * 2007-10-16 2011-08-09 S. Aqua Semiconductor, Llc Memory with independent access and precharge
US8527819B2 (en) 2007-10-19 2013-09-03 Apple Inc. Data storage in analog memory cell arrays having erase failures
US8000141B1 (en) 2007-10-19 2011-08-16 Anobit Technologies Ltd. Compensation for voltage drifts in analog memory cells
US8068360B2 (en) 2007-10-19 2011-11-29 Anobit Technologies Ltd. Reading analog memory cells using built-in multi-threshold commands
US8095853B2 (en) 2007-10-19 2012-01-10 S. Aqua Semiconductor Llc Digital memory with fine grain write operation
US7787311B2 (en) * 2007-11-08 2010-08-31 Rao G R Mohan Memory with programmable address strides for accessing and precharging during the same access cycle
WO2009063450A3 (en) 2007-11-13 2010-03-11 Anobit Technologies Optimized selection of memory units in multi-unit memory devices
US8225181B2 (en) 2007-11-30 2012-07-17 Apple Inc. Efficient re-read operations from memory devices
US8209588B2 (en) 2007-12-12 2012-06-26 Anobit Technologies Ltd. Efficient interference cancellation in analog memory cell arrays
US8456905B2 (en) 2007-12-16 2013-06-04 Apple Inc. Efficient data storage in multi-plane memory devices
US8085586B2 (en) 2007-12-27 2011-12-27 Anobit Technologies Ltd. Wear level estimation in analog memory cells
US20090182977A1 (en) * 2008-01-16 2009-07-16 S. Aqua Semiconductor Llc Cascaded memory arrangement
US8156398B2 (en) 2008-02-05 2012-04-10 Anobit Technologies Ltd. Parameter estimation based on error correction code parity check equations
US7924587B2 (en) 2008-02-21 2011-04-12 Anobit Technologies Ltd. Programming of analog memory cells using a single programming pulse per state transition
US7864573B2 (en) 2008-02-24 2011-01-04 Anobit Technologies Ltd. Programming analog memory cells for reduced variance after retention
US8230300B2 (en) 2008-03-07 2012-07-24 Apple Inc. Efficient readout from analog memory cells using data compression
US8400858B2 (en) 2008-03-18 2013-03-19 Apple Inc. Memory device with reduced sense time readout
US8059457B2 (en) 2008-03-18 2011-11-15 Anobit Technologies Ltd. Memory device with multiple-accuracy read commands
US8498151B1 (en) 2008-08-05 2013-07-30 Apple Inc. Data storage in analog memory cells using modified pass voltages
US7924613B1 (en) 2008-08-05 2011-04-12 Anobit Technologies Ltd. Data storage in analog memory cells with protection against programming interruption
US8169825B1 (en) 2008-09-02 2012-05-01 Anobit Technologies Ltd. Reliable data storage in analog memory cells subjected to long retention periods
US8949684B1 (en) 2008-09-02 2015-02-03 Apple Inc. Segmented data storage
US8000135B1 (en) 2008-09-14 2011-08-16 Anobit Technologies Ltd. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8482978B1 (en) 2008-09-14 2013-07-09 Apple Inc. Estimation of memory cell read thresholds by sampling inside programming level distribution intervals
US8239734B1 (en) 2008-10-15 2012-08-07 Apple Inc. Efficient data storage in storage device arrays
US8713330B1 (en) 2008-10-30 2014-04-29 Apple Inc. Data scrambling in memory devices
US8208304B2 (en) 2008-11-16 2012-06-26 Anobit Technologies Ltd. Storage at M bits/cell density in N bits/cell analog memory cell devices, M>N
US8174857B1 (en) 2008-12-31 2012-05-08 Anobit Technologies Ltd. Efficient readout schemes for analog memory cell devices using multiple read threshold sets
US8248831B2 (en) 2008-12-31 2012-08-21 Apple Inc. Rejuvenation of analog memory cells
US8924661B1 (en) 2009-01-18 2014-12-30 Apple Inc. Memory system including a controller and processors associated with memory devices
US8228701B2 (en) 2009-03-01 2012-07-24 Apple Inc. Selective activation of programming schemes in analog memory cell arrays
US8259506B1 (en) 2009-03-25 2012-09-04 Apple Inc. Database of memory read thresholds
US8832354B2 (en) 2009-03-25 2014-09-09 Apple Inc. Use of host system resources by memory controller
US8238157B1 (en) 2009-04-12 2012-08-07 Apple Inc. Selective re-programming of analog memory cells
US8479080B1 (en) 2009-07-12 2013-07-02 Apple Inc. Adaptive over-provisioning in memory systems
US8495465B1 (en) 2009-10-15 2013-07-23 Apple Inc. Error correction coding over multiple memory pages
US8677054B1 (en) 2009-12-16 2014-03-18 Apple Inc. Memory management schemes for non-volatile memory devices
US8694814B1 (en) 2010-01-10 2014-04-08 Apple Inc. Reuse of host hibernation storage space by memory controller
US8572311B1 (en) 2010-01-11 2013-10-29 Apple Inc. Redundant data storage in multi-die memory systems
US8151075B2 (en) * 2010-01-22 2012-04-03 Freescale Semiconductor, Inc. Multiple access type memory and method of operation
US8694853B1 (en) 2010-05-04 2014-04-08 Apple Inc. Read commands for reading interfering memory cells
US8572423B1 (en) 2010-06-22 2013-10-29 Apple Inc. Reducing peak current in memory systems
US8595591B1 (en) 2010-07-11 2013-11-26 Apple Inc. Interference-aware assignment of programming levels in analog memory cells
US9104580B1 (en) 2010-07-27 2015-08-11 Apple Inc. Cache memory for hybrid disk drives
US8767459B1 (en) 2010-07-31 2014-07-01 Apple Inc. Data storage in analog memory cells across word lines using a non-integer number of bits per cell
US8856475B1 (en) 2010-08-01 2014-10-07 Apple Inc. Efficient selection of memory blocks for compaction
US8694854B1 (en) 2010-08-17 2014-04-08 Apple Inc. Read threshold setting based on soft readout statistics
US9021181B1 (en) 2010-09-27 2015-04-28 Apple Inc. Memory management for unifying memory cell conditions by using maximum time intervals

Citations (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3931613A (en) * 1974-09-25 1976-01-06 Data General Corporation Data processing system
US4811007A (en) * 1983-11-29 1989-03-07 Tandy Corporation High resolution video graphics system
US5426603A (en) * 1993-01-25 1995-06-20 Hitachi, Ltd. Dynamic RAM and information processing system using the same
US5745732A (en) * 1994-11-15 1998-04-28 Cherukuri; Ravikrishna V. Computer system including system controller with a write buffer and plural read buffers for decoupled busses
US5856940A (en) * 1997-08-15 1999-01-05 Silicon Aquarius, Inc. Low latency DRAM cell and method therefor
US5936959A (en) * 1996-05-31 1999-08-10 Mmc Networks, Inc. Cell routing in ATM networks
US5963504A (en) * 1994-12-23 1999-10-05 Micron Technology, Inc. Address transition detection in a synchronous design
US6011744A (en) * 1997-07-16 2000-01-04 Altera Corporation Programmable logic device with multi-port memory
US6128278A (en) * 1996-08-30 2000-10-03 Mmc Networks, Inc. Cell queuing in ATM switches
US6219769B1 (en) * 1998-12-09 2001-04-17 Advanced Micro Devices, Inc. Method and system for origin-sensitive memory control and access in data processing systems
US6272577B1 (en) * 1994-07-05 2001-08-07 Monolithic System Technology, Inc. Data processing system with master and slave devices and asymmetric signal swing bus
US6360307B1 (en) * 1998-06-18 2002-03-19 Cypress Semiconductor Corporation Circuit architecture and method of writing data to a memory
US20020038415A1 (en) * 1996-11-04 2002-03-28 U.S. Philips Corporation Processor architecture with independently addressable memory banks for storing instructions to be executed
US6396764B1 (en) * 2000-11-16 2002-05-28 Silicon Aquarius, Inc. Segmented memory architecture and systems and methods using the same
US6400635B1 (en) * 2000-03-15 2002-06-04 Altera Corporation Memory circuitry for programmable logic integrated circuit devices
US6427197B1 (en) * 1998-09-16 2002-07-30 Fujitsu Limited Semiconductor memory device operating in synchronization with a clock signal for high-speed data write and data read operations
US6442644B1 (en) * 1997-08-11 2002-08-27 Advanced Memory International, Inc. Memory system having synchronous-link DRAM (SLDRAM) devices and controller
US20020133665A1 (en) * 1996-01-11 2002-09-19 Jeffrey S. Mailloux Burst/pipelined edo memory device
US6470415B1 (en) * 1999-10-13 2002-10-22 Alacritech, Inc. Queue system involving SRAM head, SRAM tail and DRAM body
US20030074517A1 (en) * 2001-09-07 2003-04-17 Volker Nicolai Control means for burst access control
US6650573B2 (en) * 2001-03-29 2003-11-18 International Business Machines Corporation Data input/output method
US6661721B2 (en) * 2001-12-13 2003-12-09 Infineon Technologies Ag Systems and methods for executing precharge commands using posted precharge in integrated circuit memory devices with memory banks each including local precharge control circuits
US6704794B1 (en) * 2000-03-03 2004-03-09 Nokia Intelligent Edge Routers Inc. Cell reassembly for packet based networks
US6717847B2 (en) * 2001-09-17 2004-04-06 Sandisk Corporation Selective operation of a multi-state non-volatile memory system in a binary mode
US6717857B2 (en) * 2001-10-24 2004-04-06 Samsung Electronics Co., Ltd. Non-volatile semiconductor memory device with cache function and program, read, and page copy-back operations thereof
US6725347B2 (en) * 2001-01-16 2004-04-20 Sun Microsystems, Inc. Spin-wheel SDRAM access scheduler for high performance microprocessors
US6728845B2 (en) * 1999-08-31 2004-04-27 Intel Corporation SRAM controller for parallel processor architecture and method for controlling access to a RAM using read and read/write queues
US6728909B1 (en) * 2000-09-26 2004-04-27 Hewlett-Packard Development Company, L.P. Data communication with speculative reception of data in a data processing system
US6728838B2 (en) * 2000-08-21 2004-04-27 Texas Instruments Incorporated Cache operation based on range of addresses
US7042884B2 (en) * 2001-10-19 2006-05-09 Acute Technology Corp. Network address forwarding table lookup apparatus and method
US7047385B1 (en) * 2003-06-16 2006-05-16 Cisco Technology, Inc. High-speed memory for use in networking systems
US7062587B2 (en) * 2000-01-20 2006-06-13 Palmchip Corporation Unidirectional bus architecture for SoC applications
US7139213B2 (en) * 2003-06-02 2006-11-21 Silicon Aquarius, Inc. Multiple data path memories and systems

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4646266A (en) 1984-09-28 1987-02-24 Energy Conversion Devices, Inc. Programmable semiconductor structures and methods for using the same
US6751696B2 (en) 1990-04-18 2004-06-15 Rambus Inc. Memory device having a programmable register
US5761115A (en) 1996-05-30 1998-06-02 Axon Technologies Corporation Programmable metallization cell structure and method of making same
US5835932A (en) 1997-03-13 1998-11-10 Silicon Aquarius, Inc. Methods and systems for maintaining data locality in a multiple memory bank system having DRAM with integral SRAM
JP3871813B2 (en) 1998-08-10 2007-01-24 株式会社ルネサステクノロジ Multiport memory, a data processor and data processing system
KR100667865B1 (en) 1999-12-08 2007-01-12 가부시키가이샤 히타치세이사쿠쇼 Semiconductor device
US6728161B1 (en) 2000-06-30 2004-04-27 Micron Technology, Inc. Zero latency-zero bus turnaround synchronous flash memory
US6728798B1 (en) 2000-07-28 2004-04-27 Micron Technology, Inc. Synchronous flash memory with status burst output
US6526483B1 (en) 2000-09-20 2003-02-25 Broadcom Corporation Page open hint in transactions
EP2618301B1 (en) 2000-11-12 2016-08-03 Advanced Micro Devices, Inc. 3D rendering engine with embedded memory
US6643165B2 (en) 2001-07-25 2003-11-04 Nantero, Inc. Electromechanical memory having cell selection circuitry constructed with nanotube technology
US6724665B2 (en) 2001-08-31 2004-04-20 Matrix Semiconductor, Inc. Memory device and method for selectable sub-array activation

Patent Citations (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3931613A (en) * 1974-09-25 1976-01-06 Data General Corporation Data processing system
US4811007A (en) * 1983-11-29 1989-03-07 Tandy Corporation High resolution video graphics system
US5426603A (en) * 1993-01-25 1995-06-20 Hitachi, Ltd. Dynamic RAM and information processing system using the same
US6272577B1 (en) * 1994-07-05 2001-08-07 Monolithic System Technology, Inc. Data processing system with master and slave devices and asymmetric signal swing bus
US5745732A (en) * 1994-11-15 1998-04-28 Cherukuri; Ravikrishna V. Computer system including system controller with a write buffer and plural read buffers for decoupled busses
US5963504A (en) * 1994-12-23 1999-10-05 Micron Technology, Inc. Address transition detection in a synchronous design
US20020133665A1 (en) * 1996-01-11 2002-09-19 Jeffrey S. Mailloux Burst/pipelined edo memory device
US5936959A (en) * 1996-05-31 1999-08-10 Mmc Networks, Inc. Cell routing in ATM networks
US6128278A (en) * 1996-08-30 2000-10-03 Mmc Networks, Inc. Cell queuing in ATM switches
US20020038415A1 (en) * 1996-11-04 2002-03-28 U.S. Philips Corporation Processor architecture with independently addressable memory banks for storing instructions to be executed
US6011744A (en) * 1997-07-16 2000-01-04 Altera Corporation Programmable logic device with multi-port memory
US6317367B1 (en) * 1997-07-16 2001-11-13 Altera Corporation FPGA with on-chip multiport memory
US6442644B1 (en) * 1997-08-11 2002-08-27 Advanced Memory International, Inc. Memory system having synchronous-link DRAM (SLDRAM) devices and controller
US5856940A (en) * 1997-08-15 1999-01-05 Silicon Aquarius, Inc. Low latency DRAM cell and method therefor
US6360307B1 (en) * 1998-06-18 2002-03-19 Cypress Semiconductor Corporation Circuit architecture and method of writing data to a memory
US6427197B1 (en) * 1998-09-16 2002-07-30 Fujitsu Limited Semiconductor memory device operating in synchronization with a clock signal for high-speed data write and data read operations
US6219769B1 (en) * 1998-12-09 2001-04-17 Advanced Micro Devices, Inc. Method and system for origin-sensitive memory control and access in data processing systems
US6728845B2 (en) * 1999-08-31 2004-04-27 Intel Corporation SRAM controller for parallel processor architecture and method for controlling access to a RAM using read and read/write queues
US6470415B1 (en) * 1999-10-13 2002-10-22 Alacritech, Inc. Queue system involving SRAM head, SRAM tail and DRAM body
US7062587B2 (en) * 2000-01-20 2006-06-13 Palmchip Corporation Unidirectional bus architecture for SoC applications
US6704794B1 (en) * 2000-03-03 2004-03-09 Nokia Intelligent Edge Routers Inc. Cell reassembly for packet based networks
US6400635B1 (en) * 2000-03-15 2002-06-04 Altera Corporation Memory circuitry for programmable logic integrated circuit devices
US6556502B2 (en) * 2000-03-15 2003-04-29 Altera Corporation Memory circuitry for programmable logic integrated circuit devices
US6728838B2 (en) * 2000-08-21 2004-04-27 Texas Instruments Incorporated Cache operation based on range of addresses
US6728909B1 (en) * 2000-09-26 2004-04-27 Hewlett-Packard Development Company, L.P. Data communication with speculative reception of data in a data processing system
US6396764B1 (en) * 2000-11-16 2002-05-28 Silicon Aquarius, Inc. Segmented memory architecture and systems and methods using the same
US6725347B2 (en) * 2001-01-16 2004-04-20 Sun Microsystems, Inc. Spin-wheel SDRAM access scheduler for high performance microprocessors
US6650573B2 (en) * 2001-03-29 2003-11-18 International Business Machines Corporation Data input/output method
US20030074517A1 (en) * 2001-09-07 2003-04-17 Volker Nicolai Control means for burst access control
US6717847B2 (en) * 2001-09-17 2004-04-06 Sandisk Corporation Selective operation of a multi-state non-volatile memory system in a binary mode
US7042884B2 (en) * 2001-10-19 2006-05-09 Acute Technology Corp. Network address forwarding table lookup apparatus and method
US6717857B2 (en) * 2001-10-24 2004-04-06 Samsung Electronics Co., Ltd. Non-volatile semiconductor memory device with cache function and program, read, and page copy-back operations thereof
US6661721B2 (en) * 2001-12-13 2003-12-09 Infineon Technologies Ag Systems and methods for executing precharge commands using posted precharge in integrated circuit memory devices with memory banks each including local precharge control circuits
US7139213B2 (en) * 2003-06-02 2006-11-21 Silicon Aquarius, Inc. Multiple data path memories and systems
US7047385B1 (en) * 2003-06-16 2006-05-16 Cisco Technology, Inc. High-speed memory for use in networking systems

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7535792B2 (en) * 2006-11-07 2009-05-19 Seiko Epson Corporation Data transmission control device, and data transmission control method
US20080106961A1 (en) * 2006-11-07 2008-05-08 Seiko Epson Corporation Data transmission control device, and data transmission control method
US9361955B2 (en) 2010-01-28 2016-06-07 Hewlett Packard Enterprise Development Lp Memory access methods and apparatus
CN101916590A (en) * 2010-08-19 2010-12-15 中国科学院上海微系统与信息技术研究所 Data reading method and circuit of phase change memory
US8374051B2 (en) 2011-03-03 2013-02-12 Sandisk 3D Llc Three dimensional memory system with column pipeline
US8553476B2 (en) 2011-03-03 2013-10-08 Sandisk 3D Llc Three dimensional memory system with page of data across word lines
US9053766B2 (en) 2011-03-03 2015-06-09 Sandisk 3D, Llc Three dimensional memory system with intelligent select circuit
WO2013025656A1 (en) * 2011-08-12 2013-02-21 Gsi Technology, Inc. Systems and methods involving multi-bank, dual- or multi-pipe srams
US8982649B2 (en) 2011-08-12 2015-03-17 Gsi Technology, Inc. Systems and methods involving multi-bank, dual- or multi-pipe SRAMs
US9196324B2 (en) 2011-08-12 2015-11-24 Gsi Technology, Inc. Systems and methods involving multi-bank, dual- or multi-pipe SRAMs
CN104025196A (en) * 2011-08-12 2014-09-03 Gsi技术有限公司 Systems and methods involving multi-bank, dual- or multi-pipe srams
US9679631B2 (en) 2011-08-12 2017-06-13 Gsi Technology, Inc. Systems and methods involving multi-bank, dual- or multi-pipe SRAMs
US9146867B2 (en) 2011-10-31 2015-09-29 Hewlett-Packard Development Company, L.P. Methods and apparatus to access memory using runtime characteristics
US8856447B2 (en) * 2012-07-17 2014-10-07 Apple Inc. Converting memory accesses near barriers into prefetches
US20140025892A1 (en) * 2012-07-17 2014-01-23 Gerard R. Williams III Converting memory accesses near barriers into prefetches
US20140173170A1 (en) * 2012-12-14 2014-06-19 Hewlett-Packard Development Company, L.P. Multiple subarray memory access

Also Published As

Publication number Publication date Type
US7254690B2 (en) 2007-08-07 grant
US20040243781A1 (en) 2004-12-02 application

Similar Documents

Publication Publication Date Title
US6762948B2 (en) Semiconductor memory device having first and second memory architecture and memory system using the same
US5025421A (en) Single port dual RAM
US6163491A (en) Synchronous semiconductor memory device which can be inspected even with low speed tester
US5784705A (en) Method and structure for performing pipeline burst accesses in a semiconductor memory
US20060039227A1 (en) Memory device having staggered memory operations
US20070028027A1 (en) Memory device and method having separate write data and read data buses
US8503250B2 (en) High speed DRAM architecture with uniform access latency
US6453381B1 (en) DDR DRAM data coherence scheme
US6570791B2 (en) Flash memory with DDRAM interface
US6791898B1 (en) Memory device providing asynchronous and synchronous data transfer
US7609584B2 (en) Latency control circuit and method thereof and an auto-precharge control circuit and method thereof
US6134180A (en) Synchronous burst semiconductor memory device
US6711083B2 (en) High speed DRAM architecture with uniform access latency
US5513148A (en) Synchronous NAND DRAM architecture
US6636444B2 (en) Semiconductor memory device having improved data transfer rate without providing a register for holding write data
US20020161967A1 (en) Destructive read architecture for dynamic random access memories
US7124260B2 (en) Modified persistent auto precharge command protocol system and method for memory devices
US7433258B2 (en) Posted precharge and multiple open-page RAM architecture
US6845059B1 (en) High performance gain cell architecture
US5341488A (en) N-word read/write access achieving double bandwidth without increasing the width of external data I/O bus
US6151273A (en) Synchronous semiconductor memory device
US20020196669A1 (en) Decoding scheme for a stacked bank architecture
US20040246783A1 (en) High burst rate write data paths for integrated circuit memory devices and methods of operating same
US7272070B2 (en) Memory access using multiple activated memory cell rows
US20050114603A1 (en) Method and circuit for reading and writing an instruction buffer

Legal Events

Date Code Title Description
AS Assignment

Owner name: S. AQUA SEMICONDUCTOR, LLC, DELAWARE

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:SILICON AQUARIUS, INCORPORATED;REEL/FRAME:024707/0984

Effective date: 20070423