US20070075368A1 - CMOS inverter cell - Google Patents

CMOS inverter cell Download PDF

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Publication number
US20070075368A1
US20070075368A1 US11/503,819 US50381906A US2007075368A1 US 20070075368 A1 US20070075368 A1 US 20070075368A1 US 50381906 A US50381906 A US 50381906A US 2007075368 A1 US2007075368 A1 US 2007075368A1
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Prior art keywords
pattern
area
active area
gate
supply voltage
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Abandoned
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US11/503,819
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English (en)
Inventor
Hyuk-joon Kwon
Sang-woong Shin
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KWON, HYUK-JOON, SHIN, SANG-WOONG
Publication of US20070075368A1 publication Critical patent/US20070075368A1/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Definitions

  • the present invention relates to a layout of an inverter cell, and more particularly to a complementary metal oxide semiconductor (CMOS) inverter cell with a reduced cell area and an enhanced response speed.
  • CMOS complementary metal oxide semiconductor
  • FIG. 1 illustrates the layout of a conventional CMOS inverter cell.
  • the CMOS inverter cell 100 has a P-type MOS transistor in an upper portion and an N-type MOS transistor in a lower portion.
  • a left portion of a diffusion area 10 is a source terminal and a right portion of the diffusion area 10 is a drain terminal, and a P-type gate PGATE 1 is disposed between the source and drain terminals.
  • a first supply-voltage VDD is applied to the source terminal through a contact CNT, and an output signal OUTPUT is output from the drain terminal through a contact CNT.
  • the P-type gate PGATE 1 is connected to an external metal line LINE 1 through a contact CNT.
  • a left portion of a diffusion area 11 is a source terminal and a right portion of the diffusion area 11 is a drain terminal, and an N-type gate NGATE 1 is disposed between the source and drain terminals.
  • a second supply voltage VSS is applied to the source terminal through a contact CNT and an output signal OUPUT is output from the drain terminal through a contact CNT.
  • the N-type gate NGATE 1 is connected to the external metal line LINE 1 through a contact CNT.
  • An area AREA 1 denoted by a dotted line is prepared to form the external metal line LINE 1 through which signals are applied to the P-type gate PGATE 1 and the N-type gate NGATE 1 . Since the area AREA 1 extends in a horizontal direction outside an arbitrary area including the two diffusion areas 10 and 11 forming the P-type MOS transistor and the N-type MOS transistor, the area AREA 1 increases the horizontal length of the cell 100 .
  • the vertical length of the cell 100 depends on the widths of the P-type and N-type MOS transistors.
  • the current driving capability increases as the widths of the P-type and N-type gates PGAGE 1 and NGATE 1 increase.
  • FIG. 2 illustrates a layout of a conventional CMOS inverter cell.
  • the CMOS inverter cell 200 has a P-type MOS transistor in an upper portion and an N-type MOS transistor in a lower portion.
  • the CMOS inverter cell 200 has an external metal line LINE 2 for supplying signals from an external source to a P-type gate PGATE 2 of the P-type MOS transistor and an N-type gate NGATE 2 of the N-type MOS transistor connected to the P-type and N-type gates PGATE 2 and NGATE 2 through a contact Via-CNT and to an inter-metal line LINE 3 , and is not directly connected to the P-type gate PGATE 2 and the N-type gate NGATE 2 through a contact CNT.
  • the horizontal length of the CMOS inverter cell 200 depends on the length of an area AREA 2 denoted by a dotted line.
  • CMOS inverter cells 100 and 200 of FIGS. 1 and 2 sizable areas are used for the external metal lines LINE 1 and LINE 2 , resulting in the overall sizes of the CMOS inverter cells 100 and 200 increasing accordingly.
  • a finger gate structure is typically used, which results in an increase in the horizontal length of the inverter cell layout.
  • a CMOS inverter cell includes a gate pattern, a first active area pattem, a second active area pattern, a first metal line pattern, a second metal line pattern, a third metal line pattern, and a plurality of contacts in a cell boundary line.
  • the gate pattern extends linearly and contacts a cell boundary line.
  • the first active area pattem has a channel area overlapping the gate pattern, and a drain area and a source area disposed adjacent to the channel area.
  • the second active area pattern has a channel area overlapping the gate pattern, and a drain area and a source area disposed adjacent to the channel area.
  • the first metal line pattern extends substantially parallel to the gate pattern, contacts the cell boundary line, and is disposed on the first active area pattern.
  • the second metal line pattern extends substantially parallel to the gate pattern, contacts the cell boundary line, and is disposed on the first active area pattern.
  • the third metal line pattern extends linearly from the second metal line pattern and substantially parallel to the gate pattern, contacts the cell boundary line, and is disposed on the second active area pattern.
  • the plurality of contacts is mounted on the drain area and the source areas of the first and second active area patterns.
  • the first metal line pattern connects the drain area of the first active area pattern to the drain area of the second active area pattern through the contacts mounted on the drain area of the first active area pattern and the contacts mounted on the drain area of the second active area pattern.
  • the second metal line pattern connects the source area of the first active area pattern to a first supply voltage through the contacts mounted on the source area of the first active area pattern.
  • the third metal line pattern connects-the source area of the second active area pattern to a second supply voltage through the contacts mounted on the source area of the second active area pattern.
  • a CMOS inverter cell includes a first gate pattern, a second gate pattern, an internal connection pattern, a first active area pattern, a second active area pattern, a first metal line pattern, a second metal line pattern, a third metal line pattern, and a plurality of contacts in a cell boundary line.
  • the internal connection pattern connects the first gate pattern to the second gate pattern.
  • the first active area pattern has a channel area overlapping the first gate pattern, and a drain area and a source area disposed adjacent to the channel area.
  • the second.active, area pattern has a channel area overlapping the second gate pattern, and a drain area and a source area disposed adjacent to the channel area.
  • the first metal line pattern extends substantially parallel to the first gate pattern and the second gate pattern, contacts a cell boundary line, and is disposed on the first active area pattern.
  • the second metal line pattern extends substantially parallel to the first gate pattern, contacts the cell boundary line, and is disposed on the first active area pattern.
  • the third metal line pattern extends linearly from the second metal line pattern and substantially parallel to the second gate pattern, contacts the cell boundary line, and is disposed on the second active area pattern.
  • the plurality of contacts is mounted on the gate pattern, and the drain and source areas of the first and second active area patterns.
  • the first metal line pattern connects the drain area of the first active area pattern to the drain area of the second active area pattern through the contacts mounted on the drain area of the first active area pattern and the contacts mounted on the-drain area of the second active area pattern.
  • the second metal line pattern connects the source area of the first active area pattern to a first supply voltage through the contacts mounted on the source area of the first active area pattern.
  • the third metal line pattern connects the source area of the second active area pattern to a second supply voltage through the contacts mounted on the source area of the second active area pattern.
  • the internal connection pattern connects the first gate pattern to the second gate pattern through the contacts mounted on the first and second gate patterns.
  • FIG. 1 illustrates a layout of a conventional CMOS inverter cell
  • FIG. 2 illustrates a layout of a conventional CMOS inverter cell
  • FIG. 3 illustrates a layout of a CMOS inverter cell according to an embodiment of the present invention
  • FIG. 4 illustrates a layout of a CMOS inverter cell according to an embodiment of the present invention
  • FIG. 5 illustrates a layout of a CMOS inverter cell according to an embodiment of the present invention
  • FIG. 6 illustrates a layout of a CMOS inverter cell according to an embodiment of the present invention
  • FIG. 7 illustrates a layout of a CMOS inverter cell according to an embodiment of the present invention.
  • FIG. 8 illustrates a layout of a CMOS inverter cell according to an embodiment of the present invention.
  • FIG. 3 illustrates a layout of a CMOS inverter cell according to an embodiment of the present invention.
  • the CMOS inverter cell 300 includes a gate pattern 301 , a first active area pattern 302 , a second active area pattern 303 , a first metal line pattern 304 , a second metal line pattern 305 , a third metal line pattern 306 , a first supply voltage line 307 , a second supply voltage line 308 , a gate connection pattern 309 , and a plurality of contacts CNT.
  • the gate pattern 301 contacts one side of a cell boundary line 310 and extends in substantially a straight line.
  • the first active area pattern 302 is an active area of a P-type MOS transistor including a channel area overlapping the gate pattern 301 , and a drain area and a source area disposed at either side of the channel area.
  • the second active area pattern 303 is an active area of an N-type MOS transistor including a channel area overlapping the gate pattern 301 , and a drain area and a source area disposed at either side of the channel area.
  • Contacts CNT are respectively disposed in upper portions of the drain and source areas of the first and second active area patterns 302 and 303 .
  • One end of the first metal line pattern 304 contacts one side of the cell boundary line 310 .
  • the first metal line pattern 304 extends substantially parallel to the gate pattern 301 and transmits an output signal of the inverter cell 300 .
  • the second metal line pattern 305 extends substantially parallel to the gate pattern 301 , and one end of the second metal line pattern 305 contacts one side of the cell boundary line 310 .
  • the second and third metal lines 305 and 306 extend substantially along the same line.
  • the third metal line 306 extends substantially parallel to the gate pattern 301 , and one end of the third metal line 306 contacts the cell boundary line 310 .
  • the first metal line pattern 304 connects the drain area of the first active area pattern 302 to the drain area of the second active area pattern 303 through one of the contacts CNT mounted on the upper surface of the drain area of the first active area pattern 302 and one of the contacts CNT mounted on the upper surface of the drain area of the second active area pattern 303 .
  • the second metal line pattern 305 connects the source area of the first active area pattern 302 to a first supply voltage VDD through one of the contacts CNT mounted on the source area of the first active area pattern 302 .
  • the third metal line pattem 306 connects the source area of the second active area pattern 303 to a second supply voltage VSS through one of the contacts CNT mounted on the source area of the second active area pattern 303 .
  • the gate connection pattern 309 is formed outside the cell boundary line 310 .
  • the gate connection pattern 309 contacts a portion of the cell boundary line 310 where the N-type MOS transistor is disposed.
  • the first supply voltage VDD may be supplied through the first supply voltage line 307 and the second supply voltage VSS may be supplied through the second supply voltage line 308 .
  • the gate connection pattern 309 is made of the same material as the gate pattern 301 .
  • the gate connection pattern 309 is formed outside and contacts the cell boundary line 310 , and transmits signals to the gate pattern 301 .
  • FIG. 3 illustrates a case where the gate connection pattern 309 contacts the cell boundary line 310 where the N-type MOS transistor is disposed.
  • FIG. 4 illustrates a layout of a CMOS inverter cell according to an embodiment of the present invention.
  • the CMOS inverter cell 400 illustrated in FIG. 4 is similar to the CMOS inverter cell 300 of FIG. 3 .
  • a gate connection pattern 409 contacts a portion of a cell boundary line 410 where a P-type MOS transistor is disposed.
  • FIG. 5 illustrates a layout of a CMOS inverter cell according to an embodiment of the present invention.
  • the CMOS inverter cell 500 illustrated in FIG. 5 is similar to the CMOS inverter cell of FIG. 4 .
  • Two gate connection patterns 509 and 510 contact portions of cell boundary lines 510 where a P-type MOS transistor and an N-type MOS transistor are disposed.
  • a single gate pattern 301 , 401 , and 501 is used as a gate terminal of a P-type MOS transistor and an N-type MOS transistor.
  • the arrangement and number of the gate connection patterns 309 , 409 , 509 , and 510 for respectively supplying signals to the gate patterns 301 , 401 , and 501 can vary. Accordingly, in the CMOS inverter cell according to embodiments of the present invention, data can be transmitted to a gate pattern through one side of the cell, or data can be transmitted to a gate pattern through both sides of the cell.
  • the predetermined areas AREA 1 and AREA 2 for the external metal lines LINE 1 and LINE 2 of the conventional inverter cells 100 and 200 as illustrated in FIGS. 1 and 2 are not needed in the CMOS inverter cells 300 , 400 and 500 according to embodiments of the present invention as illustrated in FIGS. 3, 4 , and 5 .
  • CMOS inverter cells have a gate pattern of a P-type MOS transistor and a gate pattern of an N-type MOS transistor connected through, for example, a metal line.
  • the gate pattern of the P-type MOS transistor and the gate pattern of the N-type MOS transistor are made of different materials so threshold voltages can be independently adjusted.
  • FIG. 6 illustrates a layout of a CMOS inverter cell according to an embodiment of the present invention.
  • the CMOS inverter cell 600 includes a first gate pattern 601 , a second gate pattern 602 , a first active area pattern 603 , a second active area pattern 604 , a first metal line pattern 605 , a second metal line pattern 606 , a third metal line pattern 607 , a first supply voltage line 608 , a second supply voltage line 609 , a connection pattern 610 , and a plurality of contacts CNT.
  • the first gate pattern 601 and the second gate pattern 602 may be made of poly silicon.
  • the first gate pattern 601 and the second gate pattern 602 are electrically connected to each other via the connection pattern 610 through the contacts CNT.
  • the contacts CNT disposed between the first gate pattern 601 and the internal connection pattern 610 and between the second gate pattern 602 and the internal connection pattern 610 may be in the same layer as contacts CNT mounted on source and drain areas or may in different layers than the contacts CNT mounted on the source and drain areas.
  • the first active area pattern 603 is an active area of a P-type MOS transistor including a channel area overlapping the first gate pattern 601 , and a drain area and a source area disposed at either side of the channel area.
  • the second active area pattern 604 is an active area of an N-type MOS transistor including a channel area overlapping the second gate pattern 602 , and a drain area and a source area disposed at either side of the channel area.
  • the contacts CNT are mounted on the source areas and drain areas of the first active area pattern 603 and the second active area pattern 604 .
  • the first metal line pattern 605 extends substantially parallel to the first gate pattern 601 and contacts a cell boundary line 612 .
  • the second metal line pattern 606 extends substantially parallel to the second gate pattern 602 and contacts the cell boundary line 612 .
  • the third metal line pattern 607 extends along the same line as the second metal line pattern 606 , extends substantially parallel to the first gate pattern 601 and the second gate pattern 602 , and contacts the cell boundary line 612 .
  • the first metal line pattern 605 connects the drain area of the first active area pattern 603 with the drain area of the second active area pattern 604 through one of the contacts CNT mounted on the drain area of the first active area pattern 603 and one of the contacts CNT mounted on the drain area of the second active area pattern 604 .
  • the second metal line pattern 606 connects the source area of the first active area pattern 603 to a first supply voltage VDD through one of the contacts CNT mounted on the source area of the first active area pattern 603 .
  • the third metal line pattern 607 connects the source area of the second active area pattern 604 to a second supply voltage VSS through one of the contacts CNT mounted on the source area of the second active area pattern 604 .
  • a gate connection pattern 611 is mounted outside the boundary line 612 .
  • the gate connection pattern 611 contacts a portion of the cell boundary line 612 where the N-type MOS transistor is formed.
  • the first supply voltage VDD may be applied through the first supply voltage line 608 and the second supply voltage VSS may be applied through the second supply voltage line 609 .
  • the connection pattern 610 connects the first gate pattern 601 to the second gate pattern 602 .
  • the connection pattern 610 may be made of the same material as the first and second gate patterns 601 and 602 or may be formed as a metal line.
  • FIG. 7 illustrates a layout of a CMOS inverter cell according to an embodiment of the present invention.
  • the CMOS inverter cell 700 illustrated in FIG. 7 is similar to the CMOS inverter cell 600 of FIG. 6 .
  • a gate connection pattern 711 contacts a portion of a cell boundary line 712 where a P-type MOS transistor is disposed.
  • FIG. 8 illustrates a layout of a CMOS inverter cell according to an embodiment of the present invention.
  • the CMOS inverter cell 800 illustrated in FIG. 8 is similar to the CMOS inverter cells 600 and 700 of FIGS. 6 and 7 .
  • Two gate connection patterns 811 and 812 contact portions of cell boundary lines where a P-type MOS transistor and an N-type MOS transistor are disposed.
  • CMOS inverter cells 600 , 700 , and 800 a pair of gate patterns 601 and 602 , 701 and 702 , and 801 and 802 , respectively, which are separated from each other, are used as gate terminals of a P-type MOS transistor and an N-type MOS transistor. Also, the CMOS inverter cells 600 , 700 , and 800 further include internal connection patterns 610 , 710 , and 810 for connecting the gate pattern pairs 601 and 602 , 701 and 702 , and 801 and 802 .
  • data can be transmitted to a gate pattern through one side of the CMOS inverter cells 600 , 700 , and 800 or through both sides of the CMOS inverter cells 600 , 700 , and 800 .
  • the predetermined areas AREA 1 and AREA 2 for the external metal lines LINE 1 and LINE 2 of the conventional CMOS inverter cells 100 and 200 as illustrated in FIGS. 1 and 2 are not needed in the CMOS inverter cells 600 , 700 , and 800 according to embodiments of the present invention as illustrated in FIGS. 6, 7 , and 8 .
  • CMOS inverter cells 300 , 400 , 500 , 600 , 700 , and 800 according to embodiments of the present invention as illustrated in FIGS. 3 through 8 have a smaller horizontal length than the conventional CMOS inverter cells 100 and 200 as illustrated in FIGS. 1 and 2 , while providing the same driving capability and a smaller size.
  • CMOS inverter cell having greater driving capability than a conventional CMOS inverter cell
  • a finger gate structure can be adopted into a small-sized CMOS inverter cell according to an embodiment of the present invention. Accordingly, it is possible to improve the driving capability of a CMOS inverter cell while maintaining the size of a conventional CMOS inverter cell.
  • CMOS inverter cell Since a CMOS inverter cell according to embodiments of the present invention is smaller than a conventional inverter cell having the same driving capability, parasitic resistance and parasitic capacitance of the entire circuit is reduced.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
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US11/503,819 2005-08-12 2006-08-14 CMOS inverter cell Abandoned US20070075368A1 (en)

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KR10-2005-0074475 2005-08-12
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009108769A2 (en) 2008-02-27 2009-09-03 Cadbury Adams Usa, Llc Multi-region confectionery
CN106057153A (zh) * 2016-07-20 2016-10-26 武汉华星光电技术有限公司 反相器结构及其显示面板
CN106783840A (zh) * 2016-12-05 2017-05-31 武汉新芯集成电路制造有限公司 一种标准单元库的版图结构

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US222422A (en) * 1879-12-09 Improvement in manufacture of enameled cast-iron ware
US6737685B2 (en) * 2002-01-11 2004-05-18 International Business Machines Corporation Compact SRAM cell layout for implementing one-port or two-port operation
US20050093019A1 (en) * 2003-10-31 2005-05-05 Semiconductor Energy Laboratory Co., Ltd. Transistor

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Publication number Priority date Publication date Assignee Title
JP3384421B2 (ja) 1994-12-15 2003-03-10 株式会社ニコン Ｃｍｏｓ集積回路およびイメージセンサ
US20040222422A1 (en) 2003-05-08 2004-11-11 Wein-Town Sun CMOS inverter layout
KR20050028969A (ko) * 2003-09-17 2005-03-24 주식회사 하이닉스반도체 인버터 및 그 제조방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US222422A (en) * 1879-12-09 Improvement in manufacture of enameled cast-iron ware
US6737685B2 (en) * 2002-01-11 2004-05-18 International Business Machines Corporation Compact SRAM cell layout for implementing one-port or two-port operation
US20050093019A1 (en) * 2003-10-31 2005-05-05 Semiconductor Energy Laboratory Co., Ltd. Transistor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2009108769A2 (en) 2008-02-27 2009-09-03 Cadbury Adams Usa, Llc Multi-region confectionery
CN106057153A (zh) * 2016-07-20 2016-10-26 武汉华星光电技术有限公司 反相器结构及其显示面板
CN106783840A (zh) * 2016-12-05 2017-05-31 武汉新芯集成电路制造有限公司 一种标准单元库的版图结构

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