US20070002508A1 - Electrostatic discharge protection circuit - Google Patents

Electrostatic discharge protection circuit Download PDF

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Publication number
US20070002508A1
US20070002508A1 US11/395,954 US39595406A US2007002508A1 US 20070002508 A1 US20070002508 A1 US 20070002508A1 US 39595406 A US39595406 A US 39595406A US 2007002508 A1 US2007002508 A1 US 2007002508A1
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United States
Prior art keywords
scr
trigger
region
circuit
coupled
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Abandoned
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US11/395,954
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English (en)
Inventor
Pieter Vanysacker
Benjamin Van Camp
Olivier Marichal
Wybo Geert
Steven Thijs
Gerd Vermont
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Sofics Bvba
Sarnoff Corp
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Sofics Bvba
Sarnoff Corp
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Priority to US11/395,954 priority Critical patent/US20070002508A1/en
Assigned to SARNOFF CORPORATION, SARNOFF EUROPE reassignment SARNOFF CORPORATION CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT SERIAL NUMBER 11/395,464, WHICH WAS INDICATED ON THE ORIGINAL RECORDATION FORM COVER SHEET IN ERROR. PREVIOUSLY RECORDED ON REEL 018271 FRAME 0076. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECTIVE ASSIGNMENT TO CORRECT ASSIGNMENT RECORDED AT R/F 018271/0076 TO CORRECT THE SER. NO. FROM 11/395,464 TO 11/395,954. Assignors: THIJS, STEVEN, GEERT, WYBO, MARICHAL, OLIVIER, VAN CAMP, BENJAMIN, VANYSACKER, PIETER
Assigned to SARNOFF CORPORATION, SARNOFF EUROPE reassignment SARNOFF CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: VERMONT, GERD
Publication of US20070002508A1 publication Critical patent/US20070002508A1/en
Priority to US12/345,086 priority patent/US8143700B2/en
Abandoned legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/711—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements
    • H10D89/713—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices

Definitions

  • This invention generally relates to the field of electrostatic discharge (ESD) protection circuitry, and more specifically, improvements for silicon controlled rectifier (SCR) structures in the protection circuitry of an integrated circuit (IC).
  • ESD electrostatic discharge
  • SCR silicon controlled rectifier
  • ESD electrostatic discharge
  • An ESD event commonly results from the discharge of a high voltage potential (typically, several kilovolts) and leads to pulses of high current (several amperes) of a short duration (typically, 100 nanoseconds).
  • An ESD event is generated within an IC, illustratively, by human contact with the leads of the IC or by electrically charged machinery being discharged in other leads of an IC.
  • protection devices such as silicon controlled rectifiers (SCR) or MOS devices have been incorporated within the circuitry to provide a discharge path for the high current produced by the discharge of the high electrostatic potential.
  • SCR silicon controlled rectifiers
  • MOS devices MOS devices
  • the protection device Prior to an ESD event, the protection device is in a non-conductive state. Once the ESD event is detected, the protection device then changes to a conductive state to shunt the current to ground. The protection device maintains this conductive state until the voltage is discharged to a safe level.
  • FIG. 1A shows an illustration of the classical approach in which four independently triggered power clamps PC 1 120 , PC 2 122 , PC 3 124 , and PC 4 126 are used.
  • PC 1 120 and PC 3 124 are placed in a Vdd 128 power pad cell
  • PC 2 122 and PC 4 126 are placed in a Vss 130 ground pad cell.
  • the power and ground busses have a certain amount of bus resistance RVdd 132 and RVss 134 .
  • V PC 1 , V PC 2 , V PC 3 AND V PC 4 are voltages at clamps 1 , 2 , 3 and 4 respectively. Clamps PC 2 122 PC 3 124 and PC 4 126 will also trigger when the following voltage relationship becomes true: V PC2> V t1 V PC3> V t1 V PC4> V t1
  • V PC 1 V PC 2+ V dd*I
  • V PC 3 V PC 2+ R Vss*I
  • V PC4 V PC 2+ 2*R Vss*I
  • Clamps PC 1 120 , PC 3 124 and PC 4 126 will also trigger when the following voltage relationship becomes true: V PC1> V t1 V PC3> V t1 V PC4> V t1
  • the clamp PC 4 128 which is closest to the ground pad has the biggest chance to trigger next. However, whether PC 4 126 and other clamps will trigger depends greatly on two factors. First, Vt2 being great than Vt1 or not, and second on the size of the bus resistance between the different clamps.
  • FIG. 1B depicts a schematic diagram of a prior art multi-fingered SCR ESD protection circuit 100 , which serves as protection circuitry for an integrated circuit (not shown).
  • the circuit 100 having multiple SCR fingers, and is illustratively depicted in FIG. 1B having three SCR “fingers” 102 , 104 and 106 . Each finger works as a separate clamp, but is layouted as one whole clamp.
  • the SCR protection circuit 100 comprises a first trigger device 108 , a first SCR 102 (i.e.
  • the first SCR 102 further comprises PNP transistor and an NPN transistor.
  • the first SCR 102 includes an anode 108 , which is connected to a pad (not shown) and to one side of a resistor 114 .
  • the resistor 114 represents the resistance of the N-well (or an external resistor), which is seen at the base of the PNP transistor of the SCR 102 .
  • a cathode 112 which is connected to a ground (not shown) and to one side of a resistor 110 .
  • the resistor 110 represents the resistance of the P-well (or an external resistor) which is seen at the base of NPN transistor.
  • the second and third SCRs 104 and 106 are formed exactly in the same manner as described with regard to the first SCR 102 .
  • SCRs 102 , 104 , 106 are placed in parallel as shown in FIG. 1B multifinger triggering is a potential issue.
  • the typical solution is to connect a first triggering device G 1 116 and/or a second triggering device G 2 118 , as shown in FIG. 1B such that the voltage drop seen by all anode/G 2 respectively G 1 /Cathode diodes is the same.
  • the structure acts like a PIN diode, such that the G 1 and G 2 taps do not control the voltage at the Nwell/Pwell junction anymore. This renders the multifinger triggering solution of connection the gates of the different SCRs ineffective. Therefore, there is a need in the art for a multi-fingered SCR protection device having an enhanced and reliable triggering mechanism.
  • a SCR in its basic form is depicted as a prior art in FIG. 1C with an anode 136 and cathode 138 . It is regarded as a PNPN structure, formed by P+, N ⁇ well, P-substrate and N+.
  • SCR's When using SCR's to protect a chip against ESD, one SCR is needed for each possible current path. As seen in FIG. 1C , each SCR takes some area to implement. The large number of clamps (each current path needs its own clamp) increases the needed area for the ESD protection. So, there is a need in the art to incorporate different clamps into one clamp and also to couple these clamps to overcome the disadvantages of the prior art.
  • an electrostatic discharge (ESD) protection circuit comprising at least a clamp having at least one first anode coupled to a first voltage potential and at least one first cathode coupled to a second voltage potential. Also included is at least a second clamp having at least one second anode coupled to a third voltage potential and at least one second cathode coupled to the fourth voltage potential.
  • the clamps are scr's.
  • the first and second cathodes have at least one first high-doped region and the first and second anodes have at least one second high-doped region.
  • the circuit further includes at least one first trigger tap disposed proximate to the first high-doped region of the first cathode and at least one second trigger-tap disposed proximate to the first high-doped region of he second cathode. Additionally, at least one first low ohmic connection is coupled between the first and second trigger-tap to connect the first and second silicon controlled rectifiers.
  • an electrostatic discharge (ESD) protection circuit comprising a silicon controlled rectifier (SCR) having a plurality of SCR fingers.
  • SCR silicon controlled rectifier
  • Each SCR finger includes an anode and cathode.
  • a boost circuit is connected to the anode or cathode.
  • the scr comprises at least one first trigger-tap. Additionally, at least one first low-ohmic connection is respectively coupled between the at least one trigger tap of each SCR finger.
  • an electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit comprising at least a first silicon controlled rectifier including at least one first region having a first conductive type formed in a second region having a second conductive type opposite to the first conductive type and at least one third region having a second conductive type formed in a fourth region having a first conductive type, said first region type coupled to a first voltage potential and said third conductive element coupled to a second voltage potential
  • the circuit further comprises at least a second silicon controlled rectifier including at least one fifth region having a first conductive element formed in a sixth region having a second conductive type and at least one seventh region having a second conductive element formed in a eighth region having a first conductive type, said fifth conductive element coupled to a third voltage potential and said seventh conductive element coupled to a fourth voltage potential;
  • FIG. 1A depicts an illustration of a prior art classical approach of uncoupled ESD protection clamps.
  • FIG. 1B depicts a schematic diagram of a prior art multi-fingered SCR ESD protection circuit.
  • FIG. 1C depicts a layout of a cross-section diagram of a prior art SCR
  • FIG. 2 depicts an illustrative schematic diagram of different possible schematics for interconnecting ESD clamps in another embodiment of the present invention.
  • FIG. 3 depicts an illustrative schematic diagram of different possible schematics for connecting SCR clamps with enhanced coupling technique in another embodiment of the present invention.
  • FIG. 4 depicts an illustrative schematic diagram of different possible schematics for connecting SCR clamps with an enhanced coupling technique with reference to FIG. 3 in an alternate embodiment of the present invention.
  • FIG. 5 depicts an illustrative schematic diagram of an alternate embodiment with reference to FIG. 4 of the present invention.
  • FIG. 6 depicts an illustrative schematic diagram of one embodiment of a multi-fingered SCR ESD protection circuit of the present invention.
  • FIG. 7 depicts an illustrative schematic diagram of an alternate embodiment with reference to FIG. 6 of the present invention.
  • FIG. 8A depicts an illustrative cross-section diagram of a structure for ESD protection according to one embodiment of the present invention.
  • FIG. 8B depicts an illustrative cross-section diagram of a structure for ESD protection according to an alternate embodiment of the present invention.
  • FIG. 9A and FIG. 9B depicts an illustrative schematic diagram of an alternate embodiment with reference to FIG. 8A of the present invention.
  • FIG. 10 depicts an illustrative cross-section diagram of an SCR for ESD protection according to another embodiment of the present invention.
  • FIG. 11A and FIG. 11B depict an illustrative circuit diagram of the SCR for ESD protection according to an alternate embodiment of the present invention.
  • FIG. 12A and FIG. 12B depict an illustrative circuit diagram of an alternate embodiment with reference to FIG. 11A and FIG. 11B respectively.
  • FIG. 13 depicts an illustrative cross-section diagram of an SCR for ESD protection according to an another embodiment of the present invention.
  • FIG. 14 depicts an illustrative cross-section diagram of an SCR for ESD protection according to an another embodiment of the present invention.
  • FIG. 15A and FIG. 15B depicts an illustrative circuit diagram of an alternate embodiment with reference to FIG. 14 of the present invention.
  • a novel coupled clamping technique which ensures multi-clamp triggering.
  • the novelty of this embodiment is the coupling of the trigger gates of the separate clamps through low-ohmic connections, such as metal lines, or preferably feeding the triggering signal simultaneously to the trigger gates of the different clamps, or preferably making the anode and/or cathode of the clamps in the same active well, so as to ease the triggering of a network of clamps.
  • the invention relates to the principle in which, when one certain ESD clamp triggers, it enables or triggers another ESD clamp or a group of other ESD clamps.
  • FIG. 2 a generic representation of the invention is shown illustrating different possible schematics 200 for interconnecting ESD clamps to provide simultaneous triggering.
  • clamps (n) 202 which are interconnected in order to trigger each other.
  • the anodes and cathodes are connected to nodes(n) 204 such as node 1 , node 2 , node 3 and node 4 . They are connected preferably to different protected nodes (n) 204 , as well as the same nodes (n) 204 as illustrated in FIG. 4A and FIG. 4B respectively.
  • the clamps 202 can be preferably be connected between any possible nodes 204 . They can have separate nodes 204 or common nodes 204 , or a combination of both.
  • clamp 202 Whenever one clamp 202 triggers, it provides a voltage or current to the other clamps 202 it is connected with to trigger those other clamps 202 . Principally when a first clamp triggers, a part of the current will be tapped and used as a (current) signal or converted to a (voltage) signal which enables a second clamp to trigger, as well as any number of other clamps.
  • the clamps are the power clamps of different power domains.
  • GGNMOS based clamps they can be connected in a fashion as used with enhanced multi-finger triggering techniques as like domino-triggering.
  • their triggering gates G 1 or G 2 can be connected together.
  • FIG. 3 depicts an illustrative schematic diagram of different possible schematics for connecting SCR clamps with enhanced coupling technique in another embodiment of the present invention.
  • an ESD protection circuit 300 is shown, having a first SCR clamp 302 and a second SCR clamp 304 .
  • SCR clamp 302 includes a first anode 306 coupled to a first voltage potential Vdd 308 connected to a pad of the circuitry (not shown) and a first cathode 310 coupled to a second voltage potential Vss 312 preferably connected to ground (not shown).
  • a first trigger tap G 1 a 314 connected to a triggering device/element (not shown) is disposed proximate to the first cathode 310 and a third trigger tap G 2 a 316 is disposed proximate to the first anode 306 as shown in FIG. 3 .
  • a first resistor Rg 1 a 318 is connected parallel to the first cathode 310 and a second resistor Rg 2 a 320 is connected parallel to the first anode 306 .
  • SCR clamp 304 includes a second anode 322 coupled to the Vdd 308 and a second cathode 324 coupled to the Vss 312 .
  • FIG. 5C illustrates connecting the first trigger tap G 1 a 314 to third trigger tap G 2 a 316 and connecting second trigger tap G 1 b 326 to fourth trigger tap G 2 b 328 .
  • this circuit shown in FIG. 3 is not limited to two clamps, but can be applied to any number of clamps.
  • the first trigger tap G 1 a 314 and second trigger tap G 1 b 326 are shown as two separate trigger taps, however, they are essentially one trigger tap G 1 .
  • the third trigger tap G 2 a 316 and fourth trigger tap G 2 b 328 are shown as two separate trigger taps, but the are considered essentially one trigger tap G 2 .
  • no trigger elements or devices are drawn in FIG. 3 , however any of the SCR's can have a trigger element apart from the shared trigger line, i.e. an external on-chip triggering devices coupled to the trigger taps.
  • GGNMOS triggered SCR clamps (GGSCR's) where the GGNMOS is connected between G 2 tap and ground of any or some SCR's and where the G 1 tap of any SCR is connected to G 1 of any other SCR.
  • GGSCR clamps where the GGNMOS is connected between G 2 and ground of any or some SCR's, and where the G 2 tap of any SCR is connected to G 2 of any other SCR.
  • G 1 a 314 -G 1 b 326 connection 330 is fabricated from low ohmic connection, preferably metal lines, the current will flow through the metal lines. If the SCR's have a shared Pwell, carriers generated from the first SCR 302 in the Pwell will also trigger the other SCR 304 . Note that all of this can also be done by alternatively by connecting the G 2 gates of SCR's together with a low ohmic connection 330 in the same fashion as shown in FIG. 3 b . Furthermore, in another alternative embodiment, both G 1 nodes of SCR 302 and G 2 nodes of SCR 304 can be connected with low ohmic connection 330 as shown in FIG. 3 c in order to stimulate triggering of the clamps. This technique can be applied to any number of SCR's.
  • boost circuitry can be inserted into the schematic. This boost circuit causes the trigger voltage to increase, thus triggering other SCR's more easily. Depicted in FIG. 4 are some possible implementations of this boost circuit as described in detail below.
  • FIG. 4 there is illustrated a schematic diagram of different possible schematics for connecting SCR clamps of FIG. 3 with an enhanced multi-fingering technique in an alternate embodiment of the present invention.
  • a first boost circuit 402 a connected in series with the first cathode 310 of the first SCR 302 and a second boost circuit 402 b connected in series to the second cathode 324 of the second SCR 304 .
  • the boost circuit 402 a will have a certain voltage drop over it, thus effectively increasing the voltage on node G 1 a 314 . This increased voltage will ease triggering of the other SCR 304 .
  • FIG. 4 ( a ) a first boost circuit 402 a connected in series with the first cathode 310 of the first SCR 302 and a second boost circuit 402 b connected in series to the second cathode 324 of the second SCR 304 .
  • the boost circuit 402 a will have a certain voltage drop over it, thus effectively increasing the voltage on node G 1
  • boost circuit 402 only one boost circuit 402 is connected in series with the G 1 a 314 -G 1 b 326 .
  • This circuit amplifies the signal coming from one SCR 302 or 304 , boosting the other SCR 304 or 302 respectively.
  • the amplifier can be constructed to operate in a single direction as well as to operate in both directions. Note that although, not shown more implementations are possible, for example where a boost circuit 402 would be connected in series with the Vdd line and the anode of each SCR 302 and 304 .
  • the boost circuit 402 is here a diode 404 as shown in FIG. 6A or a string of diodes 404 as shown in FIG. 6B .
  • an SCR 302 or 304 is inactive (high resistive state)
  • no current will flow through its series diode(s) 404 , thus no voltage drop will exist over the diode(s) 404 .
  • an SCR 302 or 304 is active (low resistive state)
  • high ESD current will flow through the SCR and it's series diodes 404 . In this case, every diode 404 will build up by approximately 1V.
  • the voltage on the G1 connection line will be boosted by 1V*number of series diodes. (i.e. 1V multiplied by number of series diodes). This condition will facilitate the triggering of other SCR's. In order to tune the performance of the whole circuit, the number of diodes can be altered.
  • this boost circuit 402 could also comprise one of the devices such as a MOS, resistor, capacitor, inductor or any other device that has a resistance
  • each of the boost circuit 402 may preferably be included in only one of the SCR fingers or in any possible combination of two or more SCR fingers.
  • coupling multiple clamps can preferably be used, for example, in multiple SCR fingers to simulate synchronous triggering of the clamps.
  • the problem of triggering is not only with different clamps but also in one clamp, provided by a multi-fingered SCR ESD protection circuit as described herein below.
  • FIG. 6 depicts an illustrative schematic diagram embodiment of a multi-fingered SCR ESD protection circuit 600 of the present invention which serves as protection circuitry for an integrated circuit (not shown). Similar to FIG. 1B , the SCR circuit 600 comprises multiple SCR fingers, and is illustratively depicted in FIG. 6 having three SCR “fingers” 102 , 104 and 106 .
  • the SCR protection circuit 600 comprises first SCR 102 (i.e. “first finger”), a second SCR 104 (i,e, “second finger”) and a third SCR 106 (i.e. “third finger”).
  • the first SCR 102 further comprises PNP transistor and an NPN transistor.
  • the first SCR 102 includes at least one anode 108 , as known in the art, is one interspersed high-doped first region formed within a first lightly doped region.
  • the anode 108 is connected to a first voltage potential, preferably a pad (not shown) and to one side of a resistor R 1 114 .
  • the resistor R 1 114 represents the resistance of the N-well (or an external resistor), which is seen at the base of the PNP transistor of the SCR 102 .
  • a at least one cathode 112 is a interspersed high-doped second region formed within a second lightly doped region.
  • the cathode 112 is connected to a second voltage potential, preferably ground (not shown) and to one side of a resistor R 2 110 .
  • the resistor R 2 110 represents the resistance of the P-well (or an external resistor) which is seen at the base of NPN transistor 106 .
  • the circuit 600 comprises a boost circuit 602 connected to the cathode 112 or alternatively to the anode 108 as shown in FIG. 6 .
  • the boost circuit provides an additional voltage drop at a trigger tap ( 116 or 118 in FIG. 6 ) as the trigger current runs through the boost circuit.
  • the boost circuit 602 of FIG. 6 may preferably be one or more diodes 702 as shown in an alternate embodiment of a multi-fingered SCR ESD protection circuit 700 in FIG.
  • this boost circuit 602 could also comprise one of the devices such as a MOS, resistor, capacitor, inductor or any other device that has a resistance
  • the second and third SCRs 104 and 106 are formed exactly in the same manner as described with regard to the first SCR 102 .
  • a first triggering device (not shown in the figure) represented by a node G 1 116 is connected to the cathode 112 for supplying current to each of the SCR fingers 102 , 104 , 106 .
  • a second triggering device represented by a node G 2 118 connected to the anode 108 such that the voltage drop seen by all anode/G 2 respectively G 1 /Cathode diodes is the same.
  • the boost circuit 602 is connected to the cathode 112 .
  • the G 1 node 116 will be pushed higher with respect to ground. Therefore, fluctuations in G 1 -Cathode voltage will be relatively smaller.
  • G 1 node 116 Since the G 1 node 116 will be pushed higher, the current will be uniformly distributed over all the cathodes. In other words, the current flowing through the boost circuit 602 at the cathode 112 of the SCR finger 102 will build up enough voltage to be more uniformly distributed over all the other SCR fingers 104 and 106 to trigger. Also, as G 1 node 116 has a higher potential, more current will flow through the R 1 110 resistor. Since more current will flow through the R 1 110 resistor, less current will initially flow through the cathode of the SCR. This gives the other fingers more time to trigger, relaxing the multifinger triggering issue. Note that although not shown here, G 2 connections 118 can be also made. Perhaps skilled in the art will understand that pushing G 2 118 lower by adding a boost-like circuit 602 between the first voltage potential (not shown) and anode 108 will create a similar effect.
  • each boost circuit 602 may preferably be included in only one of the SCR fingers or in any possible combination of two or more SCR finger.
  • the structure 800 is basically an SCR with preferably at least two anodes 802 and 804 or at least two cathodes 806 and 808 .
  • the purpose is if one of the inherent SCR's get triggered, the other SCR's in the structures will tend to trigger as well because all SCR parasitics share the same well (the base of all parasitic bipolars are connected by the well resistance). This behavior is especially wanted for CDM stress.
  • the protection structure is also an element that can protect the chip against ESD stress along several current paths at the same time.
  • an input pin not shown
  • placing such a structure could not only protect the chip for stress from input to the first voltage potential Vdd 508 , but also for stress from input to the second voltage potential Vss 512 .
  • two elements were needed to achieve this protection, one element for each current path.
  • FIG. 8B a generic cross section of the SCR structure 800 is shown in FIG. 8B with three anodes 802 , 804 and 810 and three cathodes 806 , 808 and 812 .
  • An inherent or parasitic SCR is shown in dashed line as will be described in greater detail below with reference to FIG. 8A .
  • the number of anodes and cathodes doesn't need to be three. Neither does the number of anodes and cathodes need to be equal. There can for example be two anodes and one cathode, or one anode and four cathodes or any number of combinations can be possible.
  • additional elements may be added as well. This includes, but is not limited to trigger elements or structures that alter the holding voltage such as diodes in series with the invention.
  • the structure 800 consists of two P+ regions 801 in the same N ⁇ well 803 , located next to two N+ regions 805 in the P ⁇ substrate 807 .
  • This structure comprises 4 parasitic bipolars, bipoloar 1 814 , bipolar 2 816 , bipolar 3 818 and bipolar 4 820 , creating 3 inherent SCR's.
  • the first SCR is created by parasitic bipolar 2 816 & parasitic bipolar 4 820 and exists between Vdd 508 and Vss 512 .
  • the second one is an SCR created by parasitic bipolar 2 816 and parasitic bipolar 1 814 between Vdd 508 and a PAD 840 .
  • PAD 840 represents the bonding pad of an IO pin (not shown).
  • the third one is an SCR created by parasitic bipolar 3 818 & parasitic bipolar 4 820 between the PAD 840 and Vss 512 . Both the second SCR and the third SCR act as a local clamp here.
  • the advantage of this structure is that when one of the three SCRs gets triggered, the other ones can trigger as well, if current is supplied to the anodes.
  • the placement of the N+ 805 and P+ 801 regions is of big importance.
  • Both solutions will differ on trigger speed, resistance during conducting state and other factors such as trigger voltage. Those who are skilled in the art will know how to design the structure in such a way to get optimal ESD performance from it.
  • FIG. 9 illustrates a schematic representation 900 of the structure from FIG. 8A with addition of holding diodes 902 .
  • Depicted in FIG. 9A are the addition of holding diodes 902 .
  • Depicted in FIG. 9B is a possible example where each of the three possible ESD paths 904 has two holding diodes 902 in series. The three paths 904 are shown in dashed lines in FIG. 9B .
  • the protection structure of FIG. 9 represents the one from FIG. 8A and consists of an SCR with 2 anodes 802 and 804 , and two cathodes 806 and 808 .
  • FIG. 9 illustrates a schematic representation 900 of the structure from FIG. 8A with addition of holding diodes 902 .
  • Depicted in FIG. 9A are the addition of holding diodes 902 .
  • Depicted in FIG. 9B is a possible example where each of the three possible ESD paths 904 has two holding diodes 902 in series. The three paths 904 are
  • Vdd 508 to Vss 512 can have 2 holding diodes 902 , while the paths from Vdd 508 to IO 906 and from IO 906 to Vss 512 may preferably have no diodes. In this case, the anti-parallel diodes at the IO 906 line can be left out.
  • FIG. 10 there is shown a cross-section diagram of the SCR structure 1000 in FIG. 10 . It is made by having the invention inherent in an output driver due to parasitic elements.
  • the SCR structure 1000 with two anodes and two cathodes is created in an output driver.
  • the structure 1000 is totally inherent to the driver.
  • the layout of this driver can be altered for an optimal working of the structure.
  • Both the NMOS 1002 and PMOS 1004 from the driver stage create the SCR's. By removing the sides of each of P+ guardband 1003 and N+ guardband 1005 band in between the two MOS transistors 1002 and 1004 , a structure that can easily latch is created.
  • the structure has two anodes, formed by the drain and source of the PMOS 1004 , as well as two cathodes formed by the drain and source of the NMOS 1002 .
  • An SCR between Out PAD 1008 and Vss 512 is created and uses the Drain of the PMOS as anode.
  • Another SCR between Vdd 508 and Out PAD 1008 uses the drain of the NMOS cathode.
  • This embodiment thus shows the intended creation of an SCR with multiple anodes and cathodes in an output buffer to create an ESD protection structure, which simultaneously works as a power clamp between Vdd 508 and Vss 512 and as a local ESD protection for the output pad.
  • the holding voltage of the parasitic SCR between Vdd and Vss can be above the normal Vdd voltage.
  • the trigger current can be increased above the latch up current (I latch ). This can be done by making the G 2 (N+ in N ⁇ well) to Vdd connection and the G 1 (P+ in P ⁇ well) to VSS connection low ohmic. In other words, the bulk ties in N ⁇ well and/or P ⁇ well need to be well placed in order to lower the well resistances.
  • the drain/source regions can be swapped, both for the NMOS as for the PMOS driver. This would reduce the length Anode/Cathode (LAC) spacing of the inherent SCR and thus improve its speed LAC is the distance between the anode and the cathode. Note that this will also affect the performance of the SCR's between Vdd and PAD, and PAD and Vss.
  • LAC Anode/Cathode
  • Triggering of the intrinsic SCR can be done by adding a trigger circuit 1102 to the bulk ties of MOS devices as illustrated in the circuit 1100 of FIG. 11 .
  • FIG. 11A illustrates adding a trigger circuit 1102 via gate G 2 1104 to the PMOS and
  • FIG. 11B illustrates adding a trigger circuit 1102 via gate G 1 1106 to the NMOS.
  • the trigger circuit 1102 preferably consists of four diodes 1202 .
  • this trigger circuit 1102 can consist of any elements, both passive (diodes, resistors, inductances, capacitances, etc.) and/or active elements (MOS devices, SCRS, etc.).
  • FIG. 12A shows a possible implementation including the trigger circuit 1102 of FIG.
  • FIG. 12B includes the trigger circuit 1102 of FIG. 11B with four diodes 1108 .
  • the resistance R 2 of FIG. 12A and the resistance R 1 of FIG. 12B can preferably be both intrinsic or externally added. The value of these resistances will determine the trigger current of the SCR. Making these resistances small will increase the latch up immunity of the clamp.
  • FIG. 13 illustrates a cross-section diagram consisting of an SCR 1300 with two anodes 1302 & 1304 and two cathodes 1306 & 1308 . It is used in a chip (not shown) with two power domains.
  • the first domain is connected at nodes of a first voltage potential Vdd 1 1310 and second voltage potential Vss 1 1312 .
  • the second domain is connected to nodes of a third voltage potential Vdd 2 1314 and a fourth voltage potential Vss 2 1316 .
  • the first and third voltage potentials Vdd 1310 and Vdd 2 1314 respectively, have equivalent values, preferably connected to a pad of the circuitry (not shown).
  • the second and the fourth voltage potentials Vss 1 1312 and Vss 2 1316 respectively, have equivalent values, preferably connected to a ground (not shown).
  • the power clamp at the other domain tends to trigger as well when current is flowing there.
  • CDM Charge Device Model
  • the different power domains on a chip have mostly a different capacitance. This means that during CDM, one domain can discharge faster than another domain. Such situation can possibly cause too much voltage difference between power domains on a chip.
  • the Vdd and Vss line of all domains can be clamped tightly together, preventing too much potential difference between them.
  • Holding diodes can be added in series with the Vdd 1 1310 and/or Vdd 2 1314 terminal as desired to raise the holding voltage of the power clamp for a certain power domain. This can be done for each power domain independently. Even though, the present invention shows an embodiment with two power domains as shown in FIG. 13 , it can also be applied for chips with more than two power domains.
  • An even further embodiment of the present invention includes a triggering scheme for triggering of the SCR as shown in cross section diagram 1400 of FIG. 14 .
  • Triggering the structure can happen by sending current through the N-well. In order to be able to do this, an N+ region is added to the N ⁇ well.
  • the triggering scheme includes a string of two diodes 1402 and 1404 connected in series from the newly created N ⁇ well connection to Vss 512 . This is similar to the diode triggering scheme of a conventional SCR.
  • Vdd 508 -Vss 512 When the voltage Vdd 508 -Vss 512 reaches about 3 V, the diodes 1402 and 1404 will conduct and current will flow from Vdd 508 to Vss 512 through the P+/N ⁇ diode and the two external diodes. This is indicated by dashed line “ 1 ” in FIG. 14 .
  • the voltage at which current starts to flow is dependent on the number of trigger diodes.
  • the trigger current will forward bias the base of the parasitic transistor in the N-well and thus turn on the SCR between Vdd 508 and Vss 512 . Triggering can also happen due to an excess voltage on the PAD 840 with respect to Vss 512 as shown by dashed line “ 2 ” in FIG. 14 .
  • the same trigger mechanism is applied here, only the other parasitic PNP in the N ⁇ well gets forward biased now.
  • the P ⁇ substrate is connected to Vss 512 by a resistor 1406 in order to prevent unwanted triggering by substrate noise, etc. Note that this resistor will have influence on the trigger speed of the circuit. A low ohmic resistor will cause slow triggering.
  • FIG. 15A A schematic representation of these triggering paths of FIG. 14 is illustrated in FIG. 15A .
  • FIG. 15B a variation of the trigger scheme as an alternate embodiment of the present invention. Only trigger diode 1502 is added here between the N ⁇ well and the P ⁇ well of the invention. There are now three possible trigger paths. The first one is for excess voltage between Vdd 508 and Vss 512 and is indicated by “ 1 ” similar to FIG. 15A . The second one is indicated by “ 2 ” and current will flow here for an over voltage between PAD 840 and Vss 512 similar to FIG. 15A . An additional third trigger path marked with “ 3 ” will start to conduct current and trigger the structure for excess voltage between Vdd 508 and PAD 512 .

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  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Emergency Protection Circuit Devices (AREA)
US11/395,954 2005-03-30 2006-03-30 Electrostatic discharge protection circuit Abandoned US20070002508A1 (en)

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US20100118454A1 (en) * 2008-11-12 2010-05-13 Ming-Dou Ker Esd protection circuitry with multi-finger scrs
US20110026176A1 (en) * 2009-07-31 2011-02-03 Kim Jang-Hoo Esd protection circuit
DE102009039247A1 (de) * 2009-08-28 2011-04-21 Austriamicrosystems Ag Halbleiterkörper mit einer Anschlusszelle
US20110204415A1 (en) * 2010-02-22 2011-08-25 Sofics Bvba High holding voltage device
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US8659859B1 (en) * 2010-06-15 2014-02-25 Ambarella, Inc. Electrostatic discharge protection scheme for high-definition multimedia interface transmitters
US20150001679A1 (en) * 2009-03-11 2015-01-01 Renesas Electronics Corporation Esd protection element
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US9041054B2 (en) 2010-02-22 2015-05-26 Sofics Bvba High holding voltage electrostatic discharge protection device
US20200021109A1 (en) * 2018-07-12 2020-01-16 Globalfoundries Inc. Electrostatic discharge clamp structures
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US20250107244A1 (en) * 2023-09-25 2025-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Electrostatic discharge diodes with different sizes and methods of manufacturing thereof

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US8906751B2 (en) 2011-01-06 2014-12-09 International Business Machines Corporation Silicon controlled rectifiers (SCR), methods of manufacture and design structures
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US7272802B2 (en) * 2005-05-11 2007-09-18 Lsi Corporation R-cells containing CDM clamps
US20060259892A1 (en) * 2005-05-11 2006-11-16 Lsi Logic Corporation R-cells containing CDM clamps
US8956924B2 (en) 2008-06-12 2015-02-17 Infineon Technologies Ag Method of forming a semiconductor device including a silicon controlled rectifier
US20090309129A1 (en) * 2008-06-12 2009-12-17 Krzysztof Domanski Semiconductor ESD Device and Method of Making Same
US8471292B2 (en) 2008-06-12 2013-06-25 Infineon Technologies Ag Semiconductor ESD device and method of making same
US7800128B2 (en) * 2008-06-12 2010-09-21 Infineon Technologies Ag Semiconductor ESD device and method of making same
US20100321843A1 (en) * 2008-06-12 2010-12-23 Krzysztof Domanski Semiconductor ESD Device and Method of Making Same
US9263430B2 (en) 2008-06-12 2016-02-16 Infineon Technologies Ag Semiconductor ESD device and method of making same
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US20100118454A1 (en) * 2008-11-12 2010-05-13 Ming-Dou Ker Esd protection circuitry with multi-finger scrs
US8379354B2 (en) * 2008-11-12 2013-02-19 United Microelectronics Corp. ESD protection circuitry with multi-finger SCRS
US20150001679A1 (en) * 2009-03-11 2015-01-01 Renesas Electronics Corporation Esd protection element
US9177949B2 (en) * 2009-03-11 2015-11-03 Renesas Electronics Corporation ESD protection element
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US20110026176A1 (en) * 2009-07-31 2011-02-03 Kim Jang-Hoo Esd protection circuit
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DE102009039247A1 (de) * 2009-08-28 2011-04-21 Austriamicrosystems Ag Halbleiterkörper mit einer Anschlusszelle
DE102009061167B3 (de) * 2009-08-28 2015-03-05 Austriamicrosystems Ag Halbleiterkörper mit einer Anschlusszelle
DE102009039247B4 (de) * 2009-08-28 2011-09-01 Austriamicrosystems Ag Halbleiterkörper mit einer Anschlusszelle
DE102009039247B9 (de) * 2009-08-28 2012-01-26 Austriamicrosystems Ag Halbleiterkörper mit einer Anschlusszelle
US8653557B2 (en) 2010-02-22 2014-02-18 Sofics Bvba High holding voltage electrostatic discharge (ESD) device
US9041054B2 (en) 2010-02-22 2015-05-26 Sofics Bvba High holding voltage electrostatic discharge protection device
US20110204415A1 (en) * 2010-02-22 2011-08-25 Sofics Bvba High holding voltage device
US8659859B1 (en) * 2010-06-15 2014-02-25 Ambarella, Inc. Electrostatic discharge protection scheme for high-definition multimedia interface transmitters
US8456785B2 (en) 2010-10-25 2013-06-04 Infineon Technologies Ag Semiconductor ESD device and method
US20200021109A1 (en) * 2018-07-12 2020-01-16 Globalfoundries Inc. Electrostatic discharge clamp structures
US11201466B2 (en) * 2018-07-12 2021-12-14 Globalfoundries U.S. Inc. Electrostatic discharge clamp structures
US11791626B2 (en) 2018-07-12 2023-10-17 Globalfoundries U.S. Inc. Electrostatic discharge clamp structures
US20230402448A1 (en) * 2022-06-14 2023-12-14 Analog Devices, Inc. Electrostatic discharge protection for high speed transceiver interface
US11942473B2 (en) * 2022-06-14 2024-03-26 Analog Devices, Inc. Electrostatic discharge protection for high speed transceiver interface
US20250107244A1 (en) * 2023-09-25 2025-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Electrostatic discharge diodes with different sizes and methods of manufacturing thereof
US12402416B2 (en) * 2023-09-25 2025-08-26 Taiwan Semiconductor Manufacturing Company, Ltd. Electrostatic discharge diodes with different sizes and methods of manufacturing thereof

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WO2007040612A2 (en) 2007-04-12
US8143700B2 (en) 2012-03-27
WO2007040612A3 (en) 2009-04-16
CN101558498A (zh) 2009-10-14
WO2007040612A9 (en) 2007-06-28
US20090101938A1 (en) 2009-04-23

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