US20060148174A1 - Method for forming recess gate of semiconductor device - Google Patents

Method for forming recess gate of semiconductor device Download PDF

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US20060148174A1
US20060148174A1 US11/148,557 US14855705A US2006148174A1 US 20060148174 A1 US20060148174 A1 US 20060148174A1 US 14855705 A US14855705 A US 14855705A US 2006148174 A1 US2006148174 A1 US 2006148174A1
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gate
polysilicon layer
forming
region
layer pattern
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US7071059B1 (en
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Hyung Kim
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled

Abstract

A method for forming a recess gate of a semiconductor device is disclosed. The method for forming a recess gate of a semiconductor device comprises forming a polysilicon layer pattern covering a contact region on a semiconductor substrate, etching a predetermined thickness of the semiconductor substrate in the active region using the polysilicon layer pattern as an etching mask to form a recess gate region, and forming and patterning the gate polysilicon layer, the gate conductive layer and the gate hard mask layer to form a recess gate.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention
  • The present invention generally relates to a method for forming a recess gate of a semiconductor device, and more specifically, to a method for forming a recess gate of a semiconductor device wherein a contact region is formed by depositing a polysilicon layer pattern covering the contact region prior to the formations of a recess gate region and a gate structure to suppress increase in resistance of the contact region and tWR (Write Recovery time) characteristics.
  • 2. Description of the Related Art
  • FIG. 1 is a cross-sectional view illustrating a conventional method for forming a recess gate of a semiconductor device.
  • Referring to FIG. 1, a predetermined region of a semiconductor substrate 10 where a channel region is to be formed is etched to form a recess gate region (not shown). Thereafter, a gate oxide film (not shown) is formed in the recess gate region.
  • Next, a planarized polysilicon layer (not shown) filling up the recess gate region is formed on the entire surface. A stacked structure of a gate conductive layer and a gate hard mask layer is then formed on the planarized polysilicon layer.
  • Afterward, the stacked structure and the polysilicon layer are patterned to form a gate structure including a polysilicon layer pattern 30, a gate conductive layer pattern 40 and a gate hard mask layer pattern 50. Thereafter, a spacer 60 is formed on a sidewall of the gate structure.
  • In accordance with the above-described conventional method for forming a recess gate of a semiconductor device, when misalignment between a device isolation film and the gate structure occurs resistance of a storage node contact region of one cell of the two sharing one active region occurs due to overlay.
  • Moreover, the misalignment between the device isolation film and the gate structure causes the storage contact region to be not completely exposed in a subsequent etching process for forming a landing plug contact hole. As a result, the tWR characteristic of the device is deteriorated.
    • SUMMARY OF THE INVENTION
  • Accordingly, it is an object of the present invention to provide a method for forming a recess gate of a semiconductor device wherein a contact region is formed by depositing a polysilicon layer pattern covering the contact region prior to the formations of a recess gate region and a gate structure to suppress increase in resistance of the contact region and tWR characteristics.
  • In order to achieve above object of the present invention in accordance with a preferred embodiment, there is provided a method for forming a recess gate of a semiconductor device, comprising the steps of:
  • (a) forming a polysilicon layer pattern on a semiconductor substrate having an active region, the polysilicon layer pattern covering a contact region;
  • (b) forming an insulating film covering the polysilicon layer pattern;
  • (c) etching the semiconductor substrate using the polysilicon layer pattern as an etching mask to form a recess gate region in the active region;
  • (d) forming a planarized gate polysilicon layer at least filling up the recess gate region;
  • (e) depositing a gate conductive layer and a gate hard mask layer on the gate polysilicon layer to form a stacked structure of the gate polysilicon layer, the gate conductive layer and the gate hard mask layer;
  • (f) etching the stacked structure to form a gate structure, whereby the insulating film is exposed;
  • (g) forming a spacer on a top surface and a sidewall of the gate structure;
  • (h) removing the exposed insulating film to expose the polysilicon layer pattern; and
  • (i) depositing a polysilicon film on the exposed polysilicon layer pattern in the contact region to form a landing plug.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a cross-sectional view illustrating a conventional method for forming a recess gate of a semiconductor device.
  • FIGS. 2 a through 2 j are cross-sectional views illustrating a method for forming a recess gate of a semiconductor device in accordance with a preferred embodiment of the present invention.
    • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
  • Reference will now be made in detail to exemplary embodiments of the present invention. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
  • FIGS. 2 a through 2 d illustrate a method for forming a recess gate of a semiconductor device according to a preferred embodiment of the present invention.
  • Referring to FIG. 2 a, a device isolation film 110 defining an active region is formed on a semiconductor substrate 100.
  • Referring to FIG. 2 b, a polysilicon layer 120 is formed on the entire surface including a surface of the semiconductor substrate 100. A first photoresist film pattern 130 covering a contact region and exposing a recess gate region is then formed on the polysilicon layer 120.
  • Referring to FIG. 2 c, the polysilicon layer 120 is etched using the first photoresist film pattern 130 as an etching mask to form a polysilicon layer pattern 125 covering the contact region. Thereafter, the first photoresist film pattern 130 is removed.
  • Referring to FIG. 2 d, an insulating film 155 covering the polysilicon layer pattern 125 is formed. Preferably, the insulating film 155 comprises a stacked structure of an oxide film 140 and a nitride film 150. The insulating film 155 prevents attack on the polysilicon layer pattern 125 during the formation process of a recess gate region 160 in the active region.
  • Referring to FIG. 2 e, a predetermined thickness of the semiconductor substrate 100 is etched using the polysilicon layer pattern 125 including the insulating film 155 as an etching mask to form the recess gate region 160 in the active region. Preferably, the predetermined thickness of the semiconductor substrate 100 etched ranges from 80 nm to 150 nm.
  • Referring to FIG. 2 f, a planarized gate polysilicon layer 170 at least filling up the recess gate region 160 is formed on the entire surface.
  • Next, a gate conductive layer 180 and a gate hard mask layer 190 are formed on the planarized gate polysilicon layer 170 to form a stacked structure of the gate polysilicon layer 170, a gate conductive layer 180 and a gate hard mask layer 190. A thickness of the gate polysilicon layer 170 may be greater than that of the stacked structure of the polysilicon layer pattern 125 and the insulating film 155. The gate conductive layer 180 may comprise a tungsten layer or a tungsten silicide layer to reduce resistance of a gate.
  • Moreover, the gate hard mask layer 190 may comprise a nitride film to prevent a SAC (Self Align Contact) fail in a subsequent process for forming a landing plug contact hole.
  • Thereafter, a second photoresist film pattern 200 defining a gate region is formed on the gate hard mask layer 190.
  • Referring to FIG. 2 g, the stacked structure is etched using the second photoresist film pattern 200 as an etching mask to form a gate structure 205 including a gate polysilicon layer pattern 175, a gate conductive layer pattern 185 and a gate hard mask layer pattern 195 and expose the insulating film 155.
  • Referring to FIG. 2 h, a spacer 210 covering the gate structure 205 is formed. The spacer 210 preferably comprises a nitride film.
  • Referring to FIG. 2 i, the exposed insulating film 155 on the contact region is removed.
  • Referring to FIG. 2 j, the space between the gate structures 205 including the spacer 210 is filled up with a polysilicon film to form a landing plug 220.
  • As described above, the method for forming a recess gate of a semiconductor device in accordance with the present invention provides an improved resistance characteristic of the contact region and tWR characteristic of the device by forming a polysilicon layer pattern covering a contact region and to secure the contact region prior to formation of a gate structure.
  • As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiment is not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the metes and bounds of the claims, or equivalences of such metes and bounds are therefore intended to be embraced by the appended claims.

Claims (3)

1. A method for forming a recess gate of a semiconductor device, comprising the steps of:
(a) forming a polysilicon layer pattern on a semiconductor substrate having an active region, the polysilicon layer pattern covering a contact region;
(b) forming an insulating film covering the polysilicon layer pattern;
(c) etching a predetermined thickness of the semiconductor substrate using the polysilicon layer pattern as an etching mask to form a recess gate region in the active region;
(d) forming a planarized gate polysilicon layer at least filling up the recess gate region;
(e) depositing a gate conductive layer and a gate hard mask layer on the gate polysilicon layer to form a stacked structure of the gate polysilicon layer, the gate conductive layer and the gate hard mask layer;
(f) etching the stacked structure to form a gate structure, whereby the insulating film is exposed;
(g) forming a spacer on a top surface and a sidewall of the gate structure;
(h) removing the exposed insulating film to expose the polysilicon layer pattern; and
(i) depositing a polysilicon film on the exposed polysilicon layer pattern in the contact region to form a landing plug.
2. The method according to claim 1, wherein the insulating film comprises a stacked structure of an oxide film and a nitride film.
3. The method according to claim 1, wherein the predetermined thickness of the semiconductor substrate in the step (c) ranges from 80 nm to 150 nm.
US11/148,557 2004-12-30 2005-06-09 Method for forming recess gate of semiconductor device Expired - Fee Related US7071059B1 (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080003832A1 (en) * 2006-06-29 2008-01-03 Hynix Semiconductor Inc. Method for fabricating recess gate of semiconductor device
US20090023277A1 (en) * 2007-07-20 2009-01-22 Hynix Semiconductor Inc. Method for fabricating semiconductor device
US20110003459A1 (en) * 2009-07-03 2011-01-06 Jong-Han Shin Method for fabricating buried gate using pre landing plugs

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100846099B1 (en) 2007-01-30 2008-07-14 삼성전자주식회사 Method of manufacturing semiconductor device including recessed channel transistor
KR100951566B1 (en) * 2007-03-15 2010-04-09 주식회사 하이닉스반도체 Method for manufacturing semiconductor device with recess gate
KR100851921B1 (en) * 2007-07-02 2008-08-12 주식회사 하이닉스반도체 Method for forming trench in semiconductor device and method for forming recess gate using the same
KR100849192B1 (en) * 2007-08-13 2008-07-30 주식회사 하이닉스반도체 Method for fabricating semiconductor device
KR100945229B1 (en) 2008-01-02 2010-03-03 주식회사 하이닉스반도체 Method for manufacturing semiconductor device
KR101095739B1 (en) 2010-12-17 2011-12-21 주식회사 하이닉스반도체 Semiconductor device and method for forming the same

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6777737B2 (en) * 2001-10-30 2004-08-17 International Business Machines Corporation Vertical DRAM punchthrough stop self-aligned to storage trench
US20050079661A1 (en) * 2003-10-13 2005-04-14 Cho Min-Hee Recessed gate transistor structure and method of forming the same
US20050196947A1 (en) * 2003-12-23 2005-09-08 Hyeoung-Won Seo Recess type MOS transistor and method of manufacturing same
US20050199930A1 (en) * 2004-03-10 2005-09-15 Hyeoung-Won Seo Transistor of a semiconductor device having a punchthrough protection layer and methods of forming the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6777737B2 (en) * 2001-10-30 2004-08-17 International Business Machines Corporation Vertical DRAM punchthrough stop self-aligned to storage trench
US20050079661A1 (en) * 2003-10-13 2005-04-14 Cho Min-Hee Recessed gate transistor structure and method of forming the same
US20050196947A1 (en) * 2003-12-23 2005-09-08 Hyeoung-Won Seo Recess type MOS transistor and method of manufacturing same
US20050199930A1 (en) * 2004-03-10 2005-09-15 Hyeoung-Won Seo Transistor of a semiconductor device having a punchthrough protection layer and methods of forming the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080003832A1 (en) * 2006-06-29 2008-01-03 Hynix Semiconductor Inc. Method for fabricating recess gate of semiconductor device
US20090023277A1 (en) * 2007-07-20 2009-01-22 Hynix Semiconductor Inc. Method for fabricating semiconductor device
US7833868B2 (en) * 2007-07-20 2010-11-16 Hynix Semiconductor Inc. Method for fabricating a semiconductor device having recessed gate electrode and elevated source and drain regions
US20110003459A1 (en) * 2009-07-03 2011-01-06 Jong-Han Shin Method for fabricating buried gate using pre landing plugs
US8357600B2 (en) 2009-07-03 2013-01-22 Hynix Semiconductor Inc. Method for fabricating buried gate using pre landing plugs
US8753966B2 (en) * 2009-07-03 2014-06-17 SK Hynix Inc. Method for fabricating buried gates using pre landing plugs

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KR20060077542A (en) 2006-07-05
US7071059B1 (en) 2006-07-04

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