US20060033141A1 - Method of manufacturing a semiconductor device having trenches for isolation and capacitor - Google Patents
Method of manufacturing a semiconductor device having trenches for isolation and capacitor Download PDFInfo
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- US20060033141A1 US20060033141A1 US11/248,309 US24830905A US2006033141A1 US 20060033141 A1 US20060033141 A1 US 20060033141A1 US 24830905 A US24830905 A US 24830905A US 2006033141 A1 US2006033141 A1 US 2006033141A1
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Images
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
Abstract
At least not less than one capacitor formation trench providing an uneven surface is formed on the surface of a capacitor formation region. Thus, the surface area of a capacitor is increased, which enables improvement of the capacitance of the capacitor is increased, which enables improvement of the capacitance of the capacitor per unit area. Further, by forming the capacitor formation trench and an element formation trench that are formed in the surface of the semiconductor substrate by the same step, it is possible to simplify the manufacturing process. Whereas, a dielectric film of the capacitor in the capacitor formation region and a high-voltage insulating film in a MISFET formation region are formed by the same step; alternatively, the dielectric of the capacitor in the capacitor formation region and a memory gate interlayer film between a polysilicon layer and a polysilicon layer in the memory cell formation region are formed by the same step.
Description
- This application is a Continuation application of Application No. 10/408,353, filed Apr. 8, 2003, the contents of which are incorporated herein by reference in their entirety.
- The present invention relates to a method of manufacture of a semiconductor device, and to the semiconductor device. More particularly, it relates to a method of forming a capacitor in conjunction with a semiconductor device.
- In recent years, with the trend toward smaller size, lower power consumption, and higher integration of a semiconductor device, the operating voltage of a semiconductor device has become increasingly lower, and the is voltage supplied from an external power source has become increasingly lower. Under such circumstances, a semiconductor device is typically equipped with a booster circuit, such as a charge pump circuit, for generating the operating voltage needed by the semiconductor device from the external power supply voltage. This kind of booster circuit includes a capacitor (capacitive element) which is formed of, for example, a MIS capacitive element utilizing a MISFET (Metal Insulator Semiconductor Field Effect Transistor) as the capacitor.
- Japanese Unexamined Patent Publication No. 2001-85633 (hereinafter referred to as the first example) discloses the following technology: In a semiconductor device having a nonvolatile memory, the capacitance of a capacitor of a charge pump circuit is formed such that a first capacitance between a first gate and a second gate and a second capacitance between the first gate and a well region are connected in parallel to each other. As a result, the area of the charge pump circuit is reduced.
- Japanese Unexamined Patent Publication No. Hei 11 (1999)-251547 (hereinafter referred to as the second example) discloses the following technology: A first trench capacitor is formed which constitutes the memory cell of a DRAM (Dynamic Random Access Memory), and a second trench capacitor, having almost the same configuration as that of the first trench capacitor, is formed in another region. The second trench capacitor is also used as a capacitor in a region other than that of the DRAM.
- Japanese Unexamined Patent Publication No. 2002-222924 (hereinafter referred to as the third example) discloses a technology for simultaneously forming a trench for element isolation and a desired pattern in a region where a capacitive element is formed in a semiconductor substrate.
- In the above-mentioned first example, the boosted voltage value is proportional to the area of the capacitor. For this reason, if the area is reduced with a reduction in size of the device, the areas of a first gate and a second gate are reduced. As a result, the capacitance is reduced. Therefore, in order to form a high-voltage stable booster circuit, the area of the capacitors required for a charge pump circuit must be increased.
- In the above-mentioned second example, the number of manufacturing steps is unfavorably increased, because a capacitor having almost the same configuration as that of the memory cell of the DRAM is formed.
- In the above-mentioned third example, a dielectric film and a wiring layer are formed for forming the capacitive elements. Accordingly, the number of manufacturing steps for respectively forming them is undesirably increased.
- It is therefore an object of the present invention to provide a technology which enables an improvement of the capacitor capacitance per unit area.
- Further, it is another object of the present invention to provide a technology for simplifying the manufacturing process in the formation of a semiconductor device having capacitors.
- The foregoing and other objects and novel features of the present invention will be apparent from the following description as provided in this specification and from the accompanying drawings.
- Out of the aspects of the present invention disclosed in this application, the general outlines of typical ones will be described as follows.
- Namely, in accordance with the present invention, in a semiconductor device having semiconductor elements, such as MISFETs, and capacitors (capacitive elements) on a semiconductor device, each of the capacitors (capacitive elements) is formed of a plurality of capacitor formation trenches formed in a capacitor formation region, a capacitor dielectric film formed on the capacitor formation region including the inside of the plurality of the capacitor formation trenches, and a capacitor electrode. As a result, it is possible to increase the surface area of the capacitor, and, thereby, to improve the capacitor capacitance per unit area.
- Further, in a method of manufacturing a semiconductor device having semiconductor elements, such as MISFETs, and capacitors (capacitive elements) on a semiconductor substrate, at least not less than one capacitor formation trench is formed by a step of forming an element isolation trench for isolation between the semiconductor elements in the semiconductor substrate. As a result, it is possible to increase the surface area of the capacitor, and, thereby, to improve the capacitor capacitance per unit area. In addition, it is possible to simplify the manufacturing process. The capacitor formation trench is formed in the shape of a hole or a stripe. Also, by forming it in this manner, it is possible to increase the surface area of the capacitor, and, thereby, to improve the capacitor capacitance per unit area.
- Still further, in accordance with the present invention, in the step of forming a gate oxide film of the MISFETs, the capacitor dielectric film is formed on the capacitor formation trenches. As a result, it is possible to simplify the manufacturing process. Herein, the MISFETs include a MISFET for high voltage and a MISFET for low voltage. It is also possible to use the gate insulating film of the high-voltage MISFET and the gate insulating film of the low-voltage MISFET differently for different purposes.
- Furthermore, in accordance with the present invention, a memory cell is formed, including a first memory gate insulating film, a first conductive film formed on the first memory gate insulating film, and a second memory gate insulating film formed on the first conductive film. The second memory gate insulating film and the capacitor dielectric film disposed on the capacitor formation trenches are formed by the same step. As a result, it is possible to simplify the manufacturing process. Further, by using the second memory gate insulating film of the memory cell as the capacitor dielectric film in place of the gate insulating film of the MISFETs, it is possible to improve the reliability of the capacitor dielectric film and to simplify the manufacturing process.
- Representative examples of a semiconductor device in accordance with typical aspects of the present invention will be briefly described as follows.
- (1) A semiconductor device comprises: semiconductor elements; element isolation trenches, each for effecting isolation between the semiconductor elements; capacitor formation trenches; and capacitor electrodes, each formed inside the capacitor formation trenches via a capacitor dielectric film, characterized in that the capacitor formation trenches are formed by a step of forming the element isolation trenches in a semiconductor substrate.
- (2) A semiconductor device comprises: semiconductor elements; element isolation trenches, each for effecting isolation between the semiconductor elements; a gate insulating film formed on MISFETs of the semiconductor elements; capacitor formation trenches; a capacitor dielectric film formed in the capacitor formation trenches; and capacitor electrodes formed on the capacitor dielectric film, characterized in that the capacitor dielectric film and the gate insulating film are formed of a dielectric film of the same layer.
- (3) A semiconductor device comprises: semiconductor elements; element isolation trenches, each for effecting isolation between the semiconductor elements; a gate insulating film formed on MISFETs of the semiconductor elements; gate electrodes formed on the gate insulating film; capacitor formation trenches; a capacitor dielectric film formed in the capacitor formation trenches; and capacitor electrodes formed on the capacitor dielectric film, characterized in that the capacitor electrodes and the gate electrodes are formed of a dielectric film of the same layer.
- (4) A semiconductor device comprises: semiconductor elements;
- memory cells; element isolation trenches, each for effecting isolation between the semiconductor elements; an electric charge storage layer formed in the memory cells; a memory gate insulating film formed on the electric charge storage layer; capacitor formation trenches; a capacitor dielectric film formed in the capacitor formation trenches; and capacitor electrodes formed on the capacitor formation trenches, characterized in that the capacitor dielectric film and the memory gate insulating film are formed of a dielectric film of the same layer.
- (5) A semiconductor device comprises: semiconductor elements; memory cells; element isolation trenches, each for effecting isolation between the semiconductor elements; an electric charge storage layer formed in the memory cells; capacitor formation trenches; a capacitor dielectric film formed in the capacitor formation trenches; and capacitor electrodes formed on the capacitor dielectric film, characterized in that the capacitor electrodes and the electric charge storage layer are formed of a conductive film of the same layer.
- (6) A semiconductor device comprises: semiconductor elements; memory cells; element isolation trenches, each for effecting isolation between the semiconductor elements; an electric charge storage layer formed in the memory cells; a memory gate insulating film formed on the electric charge storage layer; memory gate electrodes formed on the memory gate insulating film; capacitor formation trenches; a capacitor dielectric film formed in the capacitor formation trenches; and capacitor electrodes formed on the capacitor dielectric film, characterized in that the capacitor electrodes and the memory gate electrodes are formed of a conductive film of the same layer.
- (7) A semiconductor device comprises: semiconductor elements; element isolation trenches, each for effecting isolation between the semiconductor elements; a gate insulating film formed in MISFETs of the semiconductor elements; gate electrodes formed on the gate insulating film; memory cells; an electric charge storage layer formed in the memory cells; a memory gate insulating film formed on the electric charge storage layer; memory gate electrodes formed on the memory gate insulating film; capacitor formation trenches; a capacitor dielectric film formed in the capacitor formation trenches; and capacitor electrodes formed on the capacitor dielectric film, characterized in that the capacitor electrodes, the gate electrodes, and the memory gate electrodes are formed of a conductive film of the same layer.
- (8) The semiconductor device according to the item (1), wherein the depth of the capacitor formation trenches is substantially equal to the depth of the element isolation trenches.
- (9) The semiconductor device according to the item (1), wherein the capacitor formation trenches are formed in the shape of holes, stripes, or a matrix.
- (10) The semiconductor device according to the item (2), wherein the MISFETs include a first MISFET for high voltage and a second MISFET for low voltage, and the thickness of the gate insulating film of the first MISFET is larger than the thickness of the gate insulating film of the second MISFET.
- (11) The semiconductor device according to the item (7), wherein the memory gate insulating film and the capacitor dielectric film include a multilayer film composed of a silicon oxide film and a silicon nitride film.
- (12) The semiconductor device according to the item (7), wherein the electric charge storage layer includes a silicon nitride film or a Si nano-dot.
- (13) The semiconductor device according to the item (7), wherein the electric charge storage layer is formed of a polysilicon film.
- (14) The semiconductor device according to the item (7), wherein the memory gate electrode includes a polysilicon film.
- (15) The semiconductor device according to the item (1), wherein the capacitor dielectric film and each of the capacitor electrodes are formed on a plurality of the capacitor formation trenches.
- (16) The semiconductor device according to the item (15), wherein the plurality of the capacitor formation trenches are formed in the shape of holes, stripes, or a matrix.
- (17) A semiconductor device comprises a capacitor having a plurality of capacitor formation trenches formed in a capacitor formation region, a capacitor dielectric film, and capacitor electrodes formed on the capacitor formation region, including the inside of the plurality of the capacitor formation trenches.
- (18) The semiconductor device according to the item (17), wherein the plurality of the capacitor formation trenches are formed in a well region; the well region forms one electrode of the capacitor; and the capacitor electrode forms another electrode of the capacitor.
- (19) The semiconductor device according to the item (17), wherein the plurality of the capacitor formation trenches are formed in the shape of holes, stripes, or a matrix.
- (20) The semiconductor device according to the item (7), further comprising capacitors, each including the capacitor formation trenches, the capacitor dielectric film, and the capacitor electrodes; and a charge pump circuit formed of a plurality of the capacitors, and a plurality of the MISFETs, wherein the charge pump circuit is electrically connected to the memory gate electrodes.
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FIG. 1 is a plan view of basic parts of a semiconductor device, including a memory cell, a MISFET and a capacitor, representingEmbodiment 1 of the present invention; -
FIG. 2 is a cross sectional view of the respective parts of one version of the semiconductor device, as seen along line A-A′, B-B′ and C-C′; respectively, inFIG. 1 ; -
FIG. 3 is a cross sectional view of the respective parts of another version of the semiconductor device, as seen along lines B-B′ and C-C′; respectively, inFIG. 1 ; -
FIG. 4 is a cross sectional view of the respective parts of the semiconductordevice representing Embodiment 1 of the present invention, during a step in the manufacturing process thereof; -
FIG. 5 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 4 ; -
FIG. 6 is a plan view of the respective parts of the semiconductor device as it appears during a manufacturing step, showing an example of the capacitor formation trenches; -
FIG. 7 is a plan view of the respective parts of the semiconductor device as it appears during a manufacturing step, showing an example of the capacitor formation trenches; -
FIG. 8 is a plan view of the respective parts of the semiconductor device as it appears during a manufacturing step, showing an example of the capacitor formation trenches; -
FIG. 9 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 5 ; -
FIG. 10 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 9 ; -
FIG. 11 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 10 ; -
FIG. 12 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 11 ; -
FIG. 13 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 12 ; -
FIG. 14 is a plan view of the respective parts of the semiconductor device as it appears during a manufacturing step, showing a resist pattern used as a mask; -
FIG. 15 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 13 ; -
FIG. 16 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 15 ; -
FIG. 17 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step; -
FIG. 18 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 17 ; -
FIG. 19 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 18 ; -
FIG. 20 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 16 ; -
FIG. 21 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 20 ; -
FIG. 22 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 21 ; -
FIG. 23 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 22 ; -
FIG. 24 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 23 ; -
FIG. 25 is a plan view of the respective parts of the semiconductor device as it appears during a manufacturing step, showing a resist cover; -
FIG. 26 is a cross sectional view of the respective parts of a semiconductor device representing anEmbodiment 2 of the present invention; -
FIG. 27 is a cross sectional view of the respective parts of the semiconductordevice representing Embodiment 2 of the present invention, during a step in the manufacturing process thereof; -
FIG. 28 is a plan view of the respective parts of the semiconductor device as it appears during a manufacturing step, showing a resist pattern; -
FIG. 29 is a cross sectional view of the respective parts of a semiconductor device representing anEmbodiment 3 of the present invention; -
FIG. 30 is a cross sectional view of the respective parts of the semiconductordevice representing Embodiment 3 of the present invention, during a step in the manufacturing process thereof; -
FIG. 31 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 30 ; -
FIG. 32 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 31 ; -
FIG. 33 is a cross sectional view of the MISFET portion of a semiconductor device as it appears during a manufacturing step forEmbodiment 3 of the present invention; -
FIG. 34 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 32 ; -
FIG. 35 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 33 ; -
FIG. 36 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 34 ; -
FIG. 37 is a cross sectional view of the respective parts of a semiconductor device representing anEmbodiment 4 of the present invention; -
FIG. 38 is a cross sectional view of the respective parts of the semiconductordevice representing Embodiment 4 of the present invention, showing a step in the manufacturing process thereof; -
FIG. 39 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 38 ; -
FIG. 40 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 39 ; -
FIG. 41 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 40 ; -
FIG. 42 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 41 ; -
FIG. 43 is a cross sectional view of the respective parts of a semiconductor device representing anEmbodiment 5 of the present invention; -
FIG. 44 is a cross sectional view of the respective parts of the semiconductordevice representing Embodiment 5 of the present invention, showing a step in the manufacturing process thereof; -
FIG. 45 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 44 ; -
FIG. 46 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 45 ; -
FIG. 47 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 46 ; -
FIG. 48 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 47 ; -
FIG. 49 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 48 ; -
FIG. 50 is a cross sectional view of the respective parts of a semiconductor device representing Embodiment 6 of the present invention; -
FIG. 51 is a cross sectional view of the respective parts of the semiconductor device representing Embodiment 6 of the present invention, showing a step in the manufacturing process thereof; -
FIG. 52 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 51 ; -
FIG. 53 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 52 ; -
FIG. 54 is a cross sectional view of the respective parts of the semiconductor device as it appears during a manufacturing step subsequent to the step ofFIG. 53 ; and -
FIG. 55 is a circuit diagram of a charge pump circuit of the present invention. - The present invention will be described by way of various embodiments with reference to the accompanying drawings. Incidentally, throughout the drawings, elements having the same function are represented by the same reference numerals and characters, and a repeated description thereof is omitted.
-
FIG. 1 shows a plan view of the basic parts of a semiconductor device having a nonvolatile memory, which represents one embodiment of the present invention.FIG. 1 shows the plan view of a memory cell of the nonvolatile memory on the left-hand side, a MISFET at the central part, and a capacitor (capacitive element) on the right-hand side.FIG. 2 shows cross sectional diagrams of the memory cell on the left-hand side, a MISFET for high voltage (a high-voltage MISFET) at the central part, and a capacitor on the right-hand side, which correspond to cross sectional diagrams taken along the lines A-A′, B-B′, and C-C′ ofFIG. 1 , respectively. The capacitor shown inFIG. 2 uses a gate insulating film of the high-voltage MISFET as its dielectric film. -
FIG. 3 shows the respective cross sectional diagrams of a MISFET for low voltage (a low-voltage MISFET) on the left-hand side and a capacitor on the right-hand side, which are the cross sectional diagrams taken along B-B′ and C-C′ ofFIG. 1 , respectively. The capacitor shown inFIG. 3 uses a gate insulating film of the low-voltage MISFET as its dielectric film. - Thus, the right-hand side of
FIG. 2 shows a capacitor formation region in which a high-voltage gate insulating film of the MISFET is used as the capacitor dielectric film. Whereas, the right-hand side ofFIG. 3 shows a capacitor formation region in which a low-voltage gate insulating film is used as the capacitor dielectric film. Herein,FIG. 3 shows only a MISFET and capacitor that are different in configuration from those ofFIG. 2 . - First, the basic configuration in this
embodiment 1 will be described by reference to FIGS. 1 to 3. - On a
semiconductor substrate 1, a memory cell of a nonvolatile memory, a MISFET, and a capacitor are formed. Incidentally, as the MISFET, an N-channel type MISFET is shown, but a P-channel type MISFET is not shown for simplification of the following description. - The memory cell is mainly composed of a memory tunnel insulating film (first memory gate insulating film ) 9 formed on a P-type impurity layer (P-type well region) 7 formed on the
semiconductor substrate 1, a floatinggate electrode 10 which is an electric charge storage layer, a control gate electrode (memory gate electrode) 17 a formed on the floatinggate electrode 10, asilicon oxide film 18 formed on thecontrol gate electrode 17 a, a memory gate interlayer film (second memory gate insulating film) 11 formed between the floatinggate electrode 10 and thecontrol gate electrode 17 a, asidewall 26 formed on the sidewall of a memorygate electrode structure 20, an N-type impurity layer 23 a serving as a drain region, and an N-type impurity layer 23 b serving as a source region formed in the P-type impurity layer (P-type well region). Incidentally, the memorygate electrode structure 20 is formed of the memorytunnel insulating film 9, the floatinggate electrode 10, the memorygate interlayer film 11, thecontrol gate electrode 17 a, and thesilicon oxide film 18. - The memory tunnel insulating film (first memory gate insulating film) 9 is composed of, for example, a thermal oxide film. The memory gate interlayer film (second memory gate insulating film) 11 is composed of, for example, a so-called NONO film in which a silicon nitride film is formed on an oxide film, another oxide film is formed on the silicon nitride film, and another silicon nitride film is formed on the oxide film.
- The floating
gate electrode 10, which is an electric charge storage layer, is formed of, for example, a polysilicon film. The control gate electrode (memory gate electrode) 17 a is formed of, for example, a multilayer film of a polysilicon film and a silicide film, such as a cobalt silicide (CoSi) film. - The control gate electrode (memory gate electrode) 17 a is electrically connected to a word line.
- A
wiring layer 33 constitutes a bit line, and it is electrically connected to the N-type impurity layer 23 a serving as a drain region. Aplug layer 33 a forms a source line, and it is electrically connected to the N-type impurity layer 23 b serving as a source region. Thewiring layer 33 and theplug layer 33 a are formed of a metal film of, for example, tungsten (W), or copper (Cu). - In the memory cell, writing of data is performed in the following manner. For example, a ground voltage (0 V) is applied to the source region; a voltage of about 5 V is applied to the N-
type impurity layer 23 a; and a voltage of about 10 V is applied to thecontrol gate electrode 17 a. Thus, hot electrons are injected and stored in the floatinggate electrode 10, which is an electric charge storage layer. - Data erasure is performed in the following manner. For example, 10 V is applied to the P-type impurity layer (P-type well region); the source/drain regions are open; and a high voltage of about −10 V of an inverse potential to that for writing is applied to the
control gate electrode 17 a. Thus, the electrons stored in the floatinggate electrode 10, which is an electric charge storage layer, are drawn to the P-type impurity layer (P-type well region) 7 by electron tunneling through the memory tunnel insulating film (first memory gate insulating film) 9. - Reading of data is performed in the following manner. For example, 0 V is applied to the source region; about 1 V is applied to the drain region; and about 2 to 4 V is applied to the
control gate electrode 17 a. - Thus, in the writing/erasing operation of the nonvolatile memory cell, a high voltage whose absolute value is higher relative to the ground voltage (0 V) is required. On the other hand, with the desire for reduction in size and power consumption, the trend toward a lower voltage is accelerating down to use of a ground voltage (0 V) for an external power supply voltage Vss to be supplied from an external power source, and down to about 1.8 to 3.3 V for use as an external power supply voltage Vcc. Such being the case, a booster circuit, such as a charge pump circuit is mounted on the semiconductor substrate to generate the respective high voltages from the external power sources. Incidentally, the term high voltage denotes a voltage whose absolute value is higher than the external power supply voltage. In the nonvolatile memory in this embodiment, a high voltage of not less than about 10 V is required.
- For this reason, the MISFETs constituting the peripheral circuit comprises high-voltage MISFETs having a high-voltage
gate insulating film 16 and low-voltage MISFETs having a low-voltagegate insulating film 15 as their respective gate insulating films. The MISFET whose gate electrode or source/drain is to be applied with a high voltage is composed of a high-voltage MISFET. - The capacitor (capacitive element) has a MIS capacitive element formed by utilizing the high-voltage MISFET formation step, and a MIS capacitive element formed by utilizing the low-voltage MISFET formation step.
- The booster circuit, such as a charge pump circuit, is composed of these MISFETs and capacitors. It is noted that the high-voltage
gate insulating film 16 is formed to have a larger thickness than the thickness of the low-voltagegate insulating film 15. - Element isolation is provided between the semiconductor elements, such as low-voltage MISFETs, high-voltage MISFETs, and capacitors, by
element isolation trenches 4 and an element isolation insulating film embedded in theelement isolation trenches 4. Namely, the element isolation is achieved by theelement isolation trenches 4 in the semiconductor element formation regions, such as the high-voltage MISFET formation regions, the low-voltage MISFET formation regions, and the capacitor formation regions. - An N-channel type high-voltage MISFET is mainly composed of the high-voltage
gate insulating film 16 formed as the gate insulating film of the MISFET on the P-type impurity layer (P-type well region) 7 formed in thesemiconductor substrate 1, agate electrode 17 b of the MISFET formed on thegate insulating film 16 of the high-voltage MISFET, thesidewall 26 formed on the sidewall of agate electrode structure 21 composed of thegate electrode 17 b and asilicon oxide film 18, and N-type impurity layers 24 a and 27 a b serving as source/drain regions formed in the P-type impurity layer (P-type well region) 7. The N-type impurity layers 24 a and 27 a are electrically connected to awiring layer 34 a. - The high-
voltage gate electrode 17 b is formed of a conductive film of the same layer as the control gate electrode (memory gate electrode) 17 a of the memory cell. - A capacitor (MIS capacitive element) C formed by utilizing the high-voltage MISFET formation step is mainly composed of a
dielectric film 16 a of the capacitor formed by the step of forming the gate insulating film of the high-voltage MISFET oncapacitor formation trenches 4 a formed in an N-type impurity layer (N-type well region) 8 in thesemiconductor substrate 1, and acapacitor electrode 17 c formed by the step of forming thegate electrode 17 b of the high-voltage MISFET. Whereas, anupper electrode structure 22 of the capacitor is formed of thecapacitor electrode 17 c and thesilicon oxide film 18. - Namely, the
capacitor formation trench 4 a is formed by using the lo same step as the step of forming theelement isolation trench 4 for isolation between the semiconductor elements, such as MISFETs. Thedielectric film 16 a of the capacitor is formed on the side and the bottom of thecapacitor formation trench 4 a. Thecapacitor electrode 17 c is formed in such a manner as to fill in thecapacitor formation trench 4 a via thedielectric film 16 a of the capacitor. - Incidentally, the formation of the N-type impurity layer (N-type well region) 8 in the capacitor (MIS capacitive element) formation region is accomplished by the same step as the step of forming the N-type impurity layer (N-well region) 8 in a p-channel MISFET formation region (not shown).
- The
capacitor electrode 17 c formed by the same step as the step of forming thegate electrode 17 b of the N-channel type high-voltage MISFET serves as an upper electrode of the capacitor. Whereas, the N-type impurity layer (N-type well region) 8 serves as a lower electrode of the capacitor. The N-type impurity layer (N-type well region) 8 is electrically connected to awiring layer 35 a via an N-type impurity layer 28 a formed by using the step of forming the source/ drain regions of the p-channel MISFET. Thecapacitor electrode 17 c is electrically connected to awiring layer 36 a. - A low-voltage MISFET is mainly composed of the low-voltage
gate insulating film 15 formed as the gate insulating film of the MISFET on the P-type impurity layer (P-type well region) 7 formed in thesemiconductor substrate 1, agate electrode 17 b of the MISFET formed on the low-voltagegate insulating film 15, thesidewall 26 formed on the sidewall of thegate electrode structure 21 composed of thegate electrode 17 b and thesilicon oxide film 18, and N-type impurity layers 24 b and 27 b serving as source/drain regions formed in the P-type impurity layer (P-type well region) 7. The N-type impurity layers 24 b and 27 b are electrically connected to awiring layer 34 b. - The low-
voltage gate electrode 17 b is formed of a conductive film of the same layer as the control gate electrode (memory gate electrode) 17 a of the memory cell. - A capacitor (MIS capacitive element) formed by utilizing the low-voltage MISFET formation step is mainly composed of a
dielectric film 15 a of the capacitor formed by the step of forming the gate insulating film of the low-voltage MISFET on thecapacitor formation trench 4 a formed in the N-type impurity layer (N-type well region) 8 formed in thesemiconductor substrate 1, and thecapacitor electrode 17 c formed by the step of forming thegate electrode 17 b of the low-voltage MISFET. Whereas, theupper electrode structure 22 of the capacitor is formed of thecapacitor electrode 17 c and thesilicon oxide film 18. - The
capacitor formation trench 4 a is formed by using the same step as the step of forming theelement isolation trench 4 for isolation between the semiconductor elements, such as MISFETs. Thedielectric film 15 a of the capacitor is formed on the side and the bottom of thecapacitor formation trench 4 a. Thecapacitor electrode 17 c is formed in such a manner as to fill in thecapacitor formation trench 4 a via thedielectric film 16 a of the capacitor. - The
capacitor electrode 17 c formed by the step of forming thegate electrode 17 b of the low-voltage MISFET constitutes an upper electrode of the capacitor. Whereas, the N-type impurity layer (N-type well region) 8 constitutes a lower electrode of the capacitor. The N-type impurity layer (N-type well region) 8 is electrically connected to awiring layer 35 b via an N-type impurity layer 28 b formed by using the step of forming the source/drain regions of the p-channel MISFET. Thecapacitor electrode 17 c is electrically connected to awiring layer 36 b. - The capacitive elements of the booster circuit, such as a charge pump is circuit, are composed of these capacitors. The capacitance of the capacitor, i.e., the area occupied by the MIS capacitive element, must be increased for the improvement of the capability of the booster circuit. This unfavorably results in an increase in the area occupied by the booster circuit in the chip. Namely, the capacitance value of the capacitor per unit area is required to be increased. In this embodiment, the
capacitor formation trenches 4 a are formed in the surface of thesemiconductor substrate 1 by using the element isolation trench formation step. Then, thecapacitor electrode 17 c of the capacitor (MIS capacitive element) C is formed in such a manner as to be embedded in the inside thereof. As a result, it is possible to enhance the capacitor capacitance per unit area, and, hence, it is possible to increase the MIS capacitance as compared with the case where the capacitor (MIS capacitive element) is formed on the flat surface of thesemiconductor substrate 1, because the area of the capacitor (MIS capacitance), i.e., the sides and the bottoms of thecapacitor formation trenches 4 a, correspond to the MIS capacitance. - Whereas, the capacitor (capacitive element) is formed of a plurality of
capacitor formation trenches 4 a formed in the capacitor formation region, thecapacitor dielectric film 15 a and thecapacitor electrode 17 c, that is formed on the capacitor formation region, including the inside of the plurality of thecapacitor formation trenches 4 a. As a result, it is possible to increase the surface area of the capacitor and to improve the capacitor capacitance per unit area. - Further, the
capacitor formation trenches 4 a are formed to be substantially equal in depth to theelement isolation trench 4. Thecapacitor formation trenches 4 a are formed by using the step of forming theelement isolation trench 4. Namely, thecapacitor formation trenches 4 a are formed in the following manner. At least not less than onecapacitor formation trench 4 a is formed by using the step of forming theelement isolation trench 4 for isolation between the respective semiconductor elements in the region on thesemiconductor substrate 1 including the capacitor formation region. Thesilicon oxide film 5, which is an element isolation insulating film, is then embedded therein. Subsequently, the part of thesilicon oxide film 5 which is an element isolation insulating film of the capacitor formation region is removed. Namely, at least not less than onecapacitor formation trench 4 a is formed by the same formation step as with theelement isolation trench 4. - Whereas, the
dielectric films gate insulating film 15 and the high-voltagegate insulating film 16 of the MISFETs, respectively. Thecapacitor electrode 17 c is formed of the conductive film of the same layer as that of thegate electrode 17 b of the MISFET and thecontrol gate electrode 17 a. Namely, thedielectric films gate insulating film 15 and the high-voltagegate insulating film 16 of the MISFETs, respectively. Thecapacitor electrode 17 c is the conductive film formed by the same formation step used for formation of thegate electrode 17 b of the MISFET and thecontrol gate electrode 17 a. As a result, it is possible to simplify the manufacturing process, and it is possible to improve the capacitor capacitance per unit area. - A description will be given of one example of the charge pump circuit to be used in this embodiment. As shown in
FIG. 55 , a charge pump circuit 100 boosts the input voltage by the externally received input signals φ and/φ and the capacitors C1 to Cn, and it generates a high voltage. The capacitors C1 to Cn are formed of the capacitors formed in the capacitor formation region. The transistors T0 to Tn are formed of, for example, the N-type MISFETs out of the foregoing high-voltage MISFETs, each of which is formed in such a manner that thesource region 27 a and thegate electrode 17 b are short-circuited. Thesource region 27 a of such a transistor T0 is connected to an external voltage Vcc, while thedrain region 27 a is connected to the transistor T1 and the capacitor C1 of the subsequent stage. - Herein, when the external voltage Vcc is applied thereto, the electric charge boosted by the capacitor C1 of the first stage is stored in the capacitor C2 of the subsequent stage through the transistor T1. The electrical charge boosted by the capacitor C2 is stored in the capacitor C3 of the subsequent stage through the transistor T2. Repetition of such boosting provides an internal voltage Vpp from an output terminal. Such an internal voltage Vpp is applied to the
control gate electrode 17 a of the memory cell via a control circuit of the control gate. In this embodiment, the external voltage Vcc is about 1.8 to 3.3 V, and it is possible to boost the internal voltage Vpp up to about 18 V. - A method of manufacture of the semiconductor device of this
embodiment 1 will be described. - First, as shown in
FIG. 4 , asemiconductor substrate 1 that is made of, for example, P-type single crystal silicon is prepared. Then, thesemiconductor substrate 1 is, for example, thermally oxidized, so that asilicon oxide film 2 with a thickness of about 8 to 10 nm is formed on the surface. - Then, as the overlying layer of the
silicon oxide film 2, asilicon nitride film 3 with a thickness of about 130 to 150 nm is deposited as a protective layer by, for example, a CVD (Chemical Vapor Deposition) process. Then, as shown inFIG. 5 , by using a resist pattern as a mask, thesilicon nitride film 3, thesilicon oxide film 2, and thesemiconductor substrate 1 are sequentially dry etched, thereby to formelement isolation trenches 4 in thesemiconductor substrate 1. At this step, at least not less than onecapacitor formation trench 4 a also is formed in the capacitor formation region. Thecapacitor formation trenches 4 a are formed as stripes, as shown inFIG. 6 , in the form of holes, as shown inFIG. 7 , or in a lattice form, as shown inFIG. 8 . Namely, a plurality of thecapacitor formation trenches 4 a are formed in the shape of holes, stripes, or a lattice. - Thus, by forming the
element isolation trenches 4 and thecapacitor formation trenches 4 a by the same step, it is possible to simplify the manufacturing process. Further, by forming at least not less than onecapacitor formation trench 4 a on the surface of the capacitor formation region, it is possible to improve the capacitor capacitance per unit area. The pattern of thecapacitor formation trenches 4 a is not limited to the shape of holes, stripes, or a matrix, but a pattern in any other shape may also be adopted, so that a change may be made thereto, unless it departs from the scope of the present invention. - Then, as shown in
FIG. 9 , on thesemiconductor substrate 1, for example, thesilicon oxide film 5 is deposited as an insulating film by a CVD process. Subsequently, thesilicon oxide film 5 is polished by a chemical mechanical polishing (CMP) process, so that a part of thesilicon oxide film 5 is left and embedded inside theelement isolation trench 4, thereby to form the element isolation region. Thesilicon oxide film 5 is also similarly embedded inside eachcapacitor formation trench 4 a. - Then, the
silicon nitride film 3 is removed by using, for example, a hot phosphoric acid. Subsequently, a P-type impurity, such as boron (B), is ion implanted into the memory cell and the N-channel type MISFET formation region by an ion implantation process, thereby to form the P-type impurity layer (P-type well region) 7. Whereas, an N-type impurity, such as phosphorus (P) or arsenic (As), is ion implanted into the capacitors and a P-channel type MISFET formation region (not shown) by an ion implantation process, thereby to form the N-type impurity layer (N-type well region) 8. - Then, as shown in
FIG. 10 , for example, thesemiconductor substrate 1 is thermally oxidized to form a silicon oxide film with a thickness of about 8 to 12 nm on the surface, thereby to form the memory tunnel insulating film (first memory gate insulating film) 9 of the memory cell. Subsequently, by a CVD process, apolysilicon layer 10 a, which is to be the floating gate electrode (electric charge storage layer) 10 of the memory cell, is deposited on the entire surface of thesemiconductor substrate 1. - Then, as shown in
FIG. 11 , amultilayer film 11 a of a silicon oxide film and a silicon nitride film, serving as the memory gate interlayer film (second memory gate insulating film) of the memory cell, is formed on the entire surface of thepolysilicon layer 10 a. Further, on themultilayer film 11 a, asilicon nitride film 13 is formed as a protective layer, thereby to form a memory gate interlayer film 11 (below, referred to as a NONO film 11) composed of themultilayer film 11 a and thesilicon nitride film 13. TheNONO film 11 is formed by sequentially stacking a silicon oxide film with a thickness of about 2 to 6 nm, a silicon nitride film with a thickness of about 5 to 9 nm, and a silicon oxide film with a thickness of about 3 to 7 nm, and a silicon nitride film with a thickness of about 5 to 15 nm as a protective film by using, for example, a CVD process. - Then, as shown in
FIG. 12 , the entire surface of the memory cell formation region is covered with a resistpattern 121. Thereafter, theNONO film 11, thepolysilicon layer 10 a, and the memorytunnel insulating film 9, that are formed on the entire surface of the MISFET formation region and on the entire surface of the capacitor formation region, are sequentially removed by, for example, dry etching. - Then, as shown in
FIG. 13 , by using, as a mask, a resistpattern 122, which is formed in the plane pattern shown inFIG. 14 , on the entire surface of the memory cell formation region and on the entire surface of the MISFET formation region, thesilicon oxide film 5 embedded in thecapacitor formation trenches 4 a of the capacitor is selectively removed by, for example, dry etching. - Then, the gate insulating film of the MISFETs is formed. Herein, the gate insulating film used for the MISFETs and the capacitor dielectric film used for the capacitors are formed of a dielectric film of the same layer. Namely, the gate insulating film used for the MISFETs and the capacitor dielectric film used for the capacitors are formed by the same step. In this embodiment, as for the example of the case where the high-voltage gate insulating film and the low-voltage insulating film are formed differently in the same manufacturing process, a description will be given for (a) the case where the step of forming the capacitor dielectric film and the step of forming the high-voltage gate insulating film are the same step; and (b) the case where the step of forming the capacitor dielectric film and the step of forming the low-voltage gate insulating film are the same step.
- (a) As shown in
FIG. 15 , for example, thesemiconductor substrate 1 is thermally oxidized, thereby to form asilicon oxide film 14 with a thickness of about 12 to 16 nm, which is to be the high-voltage gate insulating film of the MISFETs and the dielectric film of the capacitors on the MISFET formation region and the capacitor formation region including thecapacitor formation trenches 4 a. - (b) As shown in
FIGS. 16 and 17 , a resistpattern 123 is formed on the entire surface of the memory cell formation region and on the entire surface of the region where the high-voltage gate insulating film is used out of the MISFET formation region and the capacitor formation region. Namely, the resistpattern 123 is formed in such a manner as to expose the entire surface of the region where the low-voltage gate insulating film is used out of the MISFET formation region and the capacitor formation region. - Then, as shown in
FIG. 18 , the portion of thesilicon oxide film 14, which is formed on the region where the low-voltage gate insulating film is used in the MISFETs and the capacitors, is removed by, for example, dry etching. - Then, as shown in
FIG. 19 , after removing the resistpattern 123, for example, thesemiconductor substrate 1 is thermally oxidized. As a result, a silicon oxide film with a thickness of about 4 to 8 nm, which is to serve as the is low-voltage insulating film of the MISFETs and the capacitors, is deposited, thereby to form the low-voltagegate insulating film 15 and thedielectric film 15 a. - Incidentally, as shown in
FIG. 20 , due to the thermal oxidation, the portion of thesilicon oxide film 14 on the region where the high-voltage gate insulating film is used in the MISFETs and the capacitors is oxidized, resulting in formation of the high-voltagegate insulating film 16 and thedielectric film 16 a with a thickness of about 15 to 20 nm. Namely, on the region where the high-voltage gate insulating film is used in the MISFET formation region and the capacitor formation region, the high-voltagegate insulating film 16 is formed. - On the other hand, as shown in
FIG. 19 , in the region where the low-voltage gate insulating film is used in the MISFET formation region and the capacitor formation region, the low-voltagegate insulating film 15 is formed. The silicon oxide film which is to be the low-voltagegate insulating film 15 functions as the low-voltage gate insulating film of the MISFETs and the capacitor dielectric film of the capacitors. - In this
embodiment 1, the subsequent steps will be described mainly based for the case where the capacitor dielectric film is the same film as (a) the high-voltage gate insulating film. However, also in the case where (b) the low-voltage gate insulating film is described, the subsequent manufacturing process will be carried out in accordance with the same procedure. Therefore, a description thereof, except for a part, is omitted. - Then, as shown in
FIG. 21 , on theNONO film 11 formed on the memory cell, and on the low-voltagegate insulating film 15 and the high-voltagegate insulating film 16 formed on the MISFETs and the capacitors, apolysilicon layer 17, which is to be, for example, the control gate electrode (memory gate electrode) 17 a (seeFIG. 2 ) of the memory cell, is formed. Subsequently, on thepolysilicon layer 17, for example, asilicon oxide film 18 is deposited as an insulating film to serve as a cap layer of the memory cell by a CVD process. - Then, as shown in
FIG. 22 , a resistpattern 124 is formed on thesilicon oxide film 18, so that thesilicon oxide film 18, thepolysilicon layer 17, theNONO film 11, and thepolysilicon layer 10 a are dry etched. As a result, the control gate electrode (memory gate electrode) 17 a and the floating gate electrode (electric charge storage layer) 10 of the memory cell, thegate electrode 17 b of each of the high-voltage and low-voltage MISFETs, and thecapacitor electrode 17 a of each capacitor are formed. By the steps up to this point, it is possible to form the memorygate electrode structure 20 composed of the memorytunnel insulating film 9, the floatinggate electrode 10, the memorygate interlayer film 11, thecontrol gate electrode 17 a, and thesilicon oxide film 18. - Incidentally, the control gate electrode (memory gate electrode) 17 a of the memory cell may also be configured in a polycide structure in which a silicide film, such as a cobalt silicide (CoSi) film, is formed on the polysilicon layer.
- Then, as shown in
FIG. 23 , after covering the entire surface of the MISFET formation region and the capacitor formation region with a resist, for example, an N-type impurity, such as arsenic (As), is ion-injected into the memory cell formation region in a self-aligned manner with respect to the memorygate electrode structure 20 by an ion implantation process. As a result, the N-type impurity layers 23 a and 23 b, which are to serve as source/drain regions of the memory cell, are formed. Subsequently, after covering the entire surface of the memory cell formation region and the capacitor formation region with a resist, for example, an N-type impurity, such as phosphorus (P), is ion-injected into the MISFET formation region in a self-aligned manner with respect to thegate electrode portion 21 by an ion implantation process. As a result, the N-type impurity layer 24 a, which is to serve as a source/drain region of the MISFET, is formed. - Whereas, when the gate insulating film of the MISFET is the low-voltage
gate insulating film 15, arsenic (As) ions are injected by an implantation process to form the N-type impurity layer 24 b (seeFIG. 3 ). - Then, as shown in
FIG. 24 , on the main surface, i.e., the entire surface of the memory cell formation region, the MISFET formation region, and the capacitor formation region, asilicon nitride film 25 with a thickness of about 110 to 150 nm is deposited by, for example, a CVD process. Subsequently, after covering the entire surface of the memory cell formation region with a resist, thesilicon nitride film 25 on the MISFET formation region and the capacitor formation region is anisotropically dry etched. As a result, thesidewalls 26 are formed on the sidewalls of the gate electrode of the MISFET and the capacitor electrode. - Then, an N-type impurity, such as arsenic (As), is ion-injected in a self-aligned manner with respect to the
gate electrode portion 21 of the MISFET, the capacitorupper electrode portion 22, and thesidewalls 26. As a result, the N-type impurity layer 27 a, which is to serve as the source/drain regions of the MISFET, and the N-type impurity region 28 a, which is to serve as a diffusion layer of the lower electrode extracting portion of the capacitor, are formed. - Then, on the main surface, i.e., on the entire surface of the memory cell formation region, the MISFET and capacitor formation regions, for example, a silicon oxide film (see
FIGS. 2 and 3 ) is deposited as aninterlayer insulating film 29 by a CVD process. Then, the surface is planarized by a CMP process. - Then, after covering the entire surface of the MISFET formation region and the capacitor formation region with a resist, the
interlayer insulating film 29 is subjected to patterning. As a result, a connecting hole CONT1 (seeFIG. 2 ) reaching the N-type impurity layers 23 a and 23 b of the memory cell formation region is formed in theinterlayer insulating film 29. - Then, as shown in
FIG. 25 , after covering the entire surface of the memory cell formation region with a resist cover, theinterlayer insulating film 29 is subjected to patterning. As a result, a connecting hole CONT2 (seeFIGS. 2 and 3 ) exposing the N-type impurity layers 24 a and 27 a of the MISFET formation region, a connecting hole CONT3 (seeFIGS. 2 and 3 ) reaching the N-type impurity layer 28 a of the lower electrode extracting portion of the capacitor, and a connecting hole CONT4 (seeFIGS. 2 and 3 ) reaching the capacitorupper electrode structure 22 are formed. - Then, on the
interlayer insulating film 29, including the connecting holes CONT1 to CONT4, for example, a TiN film is deposited by using a sputtering process. Subsequently, a W film is deposited on the TiN film by using a CVD process, so that the connecting holes CONT1 to CONT4 are filled with the W film. Then, the W film and the TiN film on theinterlayer insulating film 29 are removed by a CMP process, so that the portions of the W film and the TiN film are left in the connecting holes CONT1 to CONT4. Thus, a plug composed of the W film and the TiN film is formed. - Then, on the
interlayer insulating film 29 and theplug layer 33 a, an interlayer insulating film 32 (seeFIGS. 2 and 3 ) composed of a silicon oxide film is deposited by, for example, a CVD process. Subsequently, after forming alead wire hole 33 b (seeFIGS. 2 and 3 ) to theplug layer 33 a, for example, a W film is embedded in thelead wire hole 33 b by a sputtering process. The W film is etched back, thereby to form the wiring layer 33 (seeFIG. 2 ) for ensuring an electrical connection to the N-type impurity layers 23 a and 24 b formed in the capacitor, awiring layer 34 a (seeFIG. 2 ) for ensuring an electrical connection to the N-type impurity layers 24 a and 27 a formed in the high-voltage MISFET, awiring layer 34 b (seeFIG. 3 ) for ensuring an electrical connection to the N-type impurity layers 24 b and 27 b formed in the low-voltage MISFET, awiring layer 35 a (seeFIG. 2 ) and awiring layer 35 b (seeFIG. 3 ) for ensuring an electrical connection to the N-type impurity layers 28 a and 28 b formed in the capacitors, respectively, and thewiring layer 36 a (seeFIG. 2 ) and thewiring layer 36 b (seeFIG. 3 ) for ensuring an electrical connection to each capacitorupper electrode 17 c. - It is possible to form the configuration shown in
FIG. 2 based on the foregoing embodiment. Whereas, the diagram for the case where the low-voltage gate insulating films are used as the gate insulating film of the MISFET and the capacitor dielectric film of the capacitor is as shown inFIG. 3 . - In accordance with such an
embodiment 1, it is possible to form theelement isolation trench 4 and thecapacitor formation trenches 4 a by the same step. Further, it is possible to form the high-voltagegate insulating film 16 or the low-voltagegate insulating film 15 of the MISFET by the same step as the step of forming thedielectric film 16 a or thedielectric film 15 a of the capacitor. Namely, the high-voltagegate insulating film 16 or the low-voltagegate insulating film 15 and the insulating film used for forming thedielectric film 16 a or thedielectric film 15 a of the capacitor are formed by the same step. Whereas, it is possible to form thegate electrode 17 b of the MISFET and thecapacitor electrode 17 c by the same step. Namely, thegate electrode 17 b of the MISFET and the conductive film used for forming thecapacitor electrode 17 c are formed by the same step. This can simplify the manufacturing process of the semiconductor device of thisembodiment 1. - The configuration of the essential parts of a semiconductor device of
embodiment 2 of the present invention is shown inFIG. 25 . - In the foregoing
embodiment 1, as shown inFIG. 9 , in the step of removing thesilicon oxide film 5 that is embedded in thecapacitor formation trenches 4 a, the mask as shown inFIG. 14 was used as a resist pattern. However, in thisembodiment 2, a part of theelement isolation trench 4 may also be used as a part of the capacitor formation region by performing patterning by using the mask shown inFIGS. 27 and 28 . - Incidentally, for convenience in the description, a description of the same part in the following process as was used in the foregoing
embodiment 1 will be omitted. - First, after the step shown in
FIG. 12 in the foregoingembodiment 1, a is resistpattern 125, as shown inFIGS. 27 and 28 , is formed on thesilicon oxide film 5, that is embedded in the element isolation trench 4 (seeFIG. 12 ), and in at least not less than onecapacitor formation trench 4 a. Then, dry etching is performed by using the resistpattern 125 as a mask, thereby to remove the portions of thesilicon oxide film 5 embedded in thecapacitor formation trench 4 a and a part of theelement isolation trench 4. - Then, the gate insulating film (the low-voltage
gate insulating film 15 or the high-voltage gate insulating film 16) of the MISFET is formed in the same manner as with the steps shown inFIG. 15 and subsequent figures of the foregoingembodiment 1. - The subsequent steps are the same as in the foregoing
embodiment 1, and hence a description thereof will be omitted. - Thus, in this
embodiment 2, by utilizing a part of theelement isolation trench 4 as a part of the capacitor formation region, without adding another manufacturing step, it is possible to increase the capacitance per unit area of the capacitor. - Whereas, this
embodiment 2 has been described based on the foregoingembodiment 1, but it can also be carried out in a similar manner based on the subsequent embodiments. - The configuration of the essential parts of a semiconductor device of
embodiment 3 of the present invention is shown inFIG. 29 . - In the foregoing
embodiment 1, the step of forming the gate insulating films (the low-voltagegate insulating film 15 and the high-voltage gate insulating film 16) of the MISFETs was the same step as the step of forming thedielectric film embodiment 3, theNONO film 11, which is the memory gate interlayer film (second memory gate insulating film) of the memory cell and the capacitor dielectric film of the capacitor, are formed of the dielectric film of the same layer. Namely, the step of forming theNONO film 11, which is the memory gate interlayer film (second memory gate insulating film) of the memory cell, and the step of forming the capacitor dielectric film of the capacitor are set to be the same. - Incidentally, for convenience in the description, a description of the same part in the following process as was used in the foregoing
embodiment 1 will be omitted. As for the MISFETs, the gate insulating film is formed so as to be divided into the high-voltage and low-voltage films, as withEmbodiment 1. However, a description will be mainly given of the high-voltage one. - After the step of forming the
polysilicon layer 10 a, which is to serve as the floating gate electrode (electrode electric charge storage layer) of the memory cell shown inFIG. 10 in the foregoingembodiment 1, the entire surface of the memory cell and MISFET formation regions is covered with a resist, with thepolysilicon layer 10 a being formed. Thereafter, the portion of thepolysilicon layer 10 a formed on the capacitor formation region is removed by dry etching. - Then, as shown in
FIG. 30 , the entire surface of the memory cell formation region and the MISFET formation region and the region, except for thecapacitor formation trenches 4 a, of the capacitor formation region are covered with a resistpattern 126. Thereafter, the memorytunnel insulating film 9 in the capacitor formation region and the portions of thesilicon oxide film 5 embedded in thecapacitor formation trenches 4 a are sequentially removed by dry etching. - Then, as shown in
FIG. 31 , on the entire surface of the memory cell formation region, and the entire surface of the MISFET formation region, and the capacitor formation region, theNONO film 11, which is to serve as the gate interlayer film of the memory cell, is formed by the same step as inEmbodiment 1. Namely, the insulating film that is used for the formation of the memorygate interlayer film 11 and the dielectric film of the capacitor are formed by the same step. - Then, as shown in
FIG. 32 , the entire surface of the memory cell and capacitor formation region is covered with a resist 127. Thereafter, theNONO film 11, thepolysilicon layer 10 a, and the memorytunnel insulating film 9 formed on the MISFET formation region are removed by dry etching. Whereas, as shown inFIG. 33 , they are also removed similarly in the region for forming the low-voltagegate insulating film 15. - Subsequently, the high-voltage
gate insulating film 16 and the low-voltage insulating film 15 are formed in the MISFET formation regions. As for the processes for forming the high-voltagegate insulating film 16 and the low-voltage insulating film 15, different processes are respectively adopted for (a) the high-voltage gate insulating film and (b) the low-voltage gate insulating film, as with the foregoingembodiment 1. The manufacturing processes thereof are respectively the same as inEmbodiment 1, and hence a description thereof will be omitted (seeFIGS. 34 and 35 ). - Then, as shown in
FIG. 36 , on theNONO film 11 that is formed on the memory cell and capacitor formation regions and the gate insulating film that is formed on the MISFET formation region, the polysilicon film, which is to serve as the control gate electrode (memory gate electrode) 17 a of the memory cell, and thesilicon oxide film 18, which is to serve as a cap layer, are sequentially deposited by a CVD process. - Then, a resist
pattern 128 is formed. The memorygate electrode structure 20, thegate electrode structure 21 of the MISFET, and the capacitorupper electrode structure 22 are formed by dry etching using the resistpattern 128. Namely, the conductive film that is used for the formation of the memorygate electrode structure 20, thegate electrode structure 21 of the MISFET, and the capacitorupper electrode structure 22 is formed by the same step. - Below, it is possible to form the semiconductor device having the nonvolatile memory shown in
FIG. 29 through the same manufacturing process as was used in the foregoingembodiment 1, and hence a description thereof will be omitted. - Thus, by forming the capacitor dielectric film of the capacitor and the memory gate interlayer film of the memory cell by the same step, it is possible to simplify the manufacturing process. Further, by using the
NONO film 11 in place of the low-voltagegate insulating film 15 or the high-voltagegate insulating film 16 of the MISFET as the capacitor dielectric film of the capacitor, it is possible to implement a high reliability capacitor dielectric film. - The configuration of the main parts of a semiconductor device of
embodiment 4 of the present invention is shown inFIG. 37 . - In the foregoing
embodiment 1, as shown in the steps of forming the memory cell of FIGS. 10 to 22, thepolysilicon layer 10 a is formed as the electric charge storage layer of the memory cell. However, asilicon nitride film 41 is used to form the electric charge storage layer. Incidentally, thesilicon nitride film 41 stores electric charges by capturing electrons in the trap of thesilicon nitride film 41. - For convenience in description, a description of the same part in the following process as was used in the foregoing
embodiment 1 will be omitted. - After the step shown in
FIG. 10 in the foregoingembodiment 1, as shown inFIG. 38 , on the memorytunnel insulating film 9, thesilicon nitride film 41 and asilicon oxide film 42 are sequentially deposited by using, for example, a CVD process. Thesilicon nitride film 41 has a function of storing electric charges as a substitute for the floating gate electrode of the memory cell. - Then, as shown in
FIG. 39 , the entire surface of the memory cell formation region is covered with a resistpattern 129. Then, the portions of thesilicon oxide film 42, thesilicon nitride film 41 and the memorytunnel insulating film 9 that are formed on the MISFET formation region and the capacitor formation region are sequentially removed by etching. Subsequently, the resistpattern 122 shown inFIG. 14 in the foregoingembodiment 1 is formed, and the portions of thesilicon oxide film 5 embedded in thecapacitor formation trenches 4 a are removed. - Subsequently, as shown in
FIG. 40 , the gate insulating films (the low-voltagegate insulating film 15 and the high-voltage gate insulating film 16) of the MISFETs and thedielectric film 16 a are formed on the MISFET formation regions and the capacitor formation region, respectively, by the same step as in the foregoingembodiment 1. - Then, as shown in
FIG. 41 , on thesilicon oxide film 42 formed on the memory cell formation region, and on the low-voltagegate insulating film 15 or the high-voltagegate insulating film 16 formed on the MISFET formation region and the capacitor formation region, apolysilicon film 44 and asilicon oxide film 45 are sequentially deposited by using a CVD process. - Then, as shown in
FIG. 42 , patterning is performed by using a resistpattern 130 as a mask, thereby to form amemory gate electrode 44 a, a gate electrode 44 b of the MISFET, and anupper electrode 44 c of the capacitor. Namely, thememory gate electrode 44 a, the gate electrode 44 b of the MISFET, and theupper electrode 44 c of the capacitor are composed of a conductive film of the same layer, and the conductive film used for the formation of thememory gate electrode 44 a, the gate electrode 44 b of the MISFET, and theupper electrode 44 c of the capacitor is formed by the same step. In accordance with the steps up to this point, it is possible to form a memorygate electrode structure 40 that is composed of the memorytunnel insulating film 9, thesilicon nitride film 41, thesilicon oxide film 42, thememory gate electrode 44 a, and thesilicon oxide film 45. - In the subsequent steps, the semiconductor device having the nonvolatile memory shown in
FIG. 37 is formed through the same steps as used in the foregoingembodiment 1, and hence a description thereof will be omitted. - Thus, in this
embodiment 4, the electric charge storage layer of the memory cell is formed by using thesilicon nitride film 41 in place of thepolysilicon layer 10 a in the foregoingembodiment 1. However, as compared with the case where thepolysilicon film 10 a, which is a continuous conductive film, performs electric charge storage, the electron traps in thesilicon nitride film 41 are discontinuous and discrete. Therefore, even when a charge leakage path, such as a pinhole, occurs in a part of the memorytunnel insulating film 9, all of the stored electric charges will not disappear. As a result, it is possible to establish inherently strong retention characteristics. - Whereas, the electric charge storage layer of the memory cell may also be formed of so-called Si nano-dots composed of silicon spheres each having a diameter of several nanometers in place of the
silicon nitride film 41. Also, in such a case, it is possible to obtain the foregoing same effects as obtained in thisembodiment 4. - The configuration of the main parts of a semiconductor device of
embodiment 5 of the present invention is shown inFIG. 43 . - In the foregoing
embodiment 4, as a modified example of the foregoingembodiment 1, the memorygate electrode structure 40 was formed in place of the memorygate electrode structure 20. However, in thisembodiment 5, the gate electrode structure is formed in a so-called split-gate type as a memorygate electrode structure 50, as shown inFIG. 43 . - Incidentally, for convenience in the description, a description of the same part in the following process as was used in the foregoing
embodiment 1 will be omitted. - After the step shown in
FIG. 10 in the foregoingembodiment 1, as shown inFIG. 44 , on the memorytunnel insulating film 9, apolysilicon film 51 and asilicon oxide film 52 are sequentially deposited by, for example, a CVD process. Incidentally, thesilicon oxide film 52 may also be formed by thermally oxidizing the surface of thepolysilicon film 51. - Then, as shown in
FIG. 45 , a resistpattern 131 is formed on thesilicon oxide film 52 of the memory cell formation region. Thereafter, thesilicon oxide film 52, thepolysilicon film 51, and the memorytunnel insulating film 9 are sequentially patterned, and selectively removed. The electric charge storage layer of the memory cell is formed of thepolysilicon film 51. - Then, as shown in
FIG. 46 , a resistpattern 132 is formed by using the same mask as the mask shown inFIG. 14 in the foregoingembodiment 1. Thus, thesilicon oxide film 5 formed in thecapacitor formation trenches 4 a of the capacitor is selectively removed. - Then, as shown in
FIG. 47 , a silicon oxide film, which is to serve as agate insulating film 53 of the MISFET, is formed by using, for example, a CVD process. Whereas, the silicon oxide film to be thegate insulating film 53 of the MISFET may also be formed into different films by the same steps as the steps of forming the high-voltage gate insulating film 16 (seeFIG. 2 ) and the low-voltage gate insulating film 15 (seeFIG. 3 ) in the foregoingembodiment 1. - Then, as shown in
FIG. 48 , on thegate insulating film 53, apolysilicon film 54 and asilicon oxide film 55 are sequentially deposited by using, for example, a CVD process. - Then, as shown in
FIG. 49 , a resistpattern 133 is formed. Thus, thesilicon oxide film 55 and thepolysilicon film 54 are selectively removed by patterning. As a result, it is possible to form amemory gate electrode 54 a, agate electrode 54 b of the MISFET, and anupper electrode 54 c of the capacitor. In accordance with the steps up to this point, it is possible to form is a memorygate electrode structure 50 that is composed of the memorytunnel insulating film 9, thepolysilicon film 51, thesilicon oxide film 52, thegate insulating film 53, thememory gate electrode 54 a, and thesilicon oxide film 55. - In the subsequent steps, it is possible to form the semiconductor device having the nonvolatile memory shown in
FIG. 43 through the same manufacturing steps as used in the foregoingembodiment 1, and hence a description thereof will be omitted. - Thus, also when the memory gate electrode portion is formed in the configuration as shown in this
embodiment 5, it is possible to obtain the same effects as obtained in the foregoingembodiment 1. - The configuration of the main parts of a semiconductor device of embodiment 6 of the present invention is shown in
FIG. 50 . - In the foregoing
embodiment 1, the gate electrode of the MISFET and the upper electrode of the capacitor were formed of the polysilicon layer 17 (seeFIG. 21 ) serving as thecontrol gate electrode 17 a (seeFIG. 2 ) of the memory cell. However, in this embodiment 6, these electrodes are formed by using thepolysilicon layer 10 a serving as the floating gate electrode 10 (seeFIG. 2 ) of the memory cell and thepolysilicon layer 17 serving as thecontrol gate electrode 17 a. - Incidentally, for convenience in the description, a description of the same part in the following process as was used in the foregoing
embodiment 1 will be omitted. - After the step shown in
FIG. 9 in the foregoingembodiment 1, as shown inFIG. 51 , the region except for thecapacitor formation trenches 4 a is covered with a resistpattern 134. Thus, thesilicon oxide film 5 embedded in thecapacitor formation trenches 4 a is etched and removed. - Then, as shown in
FIG. 52 , for example, thesemiconductor substrate 1 is thermally oxidized, thereby to form agate insulating film 60 on the MISFET formation region, and, simultaneously, to also form thegate insulating film 60 on thecapacitor formation trenches 4 a. Herein, thegate insulating film 60 may also be formed into different films by the same steps as the steps of forming the high-voltage gate insulating film 16 (seeFIG. 2 ) and the low-voltage gate insulating film 15 (seeFIG. 3 ) in the foregoingembodiment 1. Further, at this step, the same oxide film as thegate insulating film 60 is also formed on the memory cell formation region. - Then, the entire surface of the MISFET formation region and the capacitor formation region is covered with a resist. Thereafter, the portion of the oxide film on the surface of the memory cell formation region is etched and removed. Subsequently, the
semiconductor substrate 1 is thermally oxidized, thereby to form asilicon oxide film 61, which is to serve as the memory tunnel insulating film on the memory cell formation region. - Then, as shown in
FIG. 53 , on the entire surface of thesemiconductor substrate 1, apolysilicon film 63, which is to serve as a floating gate electrode (electric charge storage layer) of the memory cell, is deposited by using a CVD process. Then, aNONO film 64, which is to serve as a memory gate interlayer film, is formed on thepolysilicon film 63. - Then, as shown in
FIG. 54 , a part of theNONO film 64 that is formed on the MISFET formation region and the capacitor formation region is selectively removed. Thereafter, on the exposedpolysilicon film 63 andNONO film 64, apolysilicon film 65, which is to serve as a control gate electrode (memory gate electrode) of the memory cell, and asilicon oxide film 66, which is to serve as a cap layer, are sequentially deposited by using a CVD process. This allows the establishment of continuity between thepolysilicon film 63 and thepolysilicon film 65 that are formed on the MISFET formation region and the capacitor formation region. Subsequently, by dry etching using a resist pattern, thesilicon oxide film 66, thepolysilicon film 65, theNONO film 64, thepolysilicon film 63, and thesilicon oxide film 61 are patterned and, thereby, selectively removed. As a result, it is possible to formmemory gate electrodes gate electrodes upper electrode FIG. 50 . - In the subsequent steps, it is possible to form the semiconductor device having the nonvolatile memory of this embodiment 6, as shown in
FIG. 50 , through the same steps as used in the foregoingembodiment 1, and, hence, a description thereof will be omitted. - As described above, the floating gate electrode and the memory gate electrode of the memory cell are formed by the same step for the gate electrode of the MISFET and the capacitor upper electrode. Namely, the floating gate electrode and the memory gate electrode of the memory cell, the gate electrode of the MISFET, and the capacitor upper electrode are composed of a conductive film of the same layer. The conductive film used for the formation of the floating gate electrode and the memory gate electrode of the memory cell, the gate electrode of the MISFET, and the capacitor upper electrode is formed by the same step. By performing the formation thereof in this manner, it is possible to simplify the manufacturing process.
- Thus, instead of forming the gate electrode of the MISFET and the capacitor upper electrode only from the polysilicon film which is to serve as the control gate electrode of the memory cell, when both the polysilicon film, which is to serve as the floating gate electrode of the memory cell, and the polysilicon film, which is to serve as the control gate electrode, are used, it is possible to obtain the same effects as obtained in the foregoing
embodiments 1 to 5. - Up to this point, the present invention has been described specifically by way of various embodiments of the invention, which should not be construed as limiting the scope of the present invention. It is needless to say that various changes and modifications may be made without departing the scope of the invention. For example, each of the foregoing
embodiments 1 to 6 may also be combined with one or a plurality of the other embodiments. - The effects obtainable in accordance with typical aspects of the present invention as disclosed in this application will be briefly described as follows.
- A capacitor (capacitive element) is formed of a plurality of capacitor formation trenches that are formed in a capacitor formation region, a capacitor dielectric film formed on the capacitor formation region, including the inside of the plurality of the capacitor formation trenches, and capacitor electrodes.
- As a result, it is possible to increase the surface area of the capacitor, and thereby to improve the capacitor capacitance per unit area.
- On a semiconductor substrate, an element isolation trench and the capacitor formation trenches formed in the capacitor are formed by the same step. As a result, it is possible to simplify the manufacturing process of the semiconductor device.
- Whereas, the gate insulating film of the MISFET and the dielectric film of the capacitor on the capacitor formation trenches are formed by the same step. As a result, it is possible to simplify the manufacturing process of the semiconductor device.
- Further, the capacitor dielectric film in the capacitor formation region, and a memory gate interlayer film of a memory cell are formed by the same step. As a result, it is possible to simplify the manufacturing process of the semiconductor device.
- Still further, the dielectric film of the capacitor is formed by using the memory gate interlayer film (NONO film) of the memory cell in place of using a gate insulating film of a MISFET. As a result, it is possible to form a high reliability capacitor dielectric film.
Claims (30)
1. A semiconductor device comprising:
semiconductor elements formed in a first well;
element isolation trenches each for isolation between the semiconductor elements;
capacitor formation trenches formed in a second well, and the depth of the capacitor formation trenches is equal to the depth of the element isolation trenches; and
capacitor electrodes each formed inside the capacitor formation trenches via a capacitor dielectric film.
2. A semiconductor device according to claim 1 , wherein the capacitor formation trenches are formed in the shape of holes, stripes, or a matrix.
3. A semiconductor device according to claim 1 , wherein an insulating film is buried in the element isolation trenches.
4. A semiconductor device comprising:
semiconductor elements each having a gate insulating film;
element isolation trenches for isolation between the semiconductor elements;
capacitor formation trenches; and
a capacitor dielectric film formed in the capacitor formation trenches,
wherein the semiconductor elements are formed in a first well,
wherein the capacitor formation trenches are formed in a second well,
wherein the depth of the capacitor formation trenches is equal to the depth of the element isolation trenches, and
wherein the capacitor dielectric film and the gate insulating film are formed of a same layer.
5. A semiconductor device according to claim 4 , wherein the capacitor formation trenches are formed in the shape of holes, stripes, or a matrix.
6. A semiconductor device according to claim 4 ,
wherein the semiconductor elements include a first MISFET for high voltage and a second MISFET for low voltage,
wherein the thickness of the gate insulating film of the first MISFET is larger than the thickness of the gate insulating film of the second MISFET, and
wherein the capacitor dielectric film is formed of a same layer as that of the gate insulating film of the first MISFET.
7. A semiconductor device according to claim 4 , wherein the capacitor dielectric film and the gate insulating film include a silicon oxide film.
8. A semiconductor device according to claim 4 , wherein an insulating film in buried in the element isolation trenches.
9. A semiconductor device comprising:
semiconductor elements each having a gate electrode;
element isolation trenches each for isolation between the semiconductor elements;
capacitor formation trenches; and
capacitor electrodes formed in the capacitor formation trenches,
wherein the semiconductor elements are formed in a first well,
wherein the capacitor formation trenches are formed in a second well,
wherein the depth of the capacitor formation trenches is equal to the depth of the element isolation trenches, and
wherein the capacitor electrodes and the gate electrodes are formed of a same layer.
10. A semiconductor device according to claim 9 , wherein the capacitor formation trenches are formed in the shape of holes, stripes, or a matrix.
11. A semiconductor device according to claim 9 ,
wherein the semiconductor elements include a first MISFET for high voltage and a second MISFET for low voltage, and
wherein the capacitor electrodes are formed of a same layer as that of the gate electrode of the first MISFET.
12. A semiconductor device according to claim 9 , wherein the capacitor electrodes and the gate electrodes include a poly-silicon film.
13. A semiconductor device according to the claim 9 , wherein an insulating film is buried in the element isolation trenches.
14. A semiconductor device comprising:
semiconductor elements formed in a first well;
memory cells formed in a third well;
capacitor elements formed in a second well; and
element isolation trenches each for isolation between the semiconductor elements,
wherein each semiconductor element has a first insulating film and a first conductive film formed over the first insulating film,
wherein each memory cell has an electric charge storage layer, a second insulating film formed over the electric charge storage layer and a second conductive film formed over the second insulating film,
wherein each capacitor element has capacitor formation trenches, the first insulating film formed in the capacitor formation trenches and the first conductive film formed over the first insulating film, and
wherein the depth of the capacitor formation trenches is equal to the depth of the element isolation trenches.
15. A semiconductor device according to claim 14 , wherein the capacitor formation trenches are formed in the shape of holes, stripes, or a matrix.
16. A semiconductor device according to claim 14 ,
wherein the semiconductor elements include a first MISFET for high voltage and a second MISFET for low voltage, the first MISFET including the first insulating film, and
wherein the first insulating film of the capacitor element is formed of the same film as the first insulating film of the first MISFET.
17. A semiconductor device according to claim 14 ,
wherein the semiconductor elements and the capacitor elements constitute a charge pump circuit, and
wherein the charge pump circuit is electrically connected to the second conductive film of the memory cell.
18. A semiconductor device according to claim 14 , wherein an insulating film is buried in the element isolation trenches.
19. A semiconductor device comprising:
memory cells formed in a third well;
capacitor elements formed in a second well; and
element isolation trenches each for isolation between the memory cells,
wherein each memory cell has an electric charge storage layer, a second insulating film formed over the electric charge storage layer and a second conductive film formed over the second insulating film,
wherein each capacitor element has capacitor formation trenches and the second insulating film formed in the capacitor formation trenches, and
wherein the depth of the capacitor formation trenches is equal to the depth of the element isolation trenches.
20. A semiconductor device according to claim 19 , wherein the capacitor formation trenches are formed in the shape of holes, stripes, or a matrix.
21. A semiconductor device according to claim 19 , wherein each capacitor element further has the second conductive film formed over the second insulating film in the capacitor formation trench.
22. A semiconductor device according to claim 19 , wherein the electric charge storage layer includes a silicon nitride film or a Si nano-dot.
23. A semiconductor device according to claim 19 , wherein the electric charge storage layer is formed of a poly-silicon film.
24. The semiconductor device according to claim 19 , wherein the second insulating film includes a silicon oxide film and a silicon nitride film.
25. A semiconductor device according to claim 19 , wherein an insulating film is buried in the element isolation trenches.
26. A semiconductor device comprising:
memory cells formed in a third well;
capacitor elements formed in a second well; and
element isolation trenches each for isolation between the memory cells,
wherein each memory cell has an electric charge storage layer and a second conductive film formed over the electric charge storage layer,
wherein each capacitor element has capacitor formation trenches, and the electric charge storage layer formed in the capacitor formation trenches, and
wherein the depth of the capacitor formation trenches is equal to the depth of the element isolation trenches.
27. A semiconductor device according to claim 26 , wherein the capacitor formation trenches are formed in the shape of holes, stripes, or a matrix.
28. A semiconductor device according to claim 26 , wherein each capacitor element further has the second conductive film formed over the second insulating film in the capacitor formation trench.
29. A semiconductor device according to claim 26 , wherein the charge storage layer includes a silicon nitride film.
30. A semiconductor device according to claim 26 , wherein an insulating film is buried in the element isolation trenches.
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US10/408,353 US7015090B2 (en) | 2002-04-17 | 2003-04-08 | Method of manufacturing a semiconductor device having trenches for isolation and capacitor formation trenches |
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Publication number | Priority date | Publication date | Assignee | Title |
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Also Published As
Publication number | Publication date |
---|---|
TW200403853A (en) | 2004-03-01 |
KR20030082474A (en) | 2003-10-22 |
US7015090B2 (en) | 2006-03-21 |
US20040038492A1 (en) | 2004-02-26 |
CN1622311A (en) | 2005-06-01 |
TWI284985B (en) | 2007-08-01 |
JP2003309182A (en) | 2003-10-31 |
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