US20050189718A1 - Target control system - Google Patents
Target control system Download PDFInfo
- Publication number
- US20050189718A1 US20050189718A1 US10/789,767 US78976704A US2005189718A1 US 20050189718 A1 US20050189718 A1 US 20050189718A1 US 78976704 A US78976704 A US 78976704A US 2005189718 A1 US2005189718 A1 US 2005189718A1
- Authority
- US
- United States
- Prior art keywords
- counter
- count
- presentation
- target
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F41—WEAPONS
- F41J—TARGETS; TARGET RANGES; BULLET CATCHERS
- F41J7/00—Movable targets which are stationary when fired at
- F41J7/06—Bobbing targets, i.e. targets intermittently or unexpectedly appearing
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Electronic Switches (AREA)
Abstract
A target controller includes a first counter configured to count at a first rate and a second counter configured to count at a second rate. The first and second counters cooperate to determine a delay between receipt of a start signal and target presentation. A third counter determines a target presentation duration, and a fourth counter determines a target presentation count.
Description
- The present disclosure relates to devices to control the presentation timing and presentation count for target practice.
- Increasing one's skill at shooting a handgun requires practice. Professional shooting courses provide access to sophisticated rotating target practice systems. Some of these systems are manually controlled by the trainer; others provide computerized controls. To simulate real-world shooting situations, decrease reaction time, and in general improve shooting skills, the instructor will operate and/or configure the target practice system to provide a variety of target presentation times and target presentation counts to the shooter.
- Challenges arise once the shooter has completed the course. The shooter should continue to practice in order to maintain and/or improve shooting skills. Often the most convenient and/or practical places to practice are locations without access to utility-generated power. These locations are often located outdoors, in environmentally rugged conditions (high humidity, dirt and dust, precipitation, rough terrain, etc.). The shooter often practices alone. Portability, simplicity of operation, and durability thus become important considerations in providing a target control system that is to be transported, set up, and operated by a single shooter.
- Experience teaches that practice value may increase when the shooter cannot anticipate the target's action. Target presentation time, delay, and count should thus be made unpredictable to some extent. The target control system should have the capability to expand beyond control of a single target, and should be cost-effective for individuals.
- Target control system are available from a number of providers, including Target Timers, Porta Target, Action Target, Beacon Target, STS Targets, Caswell, and Speedwell. However, a need remains for a target control system for individual shooters that is rugged, portable, simple to set up and operate, expandable, and that provides unpredictable target delay times, presentation times, and presentation counts.
- The following summary is intended to highlight and introduce some aspects of the disclosed embodiments, but not to limit the scope of the invention. Thereafter, a detailed description of illustrated embodiments is presented, which will permit one skilled in the relevant art to make and use aspects of the invention. One skilled in the relevant art can obtain a full appreciation of aspects of the invention from the subsequent detailed description, read together with the figures, and from the claims (which follow the detailed description).
- A target controller includes a first counter configured to count at a first rate and a second counter configured to count at a second rate. The first and second counters cooperate to determine a delay between receipt of a start signal and target presentation. A third counter determines a target presentation duration, and a fourth counter determines a target presentation count.
- The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.
- In the drawings, the same reference numbers and acronyms identify elements or acts with the same or similar functionality for ease of understanding and convenience. To easily identify the discussion of any particular element or act, the most significant digit or digits in a reference number refer to the figure number in which that element is first introduced.
-
FIG. 1 is an illustration of an embodiment of a target control system. -
FIG. 2 is a high-level block diagram of an embodiment of a target control circuit. -
FIG. 3 is a low-level block diagram of an embodiment of a target control circuit. -
FIG. 4 is a block diagram of an embodiment of variable delay generator logic. -
FIG. 5 is a block diagram of an embodiment of output pulse control logic. -
FIG. 6 is a block diagram of an embodiment of duration control logic. -
FIG. 7 is a block diagram of an embodiment of count control logic. -
FIG. 8 is a block diagram of an embodiment of start/repeat logic. -
FIG. 9 is a flow chart of an embodiment of a process to provide a variable delay before target presentation. -
FIG. 10 is a flow chart of an embodiment of a process of providing a selection of pre-selected or unpredictable target presentation time. -
FIG. 11 is a flow chart of an embodiment of a process of providing a selection of pre-selected or unpredictable target presentation count. -
FIGS. 12-15 are timing diagrams of an embodiment of signals involved in providing a target presentation delay and target presentation time. -
FIG. 16 is a timing diagram of an embodiment of signals involved in providing a target presentation count. - The invention will now be described with respect to various embodiments. The following description provides specific details for a thorough understanding of, and enabling description for, these embodiments of the invention. However, one skilled in the art will understand that the invention may be practiced without these details. In other instances, well known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the invention. References to “one embodiment” or “an embodiment” do not necessarily refer to the same embodiment, although they may.
- Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” Words using the singular or plural number also include the plural or singular number respectively. Additionally, the words “herein,” “above,” “below” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. When the claims use the word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list and any combination of the items in the list.
- Herein, “logic” refers to any information having the form of instruction signals and/or data that may be applied to affect the operation of a processing device. Examples of processing devices are computer processors (processing units), microprocessors, digital signal processors, controllers and microcontrollers, and so on. Logic may be formed from signals stored in a device memory. Software is one example of such logic. Examples of device memories that may comprise logic include RAM (random access memory), flash memories, ROMS (read-only memories), EPROMS (erasable programmable read-only memories), and EEPROMS. Logic may also be comprised by digital and/or analog hardware circuits, for example, hardware circuits comprising counters, flip-flops, switches, delays, logical AND, OR, XOR, NAND, NOR, and other logical operations. Logic may be formed from combinations of software and hardware.
-
FIG. 1 is an illustration of an embodiment of a target control system. Thetarget control system 100 comprises apresentation count control 102, apresentation time control 104, and astart button 106. Thepresentation count control 102 has a “random”setting 108 to cause an unpredictable number of target presentations. Thepresentation time control 104 has a “random” setting 110 to cause unpredictable target presentation time. -
FIG. 2 is a high-level block diagram of an embodiment of a target control circuit. Variabledelay generator logic 202 is coupled to outputpulse control logic 204. The variabledelay generator logic 202 generates a signal after an unpredictable time interval has elapsed after the shooter activates thestart button 106, or after a previous target presentation is complete. The outputpulse control logic 204 provides a signal to cause the presentation of the target to the shooter. The outputpulse control logic 204 is coupled toduration control logic 206 and countcontrol logic 208. Theduration control logic 206 determines the time interval that the target is presented to the shooter. This time interval may be an interval determined by the setting of thepresentation time control 104, or an unpredictable time interval when the presentation control is set to the random setting 110. Thecount control logic 208 determines the number of times that the target is presented to the shooter. This count may be a number determined by the setting of thepresentation count control 102, or may be an unpredictable number when thepresentation count control 102 is set to therandom setting 108. Theduration control logic 206 is coupled to the outputpulse control logic 204 and to start/repeat logic 210. The start/repeat logic 210 creates signals to start the target presentation after the shooter presses thestart button 106, and to repeat target presentation if the control settings so determine. Thecount control logic 208 is coupled to the start/repeat logic 210, and the start/repeat logic 210 is coupled to outputpulse control logic 204. -
FIG. 3 is a low-level block diagram of an embodiment of a target control circuit. Functional blocks within this overall circuit are described in conjunction withFIGS. 4-8 . Aclock 302 is coupled to acounter 304 and aclock divider 306. Thecounter 304 is coupled to anothercounter 308. Thecounter 304 is utilized to provide unpredictable presentation time and count behavior, in a manner more fully described in conjunction withFIGS. 4-8 . Thecounter 304 is coupled to switch 322 andswitch 330. Theclock divider 306 is coupled to thecounter 308 and to acounter 320. Adelay 310 is coupled to thecounter 308 and to a flip-flop (FF) 314. Theclock 302, counters 304, 308,divider 306, and delay 310 comprise an embodiment of variabledelay generator logic 202 and are more fully described in conjunction withFIG. 4 . - The
counter 308 is coupled to a norgate 312. The norgate 312 is coupled to aFF 318. TheFF 314 is coupled to the norgate 312 and acounter 320. A norgate 316 is coupled to theFF 318. TheFF 318 is coupled to thecounter 320, theFF 314, and acounter 328. The norgates FFs pulse control logic 204 and are more fully described in conjunction withFIG. 5 . - The
counter 320 is coupled to the norgate 316 and a norgate 336. Aswitch 322 is coupled to thecounter 320. Acoder 324 is coupled to theswitch 322, and an analog switch 326 (such as the presentation time control 104) is coupled to thecoder 324. Thecounter 320,coder 324,switch 322, andanalog switch 326 comprise an embodiment ofduration control logic 206 that is more fully described in conjunction withFIG. 6 . - A
counter 328 is coupled to the norgate 336. Aswitch 330 is coupled to thecounter 328. Acoder 332 is coupled to theswitch 330, and ananalog switch 334 is coupled to thecoder 332. Thecounter 328,switch 330,coder 332, andanalog switch 334 comprise an embodiment of presentationcount control logic 208 that is more fully described in conjunction withFIG. 7 . - The nor
gate 336 is coupled to a norgate 338. The norgate 338 is coupled to thedelay 310. A momentary contact button 340 (such as the start button 106) is coupled to the norgate 338. Themomentary contact button 340 is coupled to thecounter 328. Themomentary contact button 340 and norgates repeat logic 210 that is more fully described in conjunction withFIG. 8 . -
FIG. 4 is a block diagram of an embodiment of variabledelay generator logic 202. Theclock 302 produces a clock signal cp302 that is applied to the count input of thecounter 304. The clock signal cp302 is also applied to thedivider 306. The divider produces a lower-frequency clock signal cp306 (for example, by producing a signal for every seven times cp302 is applied). The signal cp306 is applied to the count input ofcounter 308. Thedelay 310 receives a start signal from the start/repeat logic and asserts a signal o310 for a predetermined interval after receipt of the start signal. The signal o310 disables the count enable ofcounter 308, while enabling the load value input of thecounter 308. When the load value input is enabled, the count value ofcounter 304 is loaded via output count304 to thecounter 308 as an initial count value and latched when the load value input goes low. Thecounter 308 then begins counting up from the loaded initial value (which varies unpredictably based upon when the start signal was received) according to the frequency of signal cp306. Once thecounter 308 reaches its count limit, it produces an output signal tc308. -
FIG. 5 is a block diagram of an embodiment of output pulse control logic. The set input of theFF 314 receives the signal o310 from thedelay 310. TheFF 314 has outputs Q and −Q (Q bar) to provide signals q314 and −q314, respectively. The signal −q314 is applied to an input of the norgate 312. The other input of the norgate 312 is coupled to receive the signal tc308. The output signal o312 of the norgate 312 is applied to the set input of theFF 318. The output signal of the norgate 316 is applied to the reset input of theFF 318. TheFF 318 has Q and −Q outputs to provide signals q318 and −q318, respectively. -
FIG. 6 is a block diagram of an embodiment of duration control logic. Theswitch 322 receives the count value count304 from thecounter 304. Theswitch 322 receives a coded value of a preset presentation time selection from thecoder 324. The coder receives the preset time setting from theanalog switch 326, which comprises a set of selectable fixed values for the presentation duration, and encodes the setting. For example, theanalog switch 326 may assert a signal on one of eight outputs, depending on the setting, and thecoder 324 may form a three bit value to represent the output of theanalog switch 326. A signal from theanalog switch 326 is applied to the select input sel322 of theswitch 322, to cause theswitch 322 to select either the time value provided from thecoder 324, or the value of signal count304. The value selected by theswitch 322 is provided to thecounter 320. Thecounter 320 loads this value as an initial count value when the q314 signal applied at input load320 is asserted and latched when the signal applied at load320 goes low. The signal −q318 is applied to the count enable input ce320 of thecounter 320. The signal cp306 is applied to the count input of thecounter 320. When −q318 is low, the count ofcounter 320 increments at a rate determined by the frequency of cp306. When thecounter 320 reaches its count limit, it outputs a signal tc320. -
FIG. 7 is a block diagram of an embodiment ofcount control logic 208. Theswitch 330 receives the count value count304 from thecounter 304. Theswitch 330 receives a coded value of a preset presentation count selection from thecoder 332. The coder receives the preset count setting from theanalog switch 334, which comprises a set of selectable fixed values for the presentation count, and encodes the setting. For example, theanalog switch 334 may assert a signal on one of eight outputs, depending on the setting, and thecoder 332 may form a three bit value to represent the output of theanalog switch 334. A signal from theanalog switch 334 is applied to the select input sel330 of theswitch 330, to cause theswitch 330 to select either the count value provided from thecoder 332, or the value of signal count304. The value selected by theswitch 330 is provided to thecounter 328. Thecounter 328 loads this value as a count target value when a signal is asserted at input load328, and latches the value when load328 goes low. The output q3_328 is applied to the count enable input ce328 of thecounter 328. The signal q318 is applied to the count input cp328 of thecounter 328. The count ofcounter 328 increments each time q318 is asserted, e.g. each time there is a target presentation. When thecounter 328 reaches its count target, it asserts a signal at q3_328. - An arrangement similar to that shown in
FIGS. 6 and 7 may be provided to select from a set of selectable fixed times for the interval between when the start signal is received by thedelay 310 and when the signal tc308 is produced to cause target presentation. For example, the initial count value loaded to thecounter 308 may be selected using a switch coupled through a coder to an analog switch, as either the value of count304 or a value corresponding to the setting of the analog switch. -
FIG. 8 is a block diagram of an embodiment of start/repeat logic 210 to repeatedly generate the start signal according to the presentation count determined by the count control logic. The signals q3_328 and tc320 are applied to the inputs of the norgate 336. The output signal o336 of the norgate 336 is applied along with the output of themomentary contact button 340 to the inputs of the norgate 338. When themomentary contact button 340 is pressed, a high signal VCC is applied to an input of the norgate 338, forcing the output signal o338 (start signal—seeFIG. 4 ) low. -
FIG. 9 is a flow chart of an embodiment of a process to provide a variable delay before target presentation. At 905 a first clock signal is applied to a first counter. At 910 a second clock signal of different frequency than the first clock signal is applied to a second counter. At 915 a start signal is received. At 920 the start signal causes the second counter to load an initial count from the first counter. At 925 second counter counts up beginning from the loaded initial count. At 930 the second counter generates a signal upon reaching its count limit value. At 935 the signal from the second counter causes target presentation. At 940 the target presentation starts athird counter 940, and at 945 the process concludes. -
FIG. 10 is a flow chart of an embodiment of a process of providing a selection of pre-selected or unpredictable target presentation time. If at 1005 the “random” setting for presentation time has not been selected, the third counter (seeFIG. 9 ) loads an initial count from a fixed setting at 1010. If at 1005 the “random” setting for presentation time has been selected, the third counter loads the initial count from the first counter at 1015. At 1020 the third counter generates a signal upon reaching its count limit value. At 1025 this signal ends target presentation, and at 1030 the process concludes. -
FIG. 11 is a flow chart of an embodiment of a process of providing a selection of pre-selected or unpredictable target presentation count. If at 1105 the “random” setting for presentation count has not been selected, a fourth counter loads an initial count from a fixed setting at 1110. If at 1105 the “random” setting for presentation count has been selected, the fourth counter loads an initial count from first counter at 1115. At 1120 the fourth counter generates a signal upon reaching its count limit value. At 1125 this signal ends target presentation count, and at 1130 the process concludes. -
FIGS. 12-15 are timing diagrams of an embodiment of signals involved in providing a target presentation delay and target presentation time. - In
FIG. 12 , target presentation is initiated by a start signal produced by operation of thestart button 106 or by other means. At t0 the start signal transitions low. At t1 the delay output o310 transitions high and remains high for a predetermined delay interval I0. At t3 o310 transitions low. The high-going pulse produced by thedelay 310 may be of similar or dissimilar width from the start pulse, but is typically dissimilar. At t4, after avariable delay period 11 determined by the initial count loaded intocounter 308, the clock frequency applied to 308, and possibly other factors, thecounter 308 reaches its count limit value and tc308 transitions low. - In
FIG. 13 the asserted signal o310 is applied to the set input ofFF 314 at t5, causing −q314 to transition low at t6 (after a short delay inherent in the FF 314). At t7 tc308 also transitions low ascounter 308 reaches its count limit value. Both inputs to norgate 312 are now low, and thus at t8 the output signal o312 of the norgate 312 transitions high. At t9 tc308 transitions high, forcing o312 to transition low at t10. - In
FIG. 14 , the assertion of o310 (the output of delay 310) causes q314 (the Q output of FF 314) to transition high at t11. At t12 the output o312 of the norgate 312 transitions high ascounter 308 reaches its count limit value. This causes the Q output q318 ofFF 318 to transition high at t13, and −q318 to transition low, and results in target presentation to the shooter. Signal q318 is applied to resetFF 314, so that q314 transitions low at t14. - In
FIG. 15 , at t15 thecounter 320 reaches its count limit value and tc320 transitions low. Signal tc320 is applied to both inputs of norgate 316, so that at t16 the output o316 of norgate 316 transitions high. The signal o316 is applied to reset theFF 318, so that at t17—q318 transitions high and q318 transitions low. -
FIG. 16 is a timing diagram of an embodiment of signals involved in providing a target presentation count. A target presentation is made during the time that q318 is high. At t20 thetarget presentation counter 320 reaches its count limit value, a value that may be loaded either from theswitch 334 selection, or from the count value count304 of counter 304 (for unpredictable presentation counts). At t20 tc320 transitions low, q318 transitions low (ending the target presentation), and the output o336 of norgate 336 transitions high because both inputs tc320 and q3_328 are low. This causes the start signal to transition low for the time that tc320 (and hence 0336) are low, e.g. another start pulse is created. This process is repeated at t21 when the second target presentation completes. Each time the target presentation completes, the count ofcounter 328 is incremented, until at t22 thecounter 328 reaches its preset count value, and q3_328 transitions high. At t23 thepresentation time counter 320 once again reaches its limit count, and tc320 transitions low. However, this time q3_328 is high, so that o336 is not asserted, and no start pulse is produced. Thus, target presentation concludes after three presentations.
Claims (11)
1. An apparatus comprising:
variable delay generator logic configured to generate a signal to cause the presentation of a target an unpredictable time interval after receiving a start signal;
presentation duration control logic configured to cause the target presentation to continue for one of an unpredictable presentation time interval determined by the variable delay generator logic, and a selectable predetermined time interval; and
presentation count control logic configured to cause target presentation to repeat for one of an unpredictable presentation count determined by the variable delay generator logic, and a selectable predetermined presentation count.
2. The apparatus of claim 1 , further comprising:
the variable delay generator logic comprising a first counter configured to count at a first rate, and a second counter configured to count at a second rate starting from an initial count value provided by the first counter, wherein the second counter generates the signal to cause the presentation of the target an unpredictable time interval after receiving the start signal.
3. The apparatus of claim 2 , the presentation duration control logic comprising a third counter and configured to provide to the third counter an initial count value determined from one of the variable delay generator logic and an analog switch.
4. The apparatus of claim 3 , further comprising:
the presentation duration control logic configured to provide to the third counter an initial count value provided by the first counter.
5. The apparatus of claim 2 , the presentation count control logic comprising a third counter and configured to provide to the third counter a target presentation count determined from one of the first counter of the variable delay generator logic and an analog switch.
6. The apparatus of claim 1 , further comprising:
the variable delay generator logic configured to generate the signal to cause the presentation of the target after an interval of time comprising a predetermined delay interval and an unpredictable delay interval.
7. The apparatus of claim 1 , further comprising:
start/repeat logic to repeatedly generate the start signal a number of times determined by the presentation count control logic.
8. A target controller comprising:
a first counter configured to count at a first rate;
a second counter configured to count at a second rate;
the first and second counter cooperating to determine a delay between receipt of a start signal and target presentation;
a third counter to determine a target presentation duration; and
a fourth counter to determine a target presentation count.
9. The target controller of claim 8 , configured to provide the third counter with an initial count value selected from one of the count value of the first counter and a set of selectable fixed values.
10. The target controller of claim 8 , configured to provide the fourth counter with an initial count value selected from one of the count value of the first counter and a set of selectable fixed values.
11. A target controller comprising:
a first counter configured to count at a first rate;
a second counter configured to count at a second rate;
the first and second counter cooperating to determine a delay between receipt of a start signal and target presentation;
a presentation duration control having a setting determined by one of the first and second counters; and
a presentation count control having a setting determined by one of the first and second counters.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/789,767 US20050189718A1 (en) | 2004-02-27 | 2004-02-27 | Target control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/789,767 US20050189718A1 (en) | 2004-02-27 | 2004-02-27 | Target control system |
Publications (1)
Publication Number | Publication Date |
---|---|
US20050189718A1 true US20050189718A1 (en) | 2005-09-01 |
Family
ID=34887367
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/789,767 Abandoned US20050189718A1 (en) | 2004-02-27 | 2004-02-27 | Target control system |
Country Status (1)
Country | Link |
---|---|
US (1) | US20050189718A1 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3933354A (en) * | 1974-09-18 | 1976-01-20 | Brunswick Corporation | Reflex testing amusement device |
US4461477A (en) * | 1982-06-14 | 1984-07-24 | Stewart Eddie A | Method and apparatus for improving the performance of a batter |
US6188742B1 (en) * | 1997-10-06 | 2001-02-13 | Theresa Jean Schousek | Event counter and method for driving a circuit device |
-
2004
- 2004-02-27 US US10/789,767 patent/US20050189718A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3933354A (en) * | 1974-09-18 | 1976-01-20 | Brunswick Corporation | Reflex testing amusement device |
US4461477A (en) * | 1982-06-14 | 1984-07-24 | Stewart Eddie A | Method and apparatus for improving the performance of a batter |
US6188742B1 (en) * | 1997-10-06 | 2001-02-13 | Theresa Jean Schousek | Event counter and method for driving a circuit device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4231106A (en) | Performance monitor apparatus and method | |
US20060168456A1 (en) | Method and apparatus to generate circuit energy models with multiple clock gating inputs | |
CN111538475B (en) | System and method for constructing true random number generator based on FPGA | |
US4255795A (en) | Programmable binary correlator | |
GB2429076A (en) | Time accumulator | |
US3323123A (en) | Range simulator for providing a controlled delay between an input trigger and an output pulse | |
US20050189718A1 (en) | Target control system | |
KR100594315B1 (en) | Multiple pulse generator | |
US20110050313A1 (en) | Methods and systems related to a configurable delay counter used with variable frequency clocks | |
CN102063785A (en) | Method for automatically emitting infrared remote control signals and system thereof | |
US20140035648A1 (en) | Timer match dithering | |
US7567137B2 (en) | Programmable oscillators for high frequency clock generation for simulation environments | |
US4684261A (en) | Method for entering a switching program into an electronic timer and arrangement for implementing the method | |
RU2613523C1 (en) | Device for solving appointment problems | |
CN103095254A (en) | Pulse slide change signal generation circuit based on field programmable gate array (FPGA) | |
CN108809322B (en) | Independent keyboard scanning and coding method | |
CN112748973B (en) | Keyboard mode switching system and method | |
RU2276456C1 (en) | Rectangular pulse generator | |
SU907553A1 (en) | Device for simulating process of control of reserves | |
RU2028642C1 (en) | Line voltage dip simulator | |
US6430250B1 (en) | Rapid triggering digital timer | |
KR940001828Y1 (en) | Signal generating circuit | |
RU2010323C1 (en) | Device for static modelling condition of test object | |
SU951318A2 (en) | Discrete communication channel simulator | |
SU1003025A1 (en) | Program time device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |