CN111538475B

CN111538475B - System and method for constructing true random number generator based on FPGA

Info

Publication number: CN111538475B
Application number: CN202010219354.0A
Authority: CN
Inventors: 蒋剑飞; 陈杨兵; 王琴; 贺光辉; 景乃锋; 绳伟光
Original assignee: Shanghai Jiaotong University
Current assignee: Shanghai Jiaotong University
Priority date: 2020-03-25
Filing date: 2020-03-25
Publication date: 2023-06-23
Anticipated expiration: 2040-03-25
Also published as: CN111538475A

Abstract

The invention provides a true random number generator construction system and method based on an FPGA, comprising the following steps: the device comprises a control unit, an entropy source generation module, an entropy extractor, an entropy source decoder, a post-processing module and a random number generator; the control unit is respectively connected with the entropy source generation module, the entropy extractor, the entropy source decoder and the post-processing module; the control unit can perform initialization setting of the random number generator; the random number generator needs to externally provide a clock unit, and the output of the clock unit is used as an operating clock of the random number generator; the entropy source of the random number generator is from an entropy source generation module; the clock jitter signal generated by the self-timing oscillation ring which is mutually coupled in the entropy source generation module is used as an entropy source of the random number generator. The invention is more stable and has better robustness than the traditional inverter oscillation ring or the self-timing oscillation ring without coupling, and the true random number generator can work relatively stably when the voltage or the environment changes.

Description

System and method for constructing true random number generator based on FPGA

Technical Field

The invention relates to the field of electronic circuits, in particular to a system and a method for constructing a true random number generator based on an FPGA.

Background

The random number is used to generate security keys, operating system protocols, mobile device IDs, digital signature verification, etc., required by the security system. The random number generator has wide application in analog simulation, data encryption, system security, statistical analysis, etc. and these systems have certain requirement on the quality and production speed of random numbers. Random numbers are classified into pseudo random numbers and true random numbers, wherein the true random numbers have high quality, and the security of a system comprising the true random number generator is higher. Because Field Programmable Gate Arrays (FPGAs) are very commonly applied to current electronic systems, FPGA-based true random number generating circuits have important application prospects. The true random number generating circuit in the FPGA comprises: the entropy source, sampling quantization and post-processing. The entropy source in the FPGA mainly comes from jitter of an oscillator, a metastable state circuit and the like, and the main problem of the current generating circuit based on the entropy source is low data generation rate, sensitivity to working environment, voltage and process variation and low reliability.

Patent document CN103502931B discloses a random number generator for providing a random number and/or a combination of random numbers and/or a matrix of random numbers. According to the present invention, the random number generator includes: a monitoring device for monitoring at least one game of a skill/skill-requiring sports facility on which at least one participant may play a skill/skill-requiring sports game that provides at least one game outcome, wherein the monitoring device comprises game outcome determination means for determining the game outcome; and a determining device for determining a random number and/or a combination of random numbers and/or a matrix of random numbers from the one or more determined game results. The patent still has room for improvement in terms of security and data generation rate.

Disclosure of Invention

Aiming at the defects in the prior art, the invention aims to provide a true random number generator construction system and method based on an FPGA.

The invention provides a true random number generator construction system based on an FPGA, which comprises: the device comprises a control unit, an entropy source generation module, an entropy extractor, an entropy source decoder, a post-processing module and a random number generator; the control unit is respectively connected with the entropy source generation module, the entropy extractor, the entropy source decoder and the post-processing module; the control unit can perform initialization setting of the random number generator, and after initialization is finished, the random number generator is controlled to enter a normal working mode; the random number generator needs to externally provide a clock unit, and the output of the clock unit is used as an operating clock of the random number generator; the entropy source of the random number generator is from an entropy source generation module; the clock jitter signal generated by the self-timing oscillation ring which is mutually coupled in the entropy source generation module is used as an entropy source of the random number generator.

Preferably, the self-timing oscillation rings are coupled by m n-level self-timing oscillation rings, so as to generate oscillation rings and clock signals with different performances; wherein m and n are both adjustable numbers; n is a positive integer greater than or equal to 3, and m is a positive integer greater than or equal to 2.

Preferably, the n-level self-timing oscillation loop is composed of n multi-input Muller units (Muller C_element); the miller unit is implemented by a LUT in the FPGA.

Preferably, each miller unit of the m n-stage coupled self-timed oscillation rings fixes one LUT.

Preferably, the multi-input miller unit Muller c_element includes: multiple sets of inputs of the same function. Wherein at least one set of inputs of the same function is used to generate an oscillating signal and at least one set of inputs of the same function is used to couple with other n-stage self-timed oscillating rings.

Preferably, the m n-stage coupled self-timed oscillation rings employ uniformly spaced propagation modes.

Preferably, the clock signals output by each of the m n stages of coupled self-timing oscillation loops are respectively connected with an entropy extractor.

Preferably, the entropy extractor includes: delay chains in the FPGA and flip-flop cells in the FPGA; delay chains in the FPGA respectively delay each level of jitter output signals of a true random number generator building system based on the FPGA; and the trigger unit in the FPGA samples signals in the delay chain under the control of the same clock, and then transmits a numerical sequence obtained by sampling the signals to the entropy source decoder.

Preferably, the delay chain in the FPGA is implemented by carry-ahead cells in the FPGA; the entropy source decoder decodes and outputs a one-bit random number according to the sequence of the input data, and sends the obtained random number to the post-processing module after performing exclusive OR operation; the post-processing module rectifies the input random number to obtain a random number sequence; the random number is a binary random number, and the random number sequence is a binary random number sequence.

According to the method for constructing the true random number generator based on the FPGA, the true random number generator based on the FPGA is constructed by adopting a system for constructing the true random number generator based on the FPGA.

Compared with the prior art, the invention has the following beneficial effects:

1. the self-timing oscillation ring is used as an entropy source of the true random number generator, so that the self-timing oscillation ring is more stable and better in robustness than the traditional inverter oscillation ring or the self-timing oscillation ring without coupling, and the true random number generator can work relatively stably when voltage or environment changes.

2. The invention adopts the coherent signal generated by internal oscillation as the sampling signal, and does not need external resources to provide sampling clocks.

3. In the invention, the circuit structure of the true random number generator is simpler, the occupied resources in the FPGA are fewer, the true random number generator can be transplanted on different platforms, and the application range is wider.

4. The true random number generator of the invention not only can generate random numbers at the speed which is a plurality of times of the oscillation frequency, but also can ensure the quality of the random numbers.

Drawings

Other features, objects and advantages of the present invention will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:

fig. 1 is a schematic diagram of the structure of the FPGA-based true random number generator of the present invention.

Fig. 2 is a schematic circuit structure of m n-level self-timing oscillation rings according to an embodiment of the present invention.

Fig. 3 is a schematic diagram of a single stage structure of a coupled self-timed oscillator loop in an embodiment of the present invention.

FIG. 4 is a truth representation of a single stage coupled self-timed oscillator loop in an embodiment of the present invention.

Fig. 5 is a schematic diagram of an implementation of a miller unit in an FPGA according to an embodiment of the invention.

Fig. 6 is a schematic diagram of a carry unit of a fast carry chain in an entropy extraction module according to an embodiment of the invention.

Fig. 7 is a general schematic diagram of an entropy extractor and an entropy source decoder in an embodiment of the present invention.

Fig. 8 is a schematic circuit diagram of an implementation on an ASIC in an embodiment of the invention.

Fig. 9 is a schematic diagram illustrating a post-processing module for performing deskewing on a random number sequence generated by an entropy source decoder according to an embodiment of the present invention.

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the present invention, but are not intended to limit the invention in any way. It should be noted that variations and modifications could be made by those skilled in the art without departing from the inventive concept. These are all within the scope of the present invention.

As shown in fig. 1 to 9, the true random number generator construction system based on FPGA according to the present invention includes: the device comprises a control unit, an entropy source generation module, an entropy extractor, an entropy source decoder, a post-processing module and a random number generator; the control unit is respectively connected with the entropy source generation module, the entropy extractor, the entropy source decoder and the post-processing module; the control unit can perform initialization setting of the random number generator, and after initialization is finished, the random number generator is controlled to enter a normal working mode; the random number generator needs to externally provide a clock unit, and the output of the clock unit is used as an operating clock of the random number generator; the entropy source of the random number generator is from an entropy source generation module; the clock jitter signal generated by the self-timing oscillation ring which is mutually coupled in the entropy source generation module is used as an entropy source of the random number generator.

Preferably, the multi-input miller unit Muller c_element includes: multiple groups of inputs with the same function; wherein at least one set of inputs of the same function is used to generate an oscillating signal and at least one set of inputs of the same function is used to couple with other n-stage self-timed oscillating rings.

Based on the Xilinx KCU116 FPGA design, the method provided by the invention can be realized on other FPGAs.

Specifically, in one embodiment, as shown in fig. 1, in a true random number generator implemented on an FPGA, the random number generator is composed of a control unit, an entropy source generation module, an entropy extractor, an entropy source decoder, and a post-processing circuit. The control unit is used for initializing the whole random number generator, and controlling the random number generator to enter a normal working mode after the initialization is finished. In general, the random number generator requires an external supply of a clock unit, which outputs as an operating clock of the random number generator. Alternatively, the output of an external PLL is used as the operating clock for the random number generator.

As shown in fig. 2 and 3, one embodiment of the coupled self-timed oscillator loop is as follows: it is composed of m n stages of miller units, each stage is composed of a four-input miller unit and an inverter, wherein n is a positive integer of 3 or more, and m is a positive integer of 2 or more.

As shown in fig. 3 and 4, the miller unit embodiment is as follows: the output of the inverter is connected to one input of the miller unit, the inputs of the inverter are r1 and r2, the other two inputs of the miller unit are f1 and f2, and the output is c. The input r1 of each inverter stage is connected to the output ci+1 of the next stage, and the other input r2 is connected to the output ci+1 of the next stage of the next self-timed oscillation ring. In order to set the initial state of the coupled self-timing oscillation loop, an init signal is added to each stage, and when the init signal is valid, the output of the miller unit is the value of init. In the FPGA, the miller unit is implemented by using a 6-input LUT, as shown in fig. 3, f11, f12, r11 and r12 are four inputs of the miller unit, the init signal is a control signal, and out is an output of the miller unit, and the structure is easy to implement in the FPGA.

When the number of inputs of the LUT is greater than 6, the number of inputs of the miller unit may be greater, as shown in fig. 4, so as to have a manner of implementing more coupling.

In a coupled self-timed oscillator loop, there are a bubble and a token. If the output Ci in the i-stage of the oscillator loop is not equal to the output Ci-1 of the previous stage, it is indicated that there is a token in the i-stage. If the output Ci in the i-stage of the oscillator loop is equal to the output Ci-1 of the previous stage, it is indicated that there is a bubble in the i-stage. The coupled self-timed oscillation loop can produce autonomous oscillations that require three conditions to be met: (1) the number n of oscillation ring stages is more than or equal to 3; (2) the number of bubbles in the oscillation ring should be 1 or more; (3) the number of tokens in the oscillation ring is a positive even number.

By adjusting the initial state of the oscillation ring, the oscillation mode of the oscillation ring can be set. The oscillator ring has two modes of propagation: uniformly spaced propagation modes and burst propagation modes. If the number of bubbles and the number of tokens differ less in the initial state of the oscillator ring, then the greater the Charles effect in the Miller unit, the higher the output clock frequency containing jitter, and the oscillator ring is in a uniformly spaced propagation mode. If the number of bubbles and the number of token differ more in the initial state of the oscillation ring, the smaller the Charles effect in the Miller unit is, the lower the frequency of the output clock is, and the oscillation ring is in a burst propagation mode. Both modes can produce the required entropy source in a true random number generator, but with the same number of stages, the frequency of the uniformly spaced propagation modes is higher.

Fig. 5 is an implementation of a miller unit in a coupled self-timed oscillation loop using a LUT in an FPGA, we use a 6-input LUT, where f11, f12, r11, and r12 are inputs to the miller unit, init is a control signal to the miller unit, and out is an output to the miller unit. Fixing each stage coupled to the self-timed oscillator ring as one LUT facilitates later fixing the position of each LUT when laying out and wiring.

The entropy extractor is composed of a fast delay chain formed by carrier 4 in the FPGA. The CARRY4 cells are distributed in the slice of the FPGA, and in order to ensure that the distance from the output of each stage of the oscillator to its corresponding fast CARRY chain is approximately the same, the LUT of each stage of the oscillator needs to be placed in the vicinity of the corresponding CARRY chain. These carry bits are input into the D flip-flops, the clock control terminal of each D flip-flop is connected to the same sampling clock, sampled and output by the D flip-flop, and the sampling schematic diagram is shown in fig. 6.

The entropy source decoder is used for decoding the 4-bit data sequence generated by the entropy extractor, and decoding a one-bit random number. The data sequence obtained from the entropy source decoder is exclusive-ored and then sent to the post-processing module, and the overall diagram of the entropy extractor and the entropy source decoder is shown in fig. 7.

The entropy extractor and the entropy source decoder can be realized by only 1 CARRY4 unit, 4D triggers and 1 LUT unit in total in the FPGA, compared with other proposed entropy source extraction circuits, the hardware consumption is greatly reduced, the entropy extractor and the entropy source decoder are convenient to transplant on different platforms, and the realization circuit of the entropy extractor and the entropy source decoder on the ASIC is shown in FIG. 8.

The post-processing module 5 shown in fig. 9 is configured to rectify the random number sequence generated by the entropy source decoder. The exclusive or post-processing method is adopted, the design of the method is simpler, the deviation in the random number sequence can be effectively eliminated, and the output speed of the random number is not influenced.

The delay between adjacent stages in carrier 4 in the Xilinx KCU116 FPGA is about 30ps to 40ps, so theoretically, a valid random number can be obtained as long as the period of the sampling clock is greater than the delay between adjacent stages in carrier 4. In a practical circuit, the sampling frequency may be relatively reduced due to other factors. In the embodiment of the invention, the sampling frequency is 200MHz, the random number output rate is 200Mbps, and the rate can be increased optionally, so that the method has a great advantage compared with other true random number generators.

In the invention, the true random number generator occupies 22 slices in the Xilinx KCU116 FPGA, wherein the entropy source module occupies 7 slices, the entropy extraction module occupies 7 slices, and the edge detector and the post-processing module occupy 8 slices. In the Xilinx KCU116 FPGA 1 slice includes 8 LUTs, 3 MUXs, 1 CARRY8 and 8D flip-flops.

The random numbers generated in the Xilinx KCU116 FPGA are transmitted to a computer port from the FPGA through a UART program, then the random numbers are output in batches by using a serial port debugging assistant, 106 data are finally output, and the quality of the random numbers is tested by using NIST random number evaluation software.

The NIST test includes 15 test items that can test the quality of the binary sequence generated by the random number generator. Some test items require a minimum of 106 data, so we output a minimum of 106 data. The combined p-value returned after the test is completed should be greater than 0.01, which indicates that this test item passed the test.

NIST Test	P-value	Result
			Frequency	0.904351	PASS
Block Frequency	0.821576	PASS
			Runs	0.747345	PASS
Longest Runs	0.908415	PASS
			Rank	0.931367	PASS
FFT	0.930626	PASS
			Non-overlapping Template	0.822367	PASS
Overlapping Template	0.973996	PASS
			Approximate Entropy	0.907300	PASS
Serial	0.664950	PASS
			Linear Complexity	0.753142	PASS
Cumulative Sums	0.990908	PASS
			Random Excursions	0.813107	PASS
Random Excursions Variant	0.850644	PASS
			Universal	0.745105	PASS

The NIST test results of random numbers generated by the true random number generator construction system based on the FPGA are shown in the table, each test result in the table has a comprehensive p value, and the p values of all items are larger than 0.01 and pass the test.

The invention can not only generate high-quality random numbers, but also generate random numbers at a high rate. The true random number generator occupies fewer resources of the FPGA, can be conveniently integrated into an application system, is particularly important to the application of the true random number generator in the aspects of data encryption, statistical analysis, information communication and the like, can further reduce the size of the device, improves the performance of the device, and further improves the safety of the system.

The self-timing oscillation ring is used as an entropy source of the true random number generator, so that the self-timing oscillation ring is more stable and better in robustness than the traditional inverter oscillation ring or the self-timing oscillation ring without coupling, and the true random number generator can work relatively stably when voltage or environment changes; the invention adopts the coherent signal generated by internal oscillation as the sampling signal, and does not need external resources to provide a sampling clock; in the invention, the circuit structure of the true random number generator is simpler, the occupied resources in the FPGA are fewer, the true random number generator can be transplanted on different platforms, and the application range is wider; the true random number generator of the invention not only can generate random numbers at the speed which is a plurality of times of the oscillation frequency, but also can ensure the quality of the random numbers.

Those skilled in the art will appreciate that the invention provides a system and its individual devices, modules, units, etc. that can be implemented entirely by logic programming of method steps, in addition to being implemented as pure computer readable program code, in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. Therefore, the system and various devices, modules and units thereof provided by the invention can be regarded as a hardware component, and the devices, modules and units for realizing various functions included in the system can also be regarded as structures in the hardware component; means, modules, and units for implementing the various functions may also be considered as either software modules for implementing the methods or structures within hardware components.

In the description of the present application, it should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientations or positional relationships illustrated in the drawings, merely to facilitate description of the present application and simplify the description, and do not indicate or imply that the devices or elements being referred to must have a specific orientation, be configured and operated in a specific orientation, and are not to be construed as limiting the present application.

The foregoing describes specific embodiments of the present invention. It is to be understood that the invention is not limited to the particular embodiments described above, and that various changes or modifications may be made by those skilled in the art within the scope of the appended claims without affecting the spirit of the invention. The embodiments of the present application and features in the embodiments may be combined with each other arbitrarily without conflict.

Claims

1. A true random number generator building system based on an FPGA, comprising: the device comprises a control unit, an entropy source generation module, an entropy extractor, an entropy source decoder, a post-processing module and a random number generator;

the control unit is respectively connected with the entropy source generation module, the entropy extractor, the entropy source decoder and the post-processing module;

the control unit can perform initialization setting of the random number generator;

the random number generator needs to externally provide a clock unit, and the output of the clock unit is used as an operating clock of the random number generator;

the entropy source of the random number generator is from an entropy source generation module;

the clock jitter signal generated by one self-timing oscillation ring which is mutually coupled in the entropy source generation module is used as an entropy source of the random number generator;

the delay chain in the FPGA is realized by a carry-ahead unit in the FPGA;

the entropy source decoder decodes and outputs a one-bit random number according to the sequence of the input data, and sends the obtained random number to the post-processing module after performing exclusive OR operation;

the post-processing module rectifies the input random number to obtain a random number sequence;

the random number is a binary random number, and the random number sequence is a binary random number sequence.

2. The FPGA-based true random number generator building system of claim 1, wherein the mutually coupled self-timed oscillation loops are coupled by m n-stage self-timed oscillation loops;

wherein m and n are both adjustable numbers;

n is a positive integer greater than or equal to 3, and m is a positive integer greater than or equal to 2.

3. The FPGA-based true random number generator building system of claim 2, wherein the n-stage self-timed oscillation loop is comprised of n multiple-input miller units;

the miller unit is implemented by a LUT in the FPGA.

4. The FPGA-based true random number generator building system of claim 3, wherein each miller cell of the m n-stage coupled self-timed oscillation loops fixes one LUT.

5. The FPGA-based true random number generator building system of claim 4,

the multi-input miller unit comprises: multiple groups of inputs with the same function;

wherein at least one set of inputs of the same function is used to generate an oscillating signal and at least one set of inputs of the same function is used to couple with other n-stage self-timed oscillating rings.

6. The FPGA-based true random number generator building system of claim 2, wherein the m n-stage coupled self-timed oscillation loops employ uniformly spaced propagation modes.

7. The FPGA-based true random number generator building system of claim 2, wherein the clock signal output by each of the m n stages of coupled self-timed oscillation loops is separately coupled to an entropy extractor.

8. The FPGA-based true random number generator building system of claim 1, wherein the entropy extractor comprises: delay chains in the FPGA and flip-flop cells in the FPGA;

delay chains in the FPGA respectively delay each level of jitter output signals of a true random number generator building system based on the FPGA;

and the trigger unit in the FPGA samples signals in the delay chain under the control of the same clock, and then transmits a numerical sequence obtained by sampling the signals to the entropy source decoder.

9. An FPGA-based true random number generator construction method, which is characterized in that the FPGA-based true random number generator construction system according to any one of claims 1-8 is adopted to construct an FPGA-based true random number generator, so that the quality of random numbers and the generation speed of random numbers are improved.